STM6503VEAADG6F ,Dual push-button smart reset with user-adjustable setup delaysBlock diagram - STM6505 . . 8Figure 5. Single-button Smart Reset typical hookup . . . . . ..
STM6520AQRRDG9F ,Dual push-button smart reset with push-button controlled output delayBlock diagram . . . . 7Figure 4. RST1 output used for microcontroller reset . . . . . 8F ..
STM6522AAAADG6F ,dual push-button smart reset with capacitor-adjustable setup delayBlock diagram . . . . 6Figure 4. Single-button Smart Reset™ typical hookup . . . . 7Figu ..
STM6600CS25DM6F ,Smart push-button on/off controller with smart reset and power-on lockoutBlock diagram . . . . 8Figure 7. Successful power-up on STM6600 (PB released prior to t expi ..
STM6601AQ2BDM6F ,Smart push-button on/off controller with Smart ResetTM and power-on lockoutApplications• Operating voltage 1.6 V to 5.5 V• Portable devices• Low standby current of 0.6 µA™ • ..
STM6601AU2DDM6F ,Smart push-button on/off controller with Smart ResetTM and power-on lockoutAbsolute maximum ratings . 38Table 4. Operating and AC measurement conditions . . . . 39Ta ..
SY55851AUKI , 2.5V/3V, 3.0GHz CML AnyGate ANY LOGIC WITH 50ohm or 100ohm OUTPUTS
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SY55851UKI , 2.5V/3V, 3.0GHz CML AnyGate ANY LOGIC WITH 50ohm or 100ohm OUTPUTS
SY55852UKG , D FLIP-FLOP
SY55854UYI , 2 X 2 PROTECTION CROSSPOINT SWITCH
STM6503VEAADG6F
Dual push-button smart reset with user-adjustable setup delays
February 2011 Doc ID 16101 Rev 6 1/29
STM6502, STM6503
STM6504, STM6505Dual push-button Smart ResetTM with user-adjustable setup delays
Features Dual Smart Reset push-button inputs with
extended reset setup delay Adjustable Smart Reset setup delay (tSRC):
by external capacitor or three-state logic
(product options): tSRC = 2, 6, 10 s (min.) Power-on reset Single RST output, active-low, open-drain Factory-programmable thresholds to monitor
VCC in the range of 1.575 to 4.625 V typ. Operating voltage 1.0 V (active-low output
valid) to 5.5 V Low supply current Operating temperature:
industrial grade –40 °C to +85 °C TDFN8 package: 2 mm x 2 mm x 0.75 mm RoHS compliant
Applications Mobile phones, smartphones e-books MP3 players Games Portable navigation devices Any application that requires delayed reset
push-button(s) response for improved system
stability
Table 1. Device summary Contact local ST sales office for availability.
Contents STM6502, STM6503, STM6504, STM65052/29 Doc ID 16101 Rev 6
Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.1 Smart Reset devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.2.1 Power supply (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.2.2 Ground (VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.2.3 Primary Smart Reset input (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.2.4 Secondary Smart Reset input (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.2.5 Edge-triggered Smart Reset input (SRE pin) – STM6504 only . . . . . . . 11
1.2.6 Adjustable delay of Smart Reset input (SRC pin) – STM6502
and STM6505 only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2.7 Programmable Smart Reset input delay (TSR pin) – STM6503
and STM6504 only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.2.8 Reset output (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.2.9 Battery monitoring input (VBAT) – STM6505 only . . . . . . . . . . . . . . . . . 12
1.2.10 Battery low detect output (BLD) – STM6505 only . . . . . . . . . . . . . . . . . 12
Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
STM6502, STM6503, STM6504, STM6505 List of tables
Doc ID 16101 Rev 6 3/29
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. tSRC programmed by an ideal external capacitor – STM6502 and STM6505 . . . . . . . . . . 11
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5. Operating and measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 7. VCC voltage thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 8. TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm pitch package mechanical data . . . . . . . . . . . . . 21
Table 9. Parameter for landing pattern - TDFN – 8-lead 2 x 2 mm package . . . . . . . . . . . . . . . . . . 22
Table 10. Carrier tape dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 11. Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 12. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 13. Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 14. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
STM6502, STM6503, STM6504, STM6505 List of figures
Doc ID 16101 Rev 6 4/29
List of figures
Figure 1. Logic diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Block diagram - STM6502, STM6503, STM6504. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Block diagram - STM6505 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. Single-button Smart Reset typical hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. Dual-button Smart Reset typical hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. STM6502, STM6503 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 8. STM6504 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 9. STM6505 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 10. Supply current (ICC ) vs. temperature (STM6505). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 11. Smart Reset delay (tSRC ) vs. temperature, CSRC = 0.62 µF (STM6505) . . . . . . . . . . . . . . 13
Figure 12. Reset threshold (VRST ) vs. temperature, “S” threshold option, VCC falling (STM6505) . . . 14
Figure 13.VBAT monitoring threshold (V BATTH) vs. temperature, falling (STM6505). . . . . . . . . . . . . . 14
Figure 14. AC testing input/output waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 15. TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm pitch package outline . . . . . . . . . . . . . . . . . . . . . 21
Figure 16. Landing pattern - TDFN – 8-lead 2 x 2 mm without thermal pad . . . . . . . . . . . . . . . . . . . . 22
Figure 17. Carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 18. Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 19. Tape trailer/leader. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 20. Pin 1 orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 21. Package marking, top view. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
STM6502, STM6503, STM6504, STM6505 Description
Doc ID 16101 Rev 6 5/29
1 Description
STM6502 has two combined Smart Reset inputs (SR0 and SR1) with delayed Smart Reset
setup time (tSRC ) programmed by an external capacitor on the SRC pin.
STM6503 is similar to STM6502, has two combined delayed Smart Reset inputs (SR0, SR1)
and three user-selectable delayed Smart Reset setup time (tSRC) options of 2 s, 6 s and 10
s through a three-state TSR input pin: when connected to ground, tSRC = 2 s; when left
open, tSRC = 6 s; when connected to VCC, tSRC = 10 s (all the times are minimum).
STM6504 has two independent Smart Reset inputs. SR0 provides the delayed Smart Reset
setup time (tSRC) function with three user-selectable tSRC options through a three-state TSR
input pin: when connected to ground, tSRC = 2 s; when left open, tSRC = 6 s; when
connected to VCC, tSRC = 10 s (all the times are minimum). SRE provides instant reset. SRE
is edge-triggered with a special debounce time (tDEBOUNCE = 240 ms min.) at the falling
edge after a valid reset period.
STM6505 has two combined delayed Smart Reset inputs (SR0, SR1) and provides an
adjustable reset delay setup time via an external capacitor connected to the SRC pin.
The RST output depends also on the VCC monitoring threshold. STM6505 also provides
independent low battery detect (BLD) output controlled by the secondary external input
voltage VBAT. VBAT is monitored for low voltage and provides an indication on the battery low
detect output pin (BLD). VBAT threshold is 1.25 V, fixed, and an external resistor divider is to
be used to set the actual battery voltage threshold. VBAT threshold hysteresis is 8 mV typ.
(16 mV max.). VBAT is voltage monitoring input only, the device is powered only from the
VCC pin; VCC must be ≥ 1.575 V for proper operation of the VBAT comparator.
1.1 Smart Reset devices
The Smart Reset device family STM65xx provides a useful feature that ensures inadvertent
short reset push-button closures do not cause system resets. This is done by implementing
extended Smart Reset input delay (tSRC ). Once the valid Smart Reset input levels and setup
delay are met, the device generates an output reset pulse with user-programmable timeout
period (tREC).
The Smart Reset inputs can be also connected to the applications interrupt to allow the
control of both the interrupt pin and the hard reset functions. If the push-buttons are closed
for a short time, the processor is only interrupted. If the system still does not respond
properly, holding the push-buttons for the extended setup time (tSRC ) causes hard reset of
the processor through the reset outputs. The Smart Reset feature helps significantly
increase system stability.
The STM65xx family of Smart Reset devices consists of low current microprocessor reset
circuits targeted at applications such as MP3 players, navigation, smartphones or mobile
phones; generally any application that requires delayed reset push-button(s) response for
improved system stability. The STM65xx devices feature single or dual Smart Reset inputs
(SR). The delayed Smart Reset setup time (tSRC ) options of 2 s, 6 s and 10 s (all min.) are
adjustable by an external capacitor on the SRC pin or selectable by three-state logic. The
delayed setup period ignores switch closures shorter than tSRC , thus preventing unwanted
resets.
Description STM6502, STM6503, STM6504, STM6505
6/29 Doc ID 16101 Rev 6
The STM65xx devices have active-low (optionally active-high) open-drain reset (RST)
output(s) with or without internal pull-up resistor or push-pull as output options, with factory-
programmed or capacitor-adjustable or push-buttons defined output reset pulse duration,
with or without power-on reset function.
Some devices also have an undervoltage monitoring feature: the reset output is also
asserted when the monitored supply voltage VCC drops below the specified threshold. The
reset output remains asserted for the reset timeout period (tREC) after the monitored supply
voltage goes above the specified threshold.
Figure 1. Logic diagrams
Figure 2. Pin connections
STM6502, STM6503, STM6504, STM6505 Description
Doc ID 16101 Rev 6 7/29
Table 2. Signal names
Description STM6502, STM6503, STM6504, STM6505
8/29 Doc ID 16101 Rev 6
Figure 3. Block diagram - STM6502, STM6503, STM6504 STM6504 only: SR0 and SRE are working independently. SRE is edge-triggered and has a special
debounce time (tDEBOUNCE = 240 ms min.) at the falling edge after a valid reset period.
Figure 4. Block diagram - STM6505
STM6502, STM6503, STM6504, STM6505 Description
Doc ID 16101 Rev 6 9/29
Figure 5. Single-button Smart Reset typical hookup
Figure 6. Dual-button Smart Reset typical hookup
Description STM6502, STM6503, STM6504, STM6505
10/29 Doc ID 16101 Rev 6
1.2 Pin descriptions
1.2.1 Power supply (VCC)
This pin is used to provide the power to the device and to monitor the power supply.
A 0.1 µF decoupling ceramic capacitor is recommended to be connected between the VCC
and VSS pins.
1.2.2 Ground (VSS)
This is the supply ground for the device.
1.2.3 Primary Smart Reset input (SR0)
The primary push-button Smart Reset input, active-low pin is connected to the first push-
button switch.
1.2.4 Secondary Smart Reset input (SR1)
The secondary push-button Smart Reset input, active-low pin is connected to the second
push-button switch. Keeping both Smart Reset inputs SR0 and SR1 active for longer than SRC activates the reset output pulse.
Figure 7. STM6502, STM6503 timing
Reset is asserted “low” right after the Smart Reset setup delay (tSRC) has been met and
returns to high after the tREC period.
STM6502, STM6503, STM6504, STM6505 Description
Doc ID 16101 Rev 6 11/29
1.2.5 Edge-triggered Smart Reset input (SRE pin) – STM6504 only
The SRE pin is active-high, immediate and independent reset input that includes an edge
trigger with debounce delay t DEBOUNCE on the falling edge.
Note: The triggering edge must be a high-to-low or low-to-high transition with a slew-rate faster
than 1 V/µs typ.
Figure 8. STM6504 timing
1.2.6 Adjustable delay of Smart Reset input (SRC pin) – STM6502 and
STM6505 only
This pin controls the setup time before the push-button action is validated by the reset
output. It is connected to an external capacitor (CSRC), which is tied to ground to provide the
desired value of the setup time (tSRC).
Calculated tSRC and CSRC examples are given in Table 3. Refer also to Table6.
Table 3. tSRC programmed by an ideal external capacitor – STM6502 and STM6505 At 25 °C. Example calculations based on an ideal capacitor. During application design and component
selection it should be considered that the current flowing into the external tSRC programming capacitor
(CSRC) is on the order of 100 nA, therefore a low-leakage capacitor (ceramic or film capacitor) should be
used and placed as close as possible to the SRC pin. Also an adequate low-leakage PCB environment
should be ensured to prevent tSRC accuracy from being affected. A recommended minimum value of CSRC
is 0.01 µF. In case of repeated activations of the tSRC timer, an interval of 10 ms min. is needed between the
activations to fully discharge CSRC, so that the next tSRC is as specified.
Description STM6502, STM6503, STM6504, STM6505
12/29 Doc ID 16101 Rev 6
1.2.7 Programmable Smart Reset input delay (TSR pin) – STM6503 and
STM6504 only
The TSR pin allows the user to program the setup time before the push-button action is
validated by the reset output. It is controlled by different voltage levels on the three-state
TSR input pin: when connected to ground, tSRC = 2 s; when left open, tSRC = 6 s; when
connected to VCC, tSRC = 10 s (all times are minimum). TSR is a DC-type input, intended to
be either permanently grounded, permanently connected to VCC or permanently left open.
If it is left open, for improved system glitch immunity it is strongly recommended to connect
a 0.1 µF decoupling ceramic capacitor between the TSR and VSS pins.
1.2.8 Reset output (RST)
RST is the active-low, open-drain reset output in the Smart Reset family.
1.2.9 Battery monitoring input (VBAT ) – STM6505 only
VBAT is an input for monitoring the battery voltage. VBAT threshold is 1.25 V, fixed, and an
external resistor divider is to be used to set the actual battery voltage threshold.
1.2.10 Battery low detect output (BLD) – STM6505 only
The battery low detect output is controlled by the VBAT voltage monitoring input and is
active-low, open-drain, with no pull-up.
Figure 9. STM6505 timing
STM6502, STM6503, STM6504, STM6505 Typical operating characteristics
Doc ID 16101 Rev 6 13/29 Typical operating characteristics
Figure 10. Supply current (ICC ) vs. temperature (STM6505)
Figure 11. Smart Reset delay (t ) vs. temperature, C = 0.62 µF (STM6505)
Typical operating characteristics STM6502, STM6503, STM6504, STM6505
14/29 Doc ID 16101 Rev 6
Figure 12. Reset threshold (VRST) vs. temperature, “S” threshold option, VCC falling (STM6505)
Figure 13.VBAT monitoring threshold (V BATTH) vs. temperature, falling (STM6505)
STM6502, STM6503, STM6504, STM6505 Maximum ratings
Doc ID 16101 Rev 6 15/29
3 Maximum ratings
Stressing the device above the rating listed in Table 4: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 4. Absolute maximum ratings Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds. For inputs or outputs with internal pull-up resistors and push-pull type outputs –0.3 to VCC +0.3 V only.
