STM6315RDW13F ,Open Drain Microprocessor ResetFeatures ■ Low supply current of 1.5µA (typ)■ ±1.8% reset threshold accuracy (25°C)■ Guaranteed RST ..
STM6315RGW13F ,Open Drain Microprocessor ResetAbsolute maximum ratings . 12Table 3. Operating and AC measurement conditions . . . . 13Ta ..
STM6315SDW13F ,Open Drain Microprocessor ResetLogic diagram . . . . 5Figure 2. SOT143-4 connections (top view) . . . . 5Figure 3.
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STM6315-STM6315LBW13F-STM6315RDW13F-STM6315RGW13F-STM6315SDW13F
Open Drain Microprocessor Reset
STM6315Open drain microprocessor reset
Features Low supply current of 1.5µA (typ) ±1.8% reset threshold accuracy (25°C) Guaranteed RST assertion down to
VCC = 1.0V Open drain RST output can exceed VCC Power supply transient immunity Operating temperature: –40 to +125°C Available in SOT143-4 package.
Contents STM6315
Contents Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.1 Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Manual reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Negative-going VCC transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4 Valid RST output down to VCC = 0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
STM6315 List of tables
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 3. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4. DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 5. SOT143-4 – 4-lead small outline transistor package mechanical data. . . . . . . . . . . . . . . . 17
Table 6. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 7. Marking description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 8. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
List of figures STM6315
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. SOT143-4 connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 5. Reset timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6. Manual reset timing diagram, switch bounce/debounce . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 7. Supply current vs. supply voltage, VRST = 2.63V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 8. Supply current vs. temperature (no load), VRST = 2.63V . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 9. RST output voltage vs. output current, VCC = 4.25V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 10. Normalized reset time-out period vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 11. Normalized reset threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 12. Max. transient duration not causing reset pulse vs. reset threshold Overdrive . . . . . . . . . 11
Figure 13. AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 14. SOT143-4 – 4-lead small outline transistor package outline . . . . . . . . . . . . . . . . . . . . . . . 17
STM6315 Summary description
1 Summary description
The STM6315 Microprocessor Reset Circuit is a low power supervisory device used to
monitor power supplies. It performs a single function: asserting a reset signal whenever the
VCC supply voltage drops below a preset value and keeping it asserted until VCC has risen
above the preset threshold for a minimum period of time (trec). It also provides a manual
reset input (MR). The open drain RST output can be pulled up to a voltage higher than VCC,
but less than 6V.
The STM6315 comes with standard factory-trimmed reset thresholds of 2.63V, 2.93V,
3.08V, 4.38V, and 4.63V. The STM6315 is available in the SOT143-4 package.
Figure 1. Logic diagram
Figure 2. SOT143-4 connections (top view)
Table 1. Signal names
Summary description STM6315
Figure 3. Block diagram
Figure 4. Hardware hookup Open drain RST output requires external pull-up resistor.
STM6315 Operation
2 Operation
2.1 Reset output
The STM6315 Microprocessor Reset Circuit has an active-low, open drain reset output. This
output structure will sink current when RST is asserted. Connect a pull-up resistor from RST
to any supply voltage up to 6V (see Figure 4 on page 6). Select a resistor value large
enough to register a logic low, and small enough to register a logic high while supplying all
input current and leakage paths connected to the reset output line. A 10k pull-up is sufficient
in most applications.
The STM6315 asserts a reset signal to the MCU whenever VCC goes below the reset
threshold (VRST), or when the manual reset input (MR) is taken low (see Figure 5 and
Figure 6 on page 8). RST is guaranteed valid down to VCC = 1.0V.
During power-up, (once VCC exceeds the reset threshold) an internal timer keeps RST low
for the reset time-out period, trec. After this interval, RST returns high.
If VCC drops below the reset threshold, RST goes low. Each time RST is asserted, it stays
low for at least the reset time-out period. Any time VCC goes below the reset threshold, the
internal timer clears. The reset timer starts when VCC returns above the reset threshold.
2.2 Manual reset input
A logic low on MR asserts RST. RST remains asserted while MR is low, and for trec after it
returns high. The MR input has an internal pull-up resistor 63kΩ (typ), allowing it to be left
open if not used.
This input can be driven with TTL/CMOS-logic levels or with open drain/collector outputs.
Connect a standard open push-button switch from MR to VSS to create a manual reset
function (see Figure 4 on page 6); external debounce circuitry is not required. If the device is
used in a noisy environment, connect a 0.1µF capacitor from MR to VSS to provide
additional noise immunity.
2.3 Negative-going VCC transients
The STM6315 is relatively immune to negative-going VCC transients (glitches). Figure 12 on
page 11 shows typical transient duration versus reset comparator overdrive (for which the
STM6315 will NOT generate a reset pulse). The graph was generated using a negative
pulse applied to VCC, starting at 0.5V above the actual reset threshold and ending below it
by the magnitude indicated (Reset Threshold Overdrive). The graph indicates the maximum
pulse width a negative VCC transient can have without causing a reset pulse. As the
magnitude of the transient increases (further below the threshold), the maximum allowable
pulse width decreases. Any combination of duration and overdrive which lies under the
curve will NOT generate a reset signal (see Figure 12). A 0.1µF bypass capacitor mounted
as close as possible to the VCC pin provides additional transient immunity.
Operation STM6315
2.4 Valid RST output down to VCC = 0V
When VCC falls below 1V, the RST output no longer sinks current, but becomes an open
circuit. In most systems this is not a problem, as most MCUs do not operate below 1V.
However, in applications where RST output must be valid down to 0V, a pull-down resistor
may be added to hold the RST output low. This resistor must be large enough to not load
the RST output, and still be small enough to pull the output to Ground. A 100KΩ resistor is
recommended.
Figure 5. Reset timing diagram
Figure 6. Manual reset timing diagram, switch bounce/debounce
STM6315 Typical operating characteristics Typical operating characteristics
Note: Typical values are at TA = 25°C.
Figure 7. Supply current vs. supply voltage, VRST = 2.63V
Figure 8. Supply current vs. temperature (no load), VRST = 2.63V
Typical operating characteristics STM6315
Figure 9. RST output voltage vs. output current, VCC = 4.25V
Figure 10. Normalized reset time-out period vs. temperature
STM6315 Typical operating characteristics
Figure 11. Normalized reset threshold vs. temperature
Figure 12. Max. transient duration not causing reset pulse vs. reset threshold Overdrive
Note: Reset occurs above the curve.
