STLVDS385BTR ,+3.3V PROGRAMMABLE LVDS TRANSMITTER 24-BIT FLAT PANEL DISPLAY (FPD) LINK-85MHZPIN CONFIGURATIONPIN DESCRIPTIONPlN N° SYMBOL NAME AND FUNCTION1, 9, 26 V PowerSupplypinsfor TTL In ..
STM1001LWX6F ,Reset CircuitFEATURES SUMMARY . . . . . 1Figure 1.
STM1001RWX6F ,Reset CircuitBlock DiagramVCCVCOMPARERSTtrec (1)RSTGeneratorAI09118Note: 1. Open DrainFigure 5. Hardware HookupV ..
STM1001RWX6F ,Reset CircuitBlock DiagramVCCVCOMPARERSTtrec (1)RSTGeneratorAI09118Note: 1. Open DrainFigure 5. Hardware HookupV ..
STM1001RWX6F ,Reset CircuitLogic DiagramTable 1. Signal NamesV GroundSSVCCActive-Low RESET Output (Open RSTDrain)VSupply Volta ..
STM1001SWX6F ,Reset CircuitBlock Diagram . . 3Figure 5. Hardware Hookup . . . . . . . 3OPERATION . . . . ..
SY10EL89ZC , COAXIAL CABLE DRIVER
SY10EL89ZC , COAXIAL CABLE DRIVER
SY10EL89ZC , COAXIAL CABLE DRIVER
SY10EL89ZI , COAXIAL CABLE DRIVER
SY10EL89ZI , COAXIAL CABLE DRIVER
SY10ELT20VZI , 5V/3.3V TTL-TO-DIFFERENTIAL PECL TRANSLATOR
STLVDS385B-STLVDS385BTR
+3.3V PROGRAMMABLE LVDS TRANSMITTER 24-BIT FLAT PANEL DISPLAY (FPD) LINK-85MHZ
1/14February 2004 20 TO85 MHz SHIFT CLOCK SUPPORT BEST–IN–CLASS SET& HOLD TIMES ON
TxINPUTs Tx POWER CONSUMPTION <130 mW (typ)
@85MHz GRAYSCALE Tx POWER-DOWN MODE <200µW (max) SUPPORTS VGA, SVGA, XGA aND SINGLE/
DUAL PIXEL SXGA. NARROW BUS REDUCES CABLE SIZE AND
COST UP TO 2.38 Gbps THROUGHPUT UP TO 297.5 Megabytes/sec BANDWIDTH 345 mV (typ) SWING LVDS DEVICES FOR
LOW EMI PLL REQUIRES NO EXTERNAL
COMPONENTS COMPATIBLE WITH TIA/EIA -644 LVDS
STANDARD
DESCRIPTIONThe STLVDS385 transmitter converts 28 bitsof
LVCMOS/LVTTL data into four LVDS (Low
Voltage Differential Signaling) data streams.A
phase-locked transmit clock is transmitted in
parallel with the data streams overa fifth LVDS
link. Every cycleof the transmit clock 28 bitsof
input data are sampled and transmitted. Ata
transmit clock frequencyof 85 MHz, 24 bitsof
RGB data and3 bitsof LCD timing and control
data (FPLINE, FPFRAME, DRDY) are transmitteda rateof 595 Mbps per LVDS data channel.
Usinga 85 MHz clock, the data throughputis
297.5 Mbytes/sec. The transmitter can be
programmed for Rising edge strobe or Falling
edge strobe througha dedicated pin.A Rising
edgeor Falling edge strobe transmitter will inter
operate witha Falling edge strobe Receiver
without any translation logic.
ORDERING CODES
STLVDS385+3.3V PROGRAMMABLE LVDS TRANSMITTER 24-BIT
FLAT PANEL DISPLAY (FPD) LINK-85MHZ
STLVDS3852/14
PIN CONFIGURATION
PIN DESCRIPTION
STLVDS3853/14
TABLE1 PROGRAMMABLE TRANSMITTER
ABSOLUTE MAXIMUM RATINGSAbsoluteMaximum Ratingsare those values beyond which damagetothe device may occur. Functional operation under theseconditionis
not implied.
RECOMMENDED OPERATING CONDITIONS
RECOMMENDED TRANSMITTER INPUT CHARACTERISTICS(VCC =3.3V,TJ= -10to 70°C unless
otherwise noted. Typical values are referredtoTA= 25°C)
ELECTRICAL CHARACTERISTICS
LVCMOS/LVTTL DC SPECIFICATIONS(VCC =3.3V,TJ= -10to 70°C unless otherwise noted. Typical
values are referredtoTA= 25°C)
STLVDS3854/14
LVDS DC SPECIFICATIONS(VCC =3.3V,TJ= -10to 70°C unless otherwise noted. Typical values are
referredto TA =25°C)
TRANSMITTER SUPPLY CURRENT (VCC =3.3V,TJ= -10to 70°C unless otherwise noted. Typical
values are referredtoTA= 25°C)
STLVDS3855/14
TRANSMITTER SWITCHING CHARACTERISTICS(VCC =3.3V,TJ= -10to 70°C unless otherwise
noted. Typical values are referredtoTA= 25°C)
Note1: Currentinto device pinsis definedas positive. Currentoutof device pinsis definedas negative. Voltagesare referencedto ground
unless otherwise specified (except VOD and ΔVOD).
Note2: VOS previously referredas VCM.
Note3: The Minimum and Maximum Limitsare basedon statistical analysisofthe device performance over process, voltage, and tempera-
ture range. This parameteris functionality tested onlyon Automatic Test Equipment (ATE).
Note4: The limitsare basedonbench characterization ofthedevice’sjitter response over thepower supply voltage range. Output clock jitter measured witha cycle-to-cycle jitterof±3ns appliedtothe input clock signal while data inputsare switching (See Figures15 and 16).A
jitter eventof 3ns, represents worse case jumpinthe clock edge from most graphics controller VGA chips currently available.
Note5: The worst case test pattern producesa maximum togglingof digital circuits, LVDSI/O and CMOS/TTLI/O.
Note 6:The16 grayscaletest pattern testsdevice powerconsumptionfor a“typical”LCD displaypattern.The testpatternapproximates signal
switching neededto produce groupsof16 vertical stripes acrossthe display.
Note7: Figures1,2 showa falling edge data strobe (TxCLK IN/RxCLK OUT).
Note8: Recommendedpinto signal mapping. Customer may chooseto define differently.
STLVDS3856/14
TIMING DIAGRAMS
Figure1: "Worst Case" Test Pattern (Note5)
STLVDS3857/14
Figure2: "16 Grayscale"TestPatter (Notes6,7,8)
