STLVDS32BDR ,HIGH SPEED DIFFERENTIAL LINE RECEIVERSelectrical characteristics of low voltage differentialand distance of data transfer is dependent up ..
STLVDS32BTR ,HIGH SPEED DIFFERENTIAL LINE RECEIVERSSTLVDS32/STLVDS3487STLVDS9637HIGH SPEEDDIFFERENTIAL LINE RECEIVERS■ MEETS OR EXCEEDS THEREQUIREMENT ..
STLVDS385B ,+3.3V PROGRAMMABLE LVDS TRANSMITTER 24-BIT FLAT PANEL DISPLAY (FPD) LINK-85MHZSTLVDS385+3.3V PROGRAMMABLE LVDS TRANSMITTER 24-BITFLAT PANEL DISPLAY (FPD) LINK-85MHZ
STLVDS32BD-STLVDS32BDR-STLVDS32BTR
HIGH SPEED DIFFERENTIAL LINE RECEIVERS
1/13December 2002 MEETS OR EXCEEDS THE
REQUIREMENTS OF ANSI TIA/EIA-644
STANDARD OPERATES WITHA SINGLE 3.3V SUPPLY DESIGNED FOR SIGNALING RATE UP TO
400Mbps DIFFERENTIAL INPUT THRESHOLDS
±100mV MAX TYPICAL PROPAGATION DELAY TIME OF
2.5ns POWER DISSIPATION 60mW TYPICAL PER
RECEIVER AT 200MHz LOW VOLATGE TTL (LVTTL) LOGIC
OUTPUT LEVELS PIN COMPATIBLE WITH THE AM26LS32,
SN65LVD32, MC3486 AND SN65LVD3486 OPEN CIRCUIT FAIL SAFE ESD PROTECTION:
7KV RECEIVER PINS
3KV ALL PINS VS GND
DESCRIPTIONThe STLVDS32, STLVDS3486 and STLVDS9637
are differential line receivers that implement the
electrical characteristicsof low voltage differential
signaling (LVDS). This signaling technique lower
the output voltage levels of 5V differential
standard levels (suchas TIA/EIA-422B)to reduce
the power, increase the switching speeds and
allows operations witha 3.3V supply rail. Anyof
the four differential receivers providesa valid
logical output state witha 3.3V supply rail. Anyof
the four differential receivers providesa valid
logical output state witha ±100mV differential
input voltage within the input common mode
voltage range. The input common mode voltage
allows 1Vof ground potential difference between
two LVDS nodes.
The intended applicationof these devices and
signalling techniqueis both point-to-point and
multidrop data transmission over controlled
impedance media approximately 100Ω.The
transmission media may be printed circuit board
traces, backplanesor cables. The ultimate rate
and distanceof data transferis dependent upon
the attenuation characteristicsof the media and
noise couplingto the enviroment.
The STLVDS32, STLVDS3486 and STLVDS9637
"B" version are characterized for operation from
-40°Cto 85°C.
ORDERING CODES
STLVDS32/STLVDS3487
STLVDS9637HIGH SPEED
DIFFERENTIAL LINE RECEIVERS
STLVDS32/STLVDS3486/STLVDS96372/13
PIN CONFIGURATION
STLVDS32 PIN DESCRIPTION STLVDS3486 PIN DESCRIPTION
STLVDS9637 PIN DESCRIPTION
STLVDS32/STLVDS3486/STLVDS96373/13
LOGIC DIAGRAM AND LOGIC SYMBOL FOR STLVDS32
LOGIC DIAGRAM AND LOGIC SYMBOL FOR STLVDS3486
LOGIC DIAGRAM AND LOGIC SYMBOL FOR STLVDS9637
STLVDS32/STLVDS3486/STLVDS96374/13
STLVDS3486 TRUTH TABLE
STLVDS9637 TRUTH TABLE
STLVDS32 TRUTH TABLEL=Low level, H=High Level, X=Don’t care,Z= High Impedance,
=Indeterminate
ABSOLUTE MAXIMUM RATINGSAbsoluteMaximum Ratingsare those values beyond which damagetothe device may occur. Functional operation under these conditionis
not implied.
Note1:All voltages except differentialI/Obus voltage,are with respecttothe network ground terminal.
RECOMMENDED OPERATING CONDITIONS
STLVDS32/STLVDS3486/STLVDS96375/13
ELECTRICAL CHARACTERISTICS (Over recommended operating conditions unless otherwise noted.
All typical values areatTA= 25°C, and VCC =3.3V)
STLVDS32/STLVDS3486/STLVDS96376/13
SWITCHING CHARACTERISTICS (Unless otherwise noted. Typical values are referredtoTA =25°C
andVCC =3.3V)
Note1: tsk(O)isthe skew betweenspecified outputsofa single device withall driving inputs connected togetherantthe outputs switchingin
the same direction while driving identical specifiad loads.
Note2: tsk(P)isthe magnitudeofthe time betweenthe hightolow andlowto high propagation delay timesatan outputs.
Note3: tsk(PP) isthemagnetudeofthedifferent inpropagationdelay times betweenany specifiedterminalsoftwodevices when bothdevices
operate withthe same supply voltage, same temperature and have identical packages andtest circuits.
STLVDS32/STLVDS3486/STLVDS96377/13
Figure1: Timing Test Circuit, Timing And Waveforms
NoteA:All input pulseare suppliedbya generator havingthe following characteristics:trortf ≤ 1ns, pulse repetition rate (PRR)= 50Mpps,
pulse width=10± 0.2ns.
NoteB:CL includes instrumentation and fixture capacitance within 6mmofthe D.U.T.
