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STLVD111BFR
PROGRAMMABLE LOW VOLTAGE 1:10 DIFFERENTIAL CLOCK DRIVER
1/12December 2002 100ps PART-TO PART SKEW 50ps BANK SKEW DIFFERENTIAL DESIGN MEETS LVDS SPEC. FOR DRIVER
OUTPUTS AND RECEIVER INPUTS REFERENCE VOLTAGE AVAILABLE
OUTPUT VBB LOW VOLTAGEVCC RANGEOF 2.375VTO
2.625V HIGH SIGNALLING RATE CAPABILITY
(EXCEEDS 622MHz) SUPPORT OPEN, SHORT AND
TERMINATED INPUT FAIL-SAFE (LOW
OUTPUT STATE) PROGRAMMABLE DRIVERS POWER OFF
CONTROL
DESCRIPTIONThe STLVD111isalow skew programmable1to differential LVDS driver, designedfor clock
distribution. The select signalis fannedoutto10
identical differential outputs.
The STLVD111is provided witha11bit shift
register witha serialin anda Control Register.
The purposeisto enableor poweroff each output
clock channel andto selectthe clock input. The
STLVD111is specifically designed, modelled and
produced withlow skewasthe key goal. Optimal
design and layout serveto minimize gateto gate
skew withina device. The net resultisa
dependable guaranteedlow skew device.
The STLVD111 canbe usedfor high performance
clock distributionin 2.5V systems with LVDS
levels. Designers can take advantageof the
device’s performanceto distribute low skew
clocks acrossthe backplaneorthe board.
ORDERING CODES
STLVD111PROGRAMMABLE LOW VOLTAGE
1:10 DIFFERENTIAL LVDS CLOCK DRIVER
STLVD111
PIN CONFIGURATION
PIN DESCRIPTION
STLVD1113/12
ABSOLUTE MAXIMUM RATINGSAbsoluteMaximum Ratingsare those values beyond which damagetothe devicemay occur. Functional operation under these conditionis
not implied.
THERMAL DATA
RECOMMENDED OPERATING CONDITIONS
DRIVER ELECTRICAL CHARACTERISTICS(TA=-40to85°C, VCC= 2.5V± 5%, unless otherwise
specified (Note1,2)
NOTE1:All currentsinto devicepinsare positive;all currentsoutof devicepinsare negative.All voltagesare referenced todevice ground
unless otherwise specified.
NOTE2:All typical valuesare givenforVCC =2.5VandTA= 25°C unless otherwise stated.
RECEIVER ELECTRICAL CHARACTERISTICS (TA =-40to85°C, VCC= 2.5V± 5%, unless otherwise
specified (Note1,2)
NOTE1:All currentsinto devicepinsare positive;all currentsoutof devicepinsare negative.All voltagesare referenced todevice ground
unless otherwise specified.
NOTE2:All typical valuesare givenforVCC =2.5VandTA= 25°C unless otherwise stated.
STLVD1114/12
DRIVER ELECTRICAL CHARACTERISTICS(TA=-40to85°C,VCC= 2.5V± 5%, unless otherwise
specified (Note1,2)
NOTE1:All currentsinto devicepinsare positive;all currentsoutof devicepinsare negative.All voltagesare referenced todevice ground
unless otherwise specified.
NOTE2:All typical valuesare givenforVCC =2.5VandTA= 25°C unless otherwise stated.
LVDS TIMING CHARACTERISTICS(TA=-40to85°C, VCC= 2.5V± 5%, unless otherwise specified
(Note4)
NOTE4: Generator waveformsforalltest conditions: f=1MHz,ZO=50Ω (unless otherwise specified).
CONTROL REGISTER TIMING CHARACTERISTICS(TA =-40to85°C,VCC= 2.5V± 5%, EN=H, unless
otherwise specified (Figure4)
STLVD1115/12
SPECIFICATIONOF CONTROL REGISTERThe STLVD111is provided witha11bit shift register witha SerialIn anda Control Register. The purposeto enableor powerof each output clock channel andto selectthe clock input. The STLVD111 provides
two working modality:
PROGRAMMED MODE (EN=1)
The shift register havea serial inputto loadthe working configuration. Oncethe configurationis loaded
with11 clock pulse, another clock pulse loadthe configurationintothe control register. The firstbitonthe
serial inputline enablesthe outputsQ9 and Q9,the secondbit enablesthe outputsQ8 andQ8 andsoon.
Thelastbitisthe clock selectionbit.To restartthe configurationofthe shift registera resetofthe state
machine mustbe done witha clock pulseonCK andtheENsetto Low. The control register shift register
canbe configuredon time after each reset.
STANDARD MODE (EN=0) Standard Modethe STLVD111 isn’t programmable,allthe clock outputsare enabled. The LVDS clock
inputis selected from Clock0or Clock1 withtheSIpinas showninthe Truth Table below.
TRUTH TABLEOF STATE MACHINE INPUTS
SERIAL INPUT SEQUENCE
TRUTH TABLEOF THE CONTROL REGISTER
TRUTH TABLE
STLVD1116/12
LOGIC DIAGRAM
