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STLC7550TQF7
LOW POWER LOW VOLTAGE ANALOG FRONT END
STLC7550
LOW POWER LOW VOLTAGE ANALOG FRONT END
November 1998 GENERAL PURPOSE SIGNAL PROCESSING
ANALOG FRONT END (AFE). TARGETED FOR V.34bis MODEM AND
56Kbps MODEM APPLICATIONS. 16-BIT OVERSAMPLING ΣΔ A/D AND D/A
CONVERTERS. 83dB SIGNAL TO NOISE RATIO FOR SAM-
PLING FREQUENCY UP TO 9.6kHz @ 3V. 87dB DYNAMIC RANGE @ 3V. FILTER BANDWIDTHS :
0.425 x THE SAMPLING FREQUENCY. ON-CHIP REFERENCE VOLTAGE. SINGLE POWER SUPPLY RANGE :
2.7 TO 5.5V. LOW POWER CONSUMPTION LESS THAN
30mW OPERATING POWER 3V. STAND-BY MODE POWER CONSUMPTION
LESS THAN 3μW at 3V. PROGRAMMING SAMPLING FREQUENCY. MAX. SAMPLING FREQUENCY : 45kHz. SYNCHRONOUS SERIAL INTERFACE FOR
PROCESSOR DATAS EXCHANGE. MASTER
OR SLAVE OPERATIONS. 0.50μm CMOS PROCESS. TQFP44 PACKAGE. STLC7546 MODE OF OPERATION COMPATIBLE
DESCRIPTION
The STLC7550 is a single chip Analog Front-end
(AFE) designed to implement modems up to
56Kbps.
It has been especially designed for host processing
application in which the modulation software .34bis, 56Kbps) is performed by the main applica-
tion processor : Pentium, Risc or DSP processors.
The main target of this device is stand alone appli-
ances as Hand Held PC (HPC), Personnal Digital
Assistants (PDA), Webphones, Network Comput-
ers, Set T op Boxes for Digital Television (Satellite
and Cable). o comply with such applications STLC7550 is
powered nominally at 3V only.
Maximum Power Dissipation 30mW is well suited
for Battery operations.
In case of battery low, STLC7550 will continue to
work even at a 2.7V level.
STLC7550 also provides clock generator for all
sampling frequencies requested for V .34bis and
56Kbps applications.
This new AFE can also be used for PC mother
boards or add-on cards or stand alone MODEMs.
It can be used in a master mode or slave mode.
The slave mode eases multi AFE architecture de-
sign in saving external logical glue.
1/17
PIN CONNECTIONS (TQFP44)
PIN CONNECTIONS (TQFP48)
STLC7550
2/17
PIN LIST
PIN DESCRIPTION
1 - POWER SUPPLY (5 pins)
1.1 - Analog VDD Supply (AVDD)
This pin is the positive analog power supply
voltage for the DAC and the ADC section.
It is not internally connected to digital VDD supply
(DVDD).
In any case the voltage on this pin must be higher
or equal to the voltage of the Digital power supply
(DVDD).
1.2 - Digital VDD Supply (DVDD)
This pin is the positive digital power supply for DAC
and ADC digital internal circuitry.
1.3 - Analog Ground (AGND1, AGND2)
These pins are the ground return of the analog DAC
(ADC) section.
1.4 - Digital Ground (DGND)
This pin is the ground for DAC and ADC internal
digital circuitry.
Notes :1. To obtain published performance, the analog VDD and Digital VDD should be decoupled with respect to Analog Ground and Digital
Ground, respectively. The decoupling is intended to isolate digital noise from the analog section ; decoupling capacitors should
be as close as possible to the respective analog and digital supply pins. All the ground pins must be tied together. In the following section, the ground and supply pins are referred to as GND and VDD,
respectively.
STLC7550
3/17
2 - HOST INTERFACE (10 pins)
2.1 - Data In (DIN)
In Data Mode, the data word is the input of the DAC
channel. In software, the data word is followed by
the control register word.
2.2 - Data Out (DOUT)
In Data Mode, the data word is the ADC conversion
result. In software, the data word is followed by the
register read.
2.3 - Frame Synchronization (FS)
In master mode, the frame synchronization signal
is used to indicate that the device is ready to send
and receive data. The data transfer begins on the
falling edge of the frame-sync signal. The frame-
sync is generated internally and goes low on the
rising edge of SCLK in master mode. In slave mode
the frame is generated externally.
2.4 - Serial Bit Clock (SCLK)
SCLK clocks the digital data into DIN and out of
DOUT during the frame synchronization interval.
The Serial bit clock is generated internally.
2.5 - Reset Function (RESET)
The reset function is to initialize the internal count-
ers and control register. A minimum low pulse of
100ns is required to reset the chip. This reset
function initiates the serial data communications.
The reset function will initialize all the registers to
their default value and will put the device in a
pre-programmed state. After a low-going pulse on
RESET, the device registers will be initialized to
provide an over-sampling ratio equal to 160, the
serial interface will be in data mode, the DAC
attenuation will be set to infinite, the ADC gain will
be set to 0dB, the Differential input mode on the
ADC converter will be selected, and the multiplexor
will be set on the main inputs IN+ and IN-. After a
reset condition, the first frame synchronization cor-
responds to the primary channel.
2.6 - Power Down (PWRDWN)
The Power-Down input powers down the entire
chip (< 50μW). When PWRDWN Pin is taken low,
the device powers down such that the existing
internally programmed state is maintained. When
PWRDWN is driven high, full operation resumes
after 1ms. If the PWRDWN input is not used, it
should be tied to VDD.
2.7 - Hardware Control (HC0, HC1)
These two pins are used for Hardware/Software
Control of the device. The data on HC0 and HC1
will be latched on to the device on the rising edge
of the Frame Synchronization Pulse. If these two
pins are low, Software Control Mode is selected.
When in Software Control Mode, the LSB of the
16-bit word will select the Data Mode (LSB = 0) or
the Control Mode (LSB = 1). Other combinations of
HC0/HC1 are for Hardware Control. These inputs
should be tied low if not used.
2.8 - Master/Slave Control (M/S)
When M/S is high, the device is in master mode
and Fs is generated internally. When M/S is low,
the device is in slave mode and Fs must be
generated externally.
2.9 - Master Clock Mode (MCM)
When MCM is high, XTALIN is provided externally
and must be equal to 36.864MHz. When MCM is low,
XTALIN is provided externally and must be equal to
oversampling frequency : Fs x Over (see Clock Block
Diagram and §4 Modes of Operation).
2.10 - Timeslot Control (TS)
When TS = 0 the data are assigned to the first
16 bits after falling edge of FS (7546 mode) other-
wise the data are bits 17 to 32.
The case M/S = 1 with TS = 1 is reserved for life-test
(transmit gain fixed to 0dB).
3 - CLOCK SIGNALS (2 pins)
Depending on MCM value, these pins have differ-
ent function.
3.1 - MCM = 1 (XTALIN, XTALOUT)
These pins must be tied to external crystal. For the
value of crystal see Functional Description Chapter
Part 3.
3.2 - MCM = 0 (MCLK, XTALOUT)
MCLK Pin must be connected to an external clock.
XTALOUT is not used.
PIN DESCRIPTION (continued)
STLC7550
4/17
4 - ANALOG INTERFACE (9 pins)
4.1 - DAC and ADC Positive Reference
Voltage Output (VREFP)
This pin provides the Positive Reference Voltage
used by the 16-bit converters. The reference volt-
age, VREF, is the voltage difference between the
VREFP and VREFN outputs, and its nominal value is
1.25V. VREFP should be externally decoupled with
respect to VCM.
4.2 - DAC and ADC Negative Reference
Voltage Output (VREFN)
This pin provides the Negative Reference Voltage
used by the 16-bit converters, and should be exter-
nally decoupled with respect to VCM.
4.3 - Common Mode Voltage Output (VCM)
This output pin is the common mode voltage
(AVDD - AGND)/2. This output must be decoupled
with respect to GND.
4.4 - Non-inverting Smoothing Filter Output(OUT+)
This pin is the non-inverting output of the fully
differential analog smoothing filter.
4.5 - Inverting Smoothing Filter Output (OUT-)
This pin is the inverting output of the fully differential
analog smoothing filter. Outputs OUT+ and OUT-
provide analog signals with maximum peak-to-
peak amplitude 2 x VREF, and must be followed by
an external two pole smoothing filter. The external
filter follows the internal single pole switch capaci-
tor filter. The cutoff frequency of the external filter
must be greater than two times the sampling fre-
quency (FS), so that the combined frequency re-
sponse of both the internal and external filters is flat
in the passband . The attenuator of the last output
stage can be programmed to 0dB, 6dB or infinite.
4.6 - Non-inverting Analog Input (IN+)
This pin is the differential non-inverting ADC input.
4.7 - Inverting Analog Input (IN-)
This pin is the differential inverting ADC input.
These analog inputs (IN+, IN-) are presented to the
Sigma-Delta modulator. The analog input peak-to-
peak differential signal range must be less than
2 x VREF, and must be preceded by an external
single pole anti-aliasing filter. The cut-off frequency
of the filter must be lower than one half the over-
sampling frequency. These filters should be set as
close as possible to the IN+ and IN- pins. The gain
of the first stage is programmable (see Table 3).
4.8 - Non-inverting Auxiliary Analog
Input (AUX IN+)
This pin is the differential non-inverting auxiliary ADC
input. The characteristics are same as the IN+ input.
4.9 - Inverting Auxiliary Analog Input (AUX IN-)
This pin is the differential inverting auxiliary ADC
input. The characteristics are same as the IN- input.
The input pair (IN+/IN- or AUX IN+/AUX IN-) are
software selectable.
PIN DESCRIPTION (continued)
BLOCK DIAGRAM (TQFP44)
STLC7550
5/17
FUNCTIONAL DESCRIPTION
1 - TRANSMIT D/A SECTION
The functions included in the Tx D/A section are
detailed hereafter. 16-bit 2’s complement data for-
mat is used in the DAC channel.
1.1 - Transmit Low Pass Filters
The transmit low pass filter is basically an interpo-
lating filter including a sinx/x correction. It is a
combination of Finite Impulse Response filter (FIR)
and an Infinite Impulse Response filter (IIR). The
digital signal from the serial interface gets interpo-
lated by 2, 3, 4, 5 or 6 x Sampling Frequency (FS)
through the IIR filter. The signal is further interpo-
lated by 32 x FS x n (with n equal to 2, 3, 4, 5, 6)
through the IIR and FIR filter. The low pass filter is
followed by the DAC. The DAC is oversampled at
64, 96, 128, 160, 192 x FS. The oversampling ratio
is user selectable.
1.2 - D/A Converter
The oversampled D/A converter includes a second
order digital noise shaper, a one bit D/A converter
and a single pole analog low-pass filter.
The attenuation of the last output stage can be
programmed to 0dB, +6dB or infinite. The cut-off
frequency of the single pole switch-capacitor low-
pass filter is :
fc−3dB = OCLK
2 ⋅ π ⋅ 10
with OCLK = Oversampling Clock frequency.
Continuous-time filtering of the analog differential
output is necessary using an off-chip amplifier and
a few external passive components.
At least 79dB signal to noise plus distortion ratio can
be obtained in the frequency band of 0.425 x 9.6kHz
(with an oversampling ratio equal to 160).
2 - RECEIVE A/D SECTION
The different functions included in the ADC channel
section are described below. 16-bit 2’s complement
data format is used in the ADC.
2.1 - A/D Converter
The oversampled A/D converter is based on a
second order sigma-delta modulator. To produce
excellent common-mode rejection of unwanted sig-
nals, the analog signal is processed differentially
until it is converted to digital data. Single-ended
mode can also be used. The ADC is oversampled
at 64, 96, 128, 160 or 192 x FS. The oversampling
ratio is user selectable. At least -85dB SNDR can
be expected in the 0.425 x 9.6kHz bandwidth with
a -6dBr differential input signal and an oversam-
pling ratio equal to 160.
2.2 - Receive Low Pass Filter
It is a decimation filter. The decimation is performed
by two decimation digital filters : one decimation
FIR filter and one decimation IIR filter.
The purpose of the FIR filter is to decimate 32 times
the digital signal coming from the ADC modulator.
The IIR is a cascade of 5 biquads. It provides the
low-pass filtering needed to remove the noise re-
maining above half the sampling frequency. The
output of the IIR will be processed by the DSP.
3 - CLOCK GENERATOR
The master clock, MCLK is provided by the user
thanks to a crystal or external clock generator (see
Figure 1).
The MCLK could be equal to 36.864MHz
(MCM = 1). In that case thanks to the divider M x Q,
the STLC7550 is able to generate all V.34bis and
56 Kbps sampling frequencies (see Table 1).
When MCM = 0, the MCLK must be equal to the
oversampling frequency : Fs x OVER (7546 mode).
The ADC and DAC are oversampled at the OCLK
frequency. OCLK is equal to the shift clock used in
the serial interface.
The MCLK frequency should be :
MCLK = K x Sampling frequency
Combination of M, Q and oversampling ratios al-
lows to generate several sampling frequencies.
Recommended values for classical modem appli-
cations are as follow :
Table 1 : Sampling Frequencies Generation
Note :1. Recommended value.
STLC7550
6/17
Figure 1 : Clock Block Diagram
FUNCTIONAL DESCRIPTION (continued)
4 - MODES OF OPERATION
Thanks to MCM and M/S programmation pins we
can get the following configuration.
Configuration 1 : MCM = 1, M/S = 1
The STLC7550 is in master mode and we have :
Fs = XTAL IN / (M x Q x OVER)
Fs and SCLK are output pins.
Figure 2 : Configuration 1
Figure 4 : Configuration 3 (7546 mode)
Figure 3 : Configuration 2
Configuration 2 : MCM = 1, M/S = 0
The STLC7550 is in slave mode. SCLK is provided
by the STLC7550, the processor generates the Fs
and controls the phase of the sampling frequency.
Fs must be the result of a division of a number of
cycles of SLCK (Fs = SCLK % OVER).
Configuration 3 : MCM = 0, M/S = 1
The STLC7550 is in master mode and the proces-
sor provides the XTAL IN = MCLK = OCLK.
The STLC7550 generates the Fs from OCLK. In
this mode the configuration 3 is equivalent to the
STLC7546 mode.
Configuration 4 : MCM = 0, M/S = 0
The STLC7550 is in slave mode.
The configuration 4 is equivalent to configuration 3
but the Fs is generated and phase controlled by the
processor.
Configuration 5 : MCM = 1, M/S = 1 (master codec)
MCM = 0, M/S = 0 (slave codec)
This is dual codec application.
The master codec has his data in timeslot 0 and
the slave codec has his data in timeslot 1 thanks to
the programmation of TS.
STLC7550
7/17
Figure 5 : Configuration 4
Figure 6 : Configuration 5
FUNCTIONAL DESCRIPTION (continued)
STLC7550
8/17
Figure 8 : Mixed Mode
5 - HOST INTERFACE
FUNCTIONAL DESCRIPTION (continued)
Figure 7 : Data Mode
The Host interface consist of the shift clock,
the frame synchronization signal, the ADC-
channel data output, and the DAC-channel
data input.
Two modes of serial transfer are available : First : Software mode for 15-bit transmit data
transfer and 16-bit receive data transfer Second : hardware mode for 16-bit data transfer.
Both modes are selected by the Hardware Control
pins (HC0, HC1).
The data to the device, input/output are MSB-first
in 2’s complement format (see Table 2).
When Control Mode is selected, the device will
internally generate an additional Frame Synchroni-
zation Pulse (Secondary Frame Synchronization
Pulse) at the midpoint of the original Frame Period.
If the device is in slave mode the additional frame
sync (secondary frame sync pulse) must be gener-
ated by the processor. The Original Frame Syn-
chronization Pulse will also be referred to as the
Primary Frame Synchronization Pulse.
Table 2 : Mode Selection
STLC7550
9/17

Partno	Mfg	Dc	Qty	Available	Descript
STLC7550TQF7	STM	N/a	60	avai	LOW POWER LOW VOLTAGE ANALOG FRONT END