STLC5048 ,FULLY PROGRAMMABLE FOUR CHANNEL CODEC AND FILTERSTLC5048FULLY PROGRAMMABLEFOUR CHANNEL CODEC AND FILTER■ FULLY PROGRAMMABLE MONOLITHIC 4 CHANNEL CO ..
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STLC5411P ,2B1Q U INTERFACE DEVICEGENERAL DESCRIPTIONline and the digital interface. That permits buildingSTLC5411 is a complete mono ..
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SY10EL01ZG , 4-INPUT OR/NOR
SY10EL01ZG , 4-INPUT OR/NOR
SY10EL01ZI , 4-INPUT OR/NOR
SY10EL01ZI , 4-INPUT OR/NOR
SY10EL04ZC , 2-INPUT AND/NAND
SY10EL04ZG , 2-INPUT AND/NAND
STLC5048
FULLY PROGRAMMABLE FOUR CHANNEL CODEC AND FILTER
1/45
STLC5048January 2003 FULLY PROGRAMMABLE MONOLITHIC 4
CHANNEL CODEC/FILTER SINGLE +3.3V SUPPLY A/m LAW PROGRAMMABLE LINEAR CODING (16 BITS) OPTION PCM HIGHWAY FORMAT AUTOMATICALLY
DETECTED:1.536 or 1.544 MHz2.048, 4.096,
8192 MHz TWO PCM PORTS AVAILABLE TX GAIN PROGRAMMING: 33dB RANGE;
<0.01dB STEP RX GAIN PROGRAMMING:42dB RANGE;
<0.01dB STEP PROGRAMMABLE SLIC INPUT IMPEDANCE PROGRAMMABLE TRANSHYBRID BALANCE
FILTER PROGRAMMABLE EQUALIZATION
(FREQUENCY RESPONSE) PROGRAMMABLE TIME SLOT ASSIGNMENT DIGITAL AND ANALOG LOOPBACKS SLIC CONTROL PORTSTATIC (16 I/Os)
DYNAMIC (12 I/Os + 4 CS) BUILT-IN TEST MODE WITH TONE
GENERATION, MCU ACCESS TO PCM DATA 64 TQFP (10X10mm) PACKAGE PROGRAMMABLE SLIC LINE CURRENT
LIMITATION PROGRAMMABLE SLIC OFF-HOOK
DETECTION THRESHOLD
DESCRIPTIONThe STLC5048 is a monolithic fully programmable 4
channel CODEC and filter. It operates with a single
+3.3V supply.
The analog interface is based on a receive output
buffer driving the SLIC RX input and on an amplifier
input stage normally driven by the SLIC TX output.
Due to the single supply voltage a midsupply refer-
ence level is generated internally by the device and
all analog signals are referred to this level (AGND).
The PCM interface uses one common 8KHz frame
sync. pulse for transmit and receive direction. The bit
clock is automatically detected between four stan-
dards: 1.563/1.544MHz, 2.048MHz, 4.096MHz,
8192MHz.
Two PCM port are provided: the channels can be
connected to port A or/and B.
Device programmability is achieved by means of
several registers and commands allowing to set the
different parameters like TX/RX gains, line imped-
ance, transhybrid balance, equalization (frequency
response), encoding law (A/μ), time slot assignment,
independent channels power up/down, loopbacks,
PCM bits offset.
The STLC5048 can be programmed via serial inter-
face running up to 8 MHz. One interrupt output pin is
also provided.
A GUI interface is also available to emulate and pro-
gram the coefficients for impedance synthesis, echo
cancelling and channel filtering.
FULLY PROGRAMMABLE
FOUR CHANNEL CODEC AND FILTER
STLC5048 2/45
BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGE
THERMAL DATA
3/45
STLC5048
PIN CONNECTION (Top view)
PIN DESCRIPTIONI/O DEFINITION
STLC5048 4/45
PIN DESCRIPTION (continued)ANALOG PIN DESCRIPTION
NOT CONNECTED
POWER SUPPLY PIN DESCRIPTION
5/45
STLC5048
PIN DESCRIPTION (continued)DIGITAL PIN DESCRIPTION
STLC5048 6/45
PIN DESCRIPTION (continued)DIGITAL PIN DESCRIPTION (continued
7/45
STLC5048
FUNCTIONAL DESCRIPTIONThe STLC5048 is a fully programmable device with embedded ROM and RAM. The ROM is used to contain the default
state coefficients for the programmable filters, while the RAM is used to load the desired coefficient values.
POWER ON INITIALIZATION
When power is first applied it is recommended to reset the device (M1=M0=0) in order to set all the internal reg-
isters to the reset value (see register description); this means also power down mode for all the four channels
and SW reset bit (RES) set in the CONF register.
When the RES bit is set, the only instructions allowed are the one that disable this bit and the REACOM instruc-
tion: all other instructions are ignored. It is not possible to disable the RES bit and write the other bits of the
CONF register with the same instruction.
Of course, RESET mode can be programmed also by writing the RES bit of the CONF register.
See appendix C for the power up sequence.
During RESET condition all the I/On and CSn pins are set as inputs, DX is in high impedance and all VFROn
are set to AGND. After the reset all registers are loaded with the reset value.
It means that the PCM interface and all the VFRO outputs are configured as described in the Power Down State,
while no transmit or receive time slot are set.
Then, filters and gain blocks are configured with the coefficient defined in the Default State.
POWER DOWN STATE
Each of the four channel may be put into power down mode by setting the appropriate bit in the CONF register.
In this mode the eventual programmed DX channel is set in high impedance while the VFRO outputs are forced
to AGND. When all the channels are set in Power Down mode the device enters the Power Down state: all the
blocks related to the data processing are turned off, while the RAM is On or Off according to the PDR bit value
in the COMEN register.
Figure 1. Block Diagram of a single channel.
STLC5048 8/45
FUNCTIONAL DESCRIPTION (continued)RINGING STATE
This state can be used during the ringing phase in order to transmit a low frequency ringing signal (25-50 Hz).
In order to obtain a 1 Vrms ringing signal at VFRO output a digital signal DR equal to -0.78dBm0 must be pro-
vided.
This state means B, Z, X, KD and KA blocks equal to open circuits and the R block configured in order to obtain
the maximum gain at the frequency of 25-50 Hz. During the ringing state if the TX time slot is enabled the idle
PCM code is forced to DX.
To switch to this state, a bit (FR0..3) in the COEFST register must be set for every channel.
The programmed values for the previous blocks become active only when the FR and FD bits are reset.
If both FR and FD bits of a channel are set, the selected coefficient will be those of the Ringing State.
IMPEDANCE SYNTHESYS
The impedance synthesis is performed by fully digital filters (Z and KD) and by an analog path (KA).
The Z, KD and KA filters report to the receive path the feedback signal coming from the transmit path. The co-
efficients of the Z, KD and KA filters are programmed via the ZFC, KD and AFE_CFF commands respectively.
ECHO CANCELING
The trans-hybrid balance is performed by the digital programmable filter B.
The B filter reports to the transmit path the signal coming from the receive path. The coefficient of the B filter
are programmed via the BFC command.
Figure 2. Transmit path.TRANSMIT PATH
The transmit section input consist of the input amplifier, the A/D converter, the equalization filter X, the gain
block GX, the encoder and the channel filters (LPX and HPX).
The input amplifier is provided of a programmable gain with a typical input impedance of 1MΩ. The amplifier
gain can be programmed with two different values (0dB, +3.52dB) by means of the TXG Register.
VFXI input must be AC coupled to the signal; the voltage swing allowed is 1.4Vpp when the preamplifier gain is
set to 0dB and 0.93Vpp when the gain is 3.52dB; higher levels must be reduced through proper dividers.
Following the input amplifier the signal is converted into digital domain and a X filter block is programmed to
equalise together with the HPX and LPX filters the frequency response. The coefficients of the X filter are pro-
grammed via the XFC command.
A gain block (GX) allows to set the transmit level in a 30dB range, with steps <0.01dB. This block can be pro-
grammed via the GTX command.
9/45
STLC5048
FUNCTIONAL DESCRIPTION (continued)The needed TX gain can be set by proper programming of the GX block in combination with the TX amplifier.
Setting GTX=00h, the transmitted signal is muted and an idle PCM signal is generated on DX.
Concerning the CODING function, A/m law can be selected writing the CONF register (bit 5 AMU). In addition,
via the CONF register (bit 6 LIN) the coding law can be set to linear mode (16 bits). In this case the signal sent
on the DX will take two adjacent PCM channels, proper care has to be taken in the time slot selection program-
ming (DXTS register).
The intrinsec non programmable gain GX0 set the TX path gain to 22.07dB. The absolute gain level (see elec-
trical characteristics) refers to this intrinsec gain.
RECEIVE PATH
The receive path of the STLC5048 consists of the decoder section, the gain block GR, the R filter, the channel
filters (LPR, HPR) the D/A converter and the output amplifier.
Concerning the DECODING function, A/m law can be selected writing the CONF register (bit 5 AMU). In addition
via the CONF register (bit 6 LIN) the coding law can be set to linear mode (16 bits).
In this case the signal received on the DR input will take two adjacent PCM channels, proper care has to be
taken in the time slot selection programming (DRTS register).
The gain block GR is controlled by the GRX command allowing 30dB gain range in 0.01dB steps.
The R filter together the channel filters (LPR and HPR) performs the line equalization. The coefficients of the R
filter are programmed via the RFC command.
The signal is converted in the analog domain and amplified by the RX amplifier that can be programmed with
four different values (mute, 0dB, -6dB and -12dB) by means of RXG register.
Figure 3. Receive path.VFRO output, referred to AGND must be AC coupled to the load, referred to VSS, to prevent a DC current flow.
In order to get the best noise performances it is recommended to keep GRX value as close as possible to the
maximum (FFh) setting properly the additional attenuation by means of RXG.
The intrinsec non programmable gain GR0 set the RX path gain to -3.15dB. The absolute gain level (see elec-
trical characteristics) refers to this intrinsec gain.
PCM INTERFACE
The STLC5048 dedicates eight pins to the interface with the PCM highways.
MCLK represents the bit clock and is also used by the device as a source for the clock of the internal PLL.
Five possible frequencies can be used: 1.536/1.544MHz (24 channels PCM frame); 2048MHz (32 channels
PCM frame); 4.096MHz (64 channels PCM frame); 8.192MHz (128 channels PCM frame). The operating fre-
STLC5048 10/45
quency is automatically detected by the device the first time both MCLK and FS are applied and becomes active
after the second FS period. MCLK synchronises both the transmit data (DXA/B) and the receive data (DRA/B).
The Frame Sync. signal FS is the common time base for all the four channels.
Transmit and Receive programmable Time-Slots are framed by an internal sync. signal that can be coincident
with FS or delayed of 1 or 7 MCLK cycles depending on the programming of PCMSH register.
Two PCM ports are available: every channel can be connected to a different PCM port by means of PCMCOM
register.
DXA/B represents the transmit PCM interface. It remains in high impedance state except during the assigned
time slots during which the PCM data byte is shifted out on the rising/falling edge of MCLK according to the TE
bit of PCMCOM register. The four channels can be shifted out in any possible timeslot as defined by the DXTS
registers. The assigned Time Slot (Transmit and Receive) takes place in the 8 MCLK cycles following the rising
edge of FS.
The data can be shifted out on port A and/or B according to PCMCOM register.
If one CODEC is set in Power Down by software programming the corresponding time slot is set in High Imped-
ance. When linear coding mode is selected by CONF register programming the output channel will need two
consecutive time slots (see register description).
DRA/B represents the receive PCM interface. It remains inactive except during the assigned time slots during
which the PCM data byte is shifted in on the falling edge of MCLK. The four channels are shifted in any possible
time slot as defined by the DRTS registers.
If one Codec is set in Power Down by software programming the corresponding time slot is not loaded and the
VFRO output is kept at steady AGND level.
INSTRUCTION BYTE STRUCTURER/W=0: Write Operation
R/W=1: Read Operation
I6..I0: Instruction Identifier: it can be a register address or a command identifier.
The number of data bytes depends on the instruction type. The first bit of a byte is the MSB, the first byte of an instruction is the LSByte.
When linear coding mode is selected by CONF register programming the input channel will need two consecu-
tive time slots (see register description).
The data can be shifted in from port A or B according to the PCMCOM register.
TSXA/B represents the Transmit Time Slot (open drain output, 3.2mA). Normally it is floating in high impedance
state except when a time slot is active on the DXA/B output. In this case TSXA/B output pulls low to enable the
backplane line driver. Should be strapped to VSS when not used.
Finally by means of the LOOPB register it is possible to implement a digital or analog loopback on any of the
selected channels.
MCU CONTROL INTERFACE
The MCU serial control interface consists of 4 pins.
CCLK: Control Clock
CI: Serial Data In
CO: Serial Data Out
CS: Chip Select Input
Control instructions require at least two bytes: however two single byte instructions are also provided.
11/45
STLC5048In the multiple byte instructions the first one specifies the command or the register address and the access type
(Read or Write).
The following bytes contain the data to be loaded into the internal RAM (on CI wire) or carry out the RAM content
(on CO wire) depending on the R/W bit of the first byte. CO wire is normally in High Impedance and goes to low
impedance only after the first byte in case of Read operation. This allows to use a common wire for both CI/CO.
CS, normally High, is set Low during the transmission/reception of a byte, lasting 8 CCLK pulses. Between two
consecutive access the CS must be set high.
The CCLK can be a continuos or a gated clock.
The result of any instruction (read/write operation), if negative, can generate an interrupt (maskable). The inter-
rupt register (INT) contains the cause information of the generated interrupt and it is cleared every time that it
is read.
Depending on the instruction specified in the first byte, the STLC5048 waits a defined number of data bytes. If
the STLC5048 doesn't receive the data byte within a predefined period specified by means of T_OUT command,
an internal time out rejects the instruction. The time-out time is verified between two consecutive MCU interface
access (between the falling edge of the CS and the following rising edge).
This feature is used to verify the synchronisation of the MCU interface: however it can be disabled if not desired
(see T_OUT reg description). To check this synchronisation is provided a specific register (SYNCK) that returns
always a predefined value: if the returned value is different the MCU interface is in out of sync state (the device
is waiting a data byte while the MCU is writing an address or vice versa). In this case, it is possible to realign it
by means of the execution of a specific single byte instruction (REACOM) from 1 to 53 times, depending on the
instructions.
Every time an illegal operation (access to not allowed address, time-out violation or clock pulse different than 8
inside a CS active) is performed the MCU interface is put on an error state: to resume it from this state a single
REACOM instruction can be used.
Anyway after a REACOM instruction a successful SYNC instruction guarantees the correct synchronisation.
One additional wire provided to the control interface is an open drain interrupt output (INT) that goes low when
a change of status is detected on the I/O pins or other interrupt source are active (see INT register). INT is au-
tomatically reset after reading of the register corresponding the cause that has generated the interrupt (see INT
register description).
A particular register (COMEN) allows to enable a command on different channel at the same time. Every time
a command operation is performed at least one channel must be enabled in this register.
This feature is useful when all channels must be configured in the same condition. When a command is used
to perform a read operation only one channel can be enabled at the same time.
To check the configuration of the device a checksum value is provided. This value is calculated on all coefficient
parameters entered (coefficients of KD, AFE_CFF, GRX, GTX, RFC, XFC, BFC, ZFC blocks; see CKSUM reg-
ister description). Two commands are required to get this value: the first one (CKSTART) starts the internal
checksum calculation, the second one (CKSUM) returns the calculated value. Between this two commands no
other operation are allowed. The checksum value is available within 400us the CKSTART command.
Coefficient checksum is defined by this algorithm:16 + X12 + X5 + 1
This algorithm guarantees a fault coverage of 1 - 2-16.
PROGRAMMING THE DEVICE
After the power up, the filters and gain blocks can be programmed also with all the channels set in Power Down.
In this case the PDR bit of the COMEN register must be set to 0.
With the proper setting of the COMEN register, the commands can be applied to more than one channel at the
same time.
To read the coefficient values loaded in the RAM, only one channel per time must be enabled in the COMEN
register.
STLC5048 12/45
SLIC CONTROL INTERFACE
The device provides 12 I/O pins plus 4 CS signals. The interface can work in dynamic or static mode: it can be
selected by means of STA bit of the CONF register. Dynamic Mode: the I/O pins are configured as input or output by means of DIR register. The CS signals
are used to select the different SLIC interface. In this case the I/O pin can be multiplexed. The data
loaded from SLIC #n via I/O pins configured as input can be read in the DATAn register. The data written
in a DATAn register will be loaded on the I/O pins configured as output when the Csn signal will be
active. Static Mode: The CS signal can be used as I/O pins. They can be configured as input or output I/O by
means of DATA1 register. The data corresponding to the CS signal can be read or written by means of
DATA2 register. All data related to the other I/O pins can be read or written by means of DATA0 register.
DC SLIC PROGRAMMABILITY
Three additional pins are used to select the On-Hook/Off-Hook detection threshold and the line card limitation
of the STLC3080 SLIC. This two values are programmed by ILIM and ITH registers. The programmation of
these two registers must be done before the filter coefficients download.
The VBG input pin must be connected to the IREF pin of the STLC3080.
When the L3235N is used in kit with STLC5048 the ILIM, ITH and VBG pin must be not connected.
BUILT IN TEST
By means of TONEG register it is possible to inject a tone of variable frequency (25Hz, 1 and 3KHz) and 0dBm0
amplitude into the receive path, replacing any signal coming from the PCM interface. This test can be performed
on every channel.
Setting the proper bit of the PCMCOM register is also possible to read/write the PCM data coming from the
transmit path via the MCU interface (PCMRD/PCMWD registers). This feature can be enabled only on one
channel per time.
These two features can be used to test the line interface operation.
REGISTER ADDRESSES
13/45
STLC5048
REGISTER ADDRESSES (continued)
STLC5048 14/45
REGISTER DESCRIPTION
I/O Direction Register (DIR)Addr=00h; Reset Value=00h
Addr=01h; Reset Value=X0h
IO11..0=0 I/O pin 11..0 is an input, data on the I/O input is written in DATAn register bit 11..0.
IO11..0=1 I/O pin 11..0 is an output, data contained in DATAn register bit 11..0 is transferred to the I/O output.
I/O Data Register channel #0 (DATA0) Addr=02h; Reset Value=00h
Addr=03h; Reset Value=X0h
If bit 4 of CONF register (STA)=0 Dynamic I/O mode:
When CS0 is active D011..0 are transferred to the corresponding I/O pins configured as outputs (see DIR reg-
ister). For the I/O pins configured as inputs the corresponding D011..0 will be written by the values applied to
those pins while CS0 is low.
If bit 4 of CONF register (STA)=1 Static I/O mode:
DS11..0 are transferred to the corresponding I/O pins configured as outputs (see DIR register). For the I/O pins
configured as inputs the corresponding DS11..0 will be written by the values applied to those pins.
15/45
STLC5048
I/O Data Register channel #1 (DATA1) Addr=04h; Reset Value=00h
Addr=05h; Reset Value=X0h
If bit 4 of CONF register (STA)=0 Dynamic I/O mode:
When CS1 is active D111..0 are transferred to the corresponding I/O pins configured as outputs (see DIR reg-
ister). For the I/O pins configured as inputs the corresponding D111..0 will be written by the values applied to
those pins while CS1 is low.
If bit 4 of CONF register (STA)=1 Static I/O mode:
In static mode CS pins are used as additional I/O pins. The CIO0..3 bits are used to define the direction of these pins.
CIO0..3=0 The CS0..3 is a static input, DATA is written in DATA2 register bits 0..3.
CIO0..3=1 The CS0..3 is a static output, DATA is taken from DATA2 register bits 0..3.
I/O Data Register channel #2 (DATA2) Addr=06h; Reset Value=00h
Addr=07h; Reset Value=X0h
If bit 4 of CONF register (STA)=0 Dynamic I/O mode:
When CS2 is active D211..0 are transferred to the corresponding I/O pins configured as outputs (see DIR reg-
ister). For the I/O pins configured as inputs the corresponding D211..0 will be written by the values applied to
those pins while CS2 is low.
STLC5048 16/45
If bit 4 of CONF register (STA)=1 Static I/O mode:
CD0..3 are transferred to the corresponding CS pin if configured as static output (see register DATA1). For the
CS pins configured as static inputs the corresponding CD0..3 will be written by the values applied to those pins.
I/O Data Register channel #3 (DATA3) Addr=08h; Reset Value=00h
Addr=09h; Reset Value=X0h
Used only if bit 4 of CONF register (STA)=0; Dynamic I/O mode:
When CS3 is active D311..0 are transferred to the corresponding I/O pins configured as outputs (see DIR reg-
ister). For the I/O pins configured as inputs the corresponding D311..0 will be written by the values applied to
those pins while CS3 is low.
If bit4 of CONF register (STA) = 1
Static I/O mode:
D33..0=1: The corresponding CSn cannot generate interrupt.
D33..0=0: The corresponding I/O (programmed as input) can generate interrupt if a change of status is detected.
Persistency Check Register (PCHK-A/B)Addr=0Ah; Reset Value=00h
Addr=0Bh; Reset Value=00h
Two input signal per channel, labelled A and B, are submitted to persistency check.
In dynamic mode (STA=0), A and B inputs of the four channels, are sampled on the multiplexed lines IO0 (pin
13) and IO1 (pin 14).
In static mode (STA=1) persistency check is performed on four pairs of lines, assigned to each channel accord-
ing to the table:
17/45
STLC5048TA7..0 and TB7..0, contents of PCHKA and PCHKB registers, define the minimum duration of input A and B to
generate interrupt; spurious transitions shorter than the programmed value are ignored.
The time width can be calculated according to the formula:
Time - Width A = (TA7..0)*64μs
Time - Width B = (TB7..0)*64μs
If PCHKA/B is programmed to 00h the persistency check is not performed and any detected transition will gen-
erate interrupt.
All the inputs, with or without persistency check, are sampled with a repetition rate of 32μs.
Interrupt Register (INT)Addr=10h; Reset Value=00h
Read Only
In dynamic I/O configuration the ID3..0 bits latch the interrupt request from the related channel (SLIC). Any sin-
gle bit IDn is cleared after reading related I/O register or by setting MCn bit High (i.e. when channel n is disabled
to generate interrupt).
In static I/O configuration ID0 and ID2 bits latch the interrupt request from I/O11..0 and CS3..0 respectively:
ID0: is set High when the interrupt is requested from any the I/O11..0 lines.
ID2: is set High when the interrupt is requested from any the CS3..0 (configured as I/O).
ID0 and ID2 are cleared after reading related I/O register.
ID1 and ID3 are don’t care.
ITV = 1: If the interrupt has been generated by time-out violation on the MCU serial interface.
IPCM = 1: When transmit PCM data reading/writing test is enabled an interrupt is generated every time valid
data are available (RRD bit set to 1) or must be written (WRD bit set to 1). The interrupt is cleared after reading/
writing the data in the PCMRD/PCMWD register via the MCU interface.
ICKF = 1: If the interrupt has been generated by a clock failure on PCM port (MCLK).
The INT register is cleared after reading operation only if signals (alarm cause) are inactive.
STLC5048 18/45
Interrupt Mask Register for I/O port (DMASK)Addr=11h; Reset Value=FFh
Addr=12h; Reset Value=XFh
MD11..0=1: The corresponding I/O doesn’t generate interrupt.
MD11..0=0: The corresponding I/O (programmed as input) generate interrupt if a change of status is detected.
Input lines with persistency check generate interrupt if the changed status remains stable longer than the time
programmed in the persistency check register PCHKA/B. Line without persistency check generate an immedi-
ate interrupt request.
Mask register has no effect on those pins configured as outputs, those pins will not generate interrupt.
Interrupt Mask Register for Interrupt (IMASK)Addr=13h; Reset Value=FFh
For dynamic I/O configuration, MCn bits are the disable/enable interrupt related to the channel n.
MC3..0=1: Any I/O line of the related channel #n is disabled to generate interrupt independently of DMASK setting.
MC3..0=0: Any I/O line of the related channel #n is enabled to generate interrupt depending on DMASK setting.
For static I/O configuration, MCn bits are the interrupt mask bits related to CSn that are configured as I/O lines.
MC0=1: The corresponding I/O cannot generate interrupt independently of DMASK setting.
MC0=0: The corresponding I/O can generate interrupt if a change of status is detected depending of DMASK setting.
MC2=1: The corresponding I/O cannot generate interrupt independently of DATA3_L setting (bit 3..0).
MC2=0: The corresponding I/O can generate interrupt if a change of status is detected depending of DATA3_L
setting (bit 3..0).
MC3 and MC1 bit are not used in static mode.
Input lines with persistency check generate interrupt if the changed status remains stable longer than the time
programmed in the persistency check register PCHKA/B. Line without persistency check generate an immedi-
ate interrupt request.
Mask register has no effect on those pins configured as outputs, those pins will not generate interrupt
MCF=1: The corresponding alarm bit (CKF) doesn’t generate interrupt.
MCF=0: The corresponding alarm bit (CKF) can generate interrupt.
MTV=1: The corresponding alarm bit (TV) doesn’t generate interrupt.
MTV=0: The corresponding alarm bit (TV) can generate interrupt.
MPCM =1 : The IPCM interrupt is masked (generation disabled).
MPCM =0 : The IPCM interrupt is enabled (generation enabled).
19/45
STLC5048
Alarm Register (ALARM)Addr=14h; Reset Value=01h
Read Only
POR=0: No Power On Reset is detected during operation.
POR=1: A Power On Reset is detected during operation.
The ALARM register is cleared after reading operation only if signals (alarm cause) are inactive.
Configuration Register (CONF)Addr=20h; Reset Value=BFh
RES=0 Normal Operation
RES=1 Device Reset: I/0n and Csn are all inputs, DX is H.I. (equivalent to Hw reset).
LIN=0 A or μ law PCM encoding
LIN=1 Linear encoding (16 bits), two’s complement.
AMU=0 μ law selection (all bits inverted)
AMU=1 A law selection (even bits inverted)
STA=0 CS0 to CS3 scan the four SLICs connected to the I/O control port, each CS has a 31.25μs repetition
time.
STA=1I/O are static, CS0 to CS3 are configured as generic static I/O
PD3..0=0 Codec 3..0 is active
PD3..0=1 Codec 3..0 is in Power Down. When one codec is in Power Down the corresponding VFRO output is
set to AGND and the corresponding transmit time slot on DX is set in H.I.
Command Enable register (COMEN)Addr=21h; Reset Value=80h
The En bits enable a command on one or more channels. All enabled channels will receive the entered data. At
least one channel must be enabled before every command.
E0..3=0: commands disabled on the corresponding channel 0..3
E0..3=1: commands enabled on the corresponding channel 0..3
PDR = 0: RAM is enabled also in Power Down.
PDR = 1: RAM is disabled in Power Down. In this way it’s possible to reduce the power consumption in Power
Down.
STLC5048 20/45
Synchronous Check register (SYNCK)Addr=23h; Reset Value=E4h
Read Only
This register contains a fixed code (E4h) that can be read to check the synchronisation of the MCU interface.
DSP Status Register (CTRLACK)Addr=25h; Reset Value=01h
Read Only
CKEND bit is 0 while the checksum calculation is performed: in the other time is always set to 1.
INIT bit becomes active (INIT = 1) after the DSP initialization. Normally it requires 70 us after the reset to be set to 1.
Checksum register (CKSUM)Addr=26h; Reset Value=00h
Addr=27h; Reset Value=00h
Read Only
The cheksum value is calculated every time the CKSTART instruction is performed and the result is available
after a proper delay (max 400 μs).
This register contains the cheksum value calculated on the contents of the following coefficient (each of 16 bits):
ZERO
KDF0_0 KDF0_1 KDF0_2 KDF1_0 KDF1_1 KDF1_2 KDF2_0 KDF2_1 KDF2_2 KDF3_0 KDF3_1 KDF3_2
AFE_CFF GRX0 GTX0 RFC0_0 ...... RFC0_16 XFC0_0 ...... XFC0_16 BFC0_0 ...... BFC0_25
ZFC0_0 ...... ZFC0_4 GRX1 GTX1 RFC1_0 ...... RFC1_16 XFC1_0 ...... XFC1_16 BFC1_0 ......BFC1_25
ZFC1_0 ...... ZFC1_4 GRX2 GTX2 RFC2_0 ......RFC2_16 XFC2_0 ...... XFC2_16 BFC2_0 ...... BFC2_25
ZFC2_0 ...... ZFC2_4 GRX3 GTX3 RFC3_0 ...... RFC3_16 XFC3_0 ...... XFC3_16 BFC3_0 ...... BFC3_25
ZFC3_0 ......ZFC3_4
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STLC5048
Loopback Register (LOOPB)Addr=2Ah; Reset Value=00h
DL3..0=0: Normal Operation
DL3..0=1: Codec #3..0 is set in Digital Loopback mode, this means that the receive PCM signal applied to the
programmed Receive Time Slot is transferred to the programmed Transmit Time Slot.
AL3..0=0: Normal Operation
AL3..0=1: Codec #3..0 is set in Analog Loopback mode, this means that the VFRO signal is transferred to the
VFXI input internally into the Codec.
When loopbacks are enabled the signal appears also at the corresponding VFRO output. It is possible to have
no signal on the VFRO output programming the GRX command to 00h in case of digital loopback.
Transmit Preamplifier Gain Register (TXG)Addr=2Bh; Reset Value=00h
TG3..0=0: Transmit preamplifier gain ch. 3..0 = 0dB
TG3..0=1: Transmit preamplifier gain ch. 3..0 = 3.52dB
Overall transmit gain depends on combination of TXG and GTXn registers.
Receive Amplifier Gain Register (RXG)Addr=2Ch; Reset Value=00h
Rn0=0,Rn1=0: Receive amp. gain ch #n = mute
Rn0=1,Rn1=0: Receive amp. gain ch #n = -12dB
Rn0=0,Rn1=1: Receive amp. gain ch #n = -6dB
Rn0=1,Rn1=1: Receive amp. gain ch #n = 0dB
Overall receive gain depends on the receive amplifier gain (R3..0) setting in RXG reg. and digital gain (GRXn
reg. setting).
STLC5048 22/45
SLIC Line Current Limit reg (ILIM)Addr=2Dh; Reset Value=00h
D4..0 = 0: Programmed value is 53
D4..0 = 1: Programmed value is 2
The step is 1.6 mA
This register allows to program a line current limitation from 2 to 53mA with a step equal to 1.6mA. These values
can be obtained using an external 15KOhm resistor in kit with STLC3080.
SLIC Off-Hook threshold register (ITH)Addr=2Eh; Reset Value=00h
D3..0 = 0: Programmed value is 16 mA
D3..0 = 1: Programmed value is 1 mA
The step is equal to 1 mA.
En = 1 The DC SLIC programmability block is enabled (ITH and ILIM)
En = 0 The DC SLIC programmability block is disabled (ITH and ILIM)
This register allows to program a threshold value from 1 to 16 mA with a step equal to 1mA. These values can
be obtained using an external 12.5KOhm resistor in kit with STLC3080.
PCM Shift Register (PCMSH)Addr=50h; Reset Value=00h
XS2..0:Effective start of the TX frame is the programmed values of clock pulses (0 to 7) after the FS rising edge.
RS2..0:Effective start of the RX frame is the programmed values of clock pulses (0 to 7) after the FS rising edge.
PCM Command register (PCMCOM)Addr=51h; Reset Value=00h
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STLC5048TPA/B = These two bits are used to enable the DX outputs of the port A or/and B. According to the combination
of these two bits the enabled port will be as follows:
RPAB = 0: Port A enabled (DRA input selected)
RPAB = 1: Port B enabled (DRB input selected)
TE = 0: Transmit PCM data change on rising edge of MCLK
TE = 1: Transmit PCM data change on falling edge of MCLK
PC1-PC0 = Selection of the channel for the PCM access data via MCU.
WR = 1: Setting this bit , receive PCM data writing via MCU (after A/μ decoding) is enabled on selected channel
and IPCM interrupt is generated every time FS signal becomes active, together to the set of the WRD bit in the
PCMCTRL register.
A data byte must be written every 125μs, if data is not replaced the old value is inserted again but the PMW bit
is set to 1 in the PCMCTRL register.
RR = 1: Setting this bit, transmit PCM data reading (after A/μ encoding) via MCU is enabled on selected channel
and IPCM interrupt is generated every time that data are available, together to the set of the RRD bit in the PC-
MCTRL register.
A data byte must be read every 125μS, if data is not read the new value is written in the PCM access register
but the POW bit is set to 1 in the PCMCTRL register.
Transmit Time Slot ch #0 (DXTS0)Addr=52h; Reset Value=00h
EN0=0:Selected transmit time slot on DX output is in H.I.
EN0=1:Selected transmit time slot on DX output is active carrying out the PCM encoded signal of VFXI0.
T06..0:Define time slot number (0 to 127) on which PCM encoded signal of VFXI0 is carried out.
If linear mode is selected (LIN=1 of CONF register) the 16 bits will be carried out as follows: the 8 most signifi-
cant bits in the programmed time slot, the 8 least significant bits in the following time slot.
Example: if T06..T00=00:
