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STLC5046
PROGRAMMABLE FOUR CHANNEL CODEC AND FILTER
PROGRAMMABLE MONOLITHIC 4 CHAN-
NEL CODEC/FILTER
SINGLE +3.3V SUPPLY
PIN STRAP / MCU CONTROL MODE
A/μ LAW PROGRAMMABLE
LINEAR CODING (16 BITS) OPTION
PCM HIGHWAY FORMAT AUTOMATICALLY
DETECTED: 1.536 or 1.544MHz; 2.048, 4.096,
8192 MHz
TX GAIN PROGRAMMING: 16dB RANGE;
<0.1dB STEP
RX GAIN PROGRAMMING: 26dB RANGE;
<0.1dB STEP
PROGRAMMABLE TIME SLOT ASSIGN-
MENT
DIGITAL AND ANALOG LOOPBACKS
SLIC CONTROL PORT
STATIC MODE (16 I/Os)
DYNAMIC MODE (12 I/Os + 4 CS)
64 TQFP PACKAGE
PCM IN HI-Z MODE
DESCRIPTIONThe STLC5046 is a monolithic programmable 4
channel codec and filter. It operates with a single
+3.3V supply. The analog interface is based on a
receive output buffer driving the SLIC RX input
and on an amplifier input stage. Due to the single
supply voltage a proper midsupply reference level
is generated internally by the device and all ana-
log signals are referred to this level (AGND). The
PCM interface uses one common 8KHz frame
sync. pulse for transmit and receive direction. The
bit clock can be selected between four standards:
1.536/1.544MHz, 2.048MHz, 4.096MHz,
8192MHz. Device programmability is achieved
by means of 41 registers allowing to set the dif-
ferent parameters like TX/RX gains, encoding law
(A/μ), time slot assignment, independent chan-
nels power up/down, loopbacks, PCM bits offset.
Thanks to pinstrap option, the most significant of
the above parameters can be set by hardware
connection of dedicated pins. This allow to use
this device also on line card without MCU on
board. When pin strap option is selected different
pins of the device will change their function (see
pin description).
In MCU control mode the STLC5046 can be pro-
grammed via serial interface running up to 4MHz.
One interrupt output pin is also provided.
STLC5046PROGRAMMABLE FOUR CHANNEL CODEC AND FILTER
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGE
THERMAL DATA
BLOCK DIAGRAM
STLC5046
ANALOG
PIN CONNECTION (Top view)
PIN DESCRIPTIONI/O DEFINITION
STLC5046
POWER SUPPLY
NOT CONNECTED
DIGITAL
PIN DESCRIPTION (continued)ANALOG
STLC5046
DIGITAL (DUAL MODE)
PIN DESCRIPTION (continued)DIGITAL
STLC5046
PIN DESCRIPTION (continued)
STLC5046
FUNCTIONAL DESCRIPTIONPOWER ON INITIALIZATION
When power is first applied it is recommended to
reset the device by forcing the condition
M1.0=00, in order to to clear all the internal regis-
ters.
In MCU mode M0 is set steadily Low and the de-
vice is reset by applying a negative pulse to M1
(its operative level in MCU mode is High); same
result can be obtained by writing an High level
into the control bit RES of the CONF register.
In Pin-strap mode M1 is set steadily Low and the
device is reset by applying a negative pulse to
M0 (its operative level in Pin-strap mode is High);
at the end of the Reset phase (M0=High) the de-
vice is programmed according to the logical con-
figuration of the control pins.
During the Reset condition all the I/On and CS_n
pins are set as inputs , DX is set in high imped-
ance and all VFROn outputs are forced to AGND.
POWER DOWN STATE
Each of the four channel may be put into power
down mode by setting the appropriate bit in the
CONF register or strapping to VDD the proper
pin. In this mode the eventual programmed DX
channel is set in high impedance while the VFRO
outputs are forced to AGND. In Pin strap mode
the value forced on the input pin is internally up-
dated every FS signal.
TRANSMIT PATH
The analog VFXI signal through an amplifier
stage is applied to a PCM converter and the cor-
responding digital signal is sent to DX output.
In MCU mode, the amplifier gain can be pro-
grammed with two different values by means of
TXG Reg. : 0dB or +3.52 dB.
A programmable gain block after the A/D conver-
sion allows to set transmit gain in 12dB range,
with steps <0.1dB by writing proper code into
GTXn register.
Setting GTXn=00h , the transmitted signal is
muted, i.e. an idle PCM signal is generated on
DX.
A/μ coding Law is selected by bit5 (AMU) of
CONF reg.
Setting LIN=1 (bit6 of CONF reg.) the Linear cod-
ing Law is selected (16bits); in this case the sig-
nal sent on DX will take two adjacent PCM time
slots.
In Pin-strap mode, the amplifier gain is set to
0dB; only two values of Transmit gain can be se-
lected according to the level of GXn control input
(in Pin-strap):
GXn=1 selects the gain corresponding to
GTXn=FFh (0dB)
GXn=0 selects the gain corresponding to
GTXn=8Fh ( -3.5dB)
Different gain value is obtained through proper
voltage divider.
A/μ coding Law is selected according to AMU pin
level:
AMU=0 μ-Law selected.
AMU=1 A-Law selected.
VFXI input must be AC coupled to the signal
source; the voltage swing allowed is 1.0Vpp
Figure 2. Receive path.
Figure 1. Transmit path.
STLC5046
when the preamplifier gain is set 0dB or 0.66Vpp
if the gain is set to 3.52dB (MCU mode only);
higher levels must be reduced through proper di-
viders.
Typical impedance of VFXI input is 1Mohm.
RECEIVE PATH
The received PCM signal DR through the de-
coder section, the gain select block and the D/A
converter is converted in an analog signal which
is transfered to VFRO output through an ampli-
fier stage.
In MCU mode a programmable gain block before
the A/D conversion allows to set receive gain in
12dB range, with steps <0.1dB by writing proper
code into GRXn register.
The amplifier gain can be programmed with five
different values by means of RXG Register:
0dB -1.94dB -4.44dB -7.96dB -13.98dB.
Setting GRXn=00h , the receive signal is muted
and VFRO output is set to AGND.
A/μ coding Law is selected by bit5 (AMU) of
CONF reg.
Setting LIN = 1 (bit6 of CONF reg.) the Linear
coding Law is selected (16bits); in this case the
signal received on DR will take two adjacent PCM
time slots.
in pin Strap mode only two values of Receive
Gain can be selected according to the level of
GRn control input (in Pin Strap)
GRn = 1 selects the gain corresponding to GRXn
= E2h, RXG = 0dB (-0.8dB)
GRn = 0 selects the gain corresponding to GRXn
= AFh, RXG = -1.94dB (-4.3dB)
Different gain value is obtained through proper
voltage divider.
A/μ coding Law is selected according to AMU pin
level:
AMU=0 μ-Law selected.
AMU=1 A-Law selected.
VFRO output, referred to AGND must be AC
coupled to the load, referred to VSS, to prevent a
DC current flow.
VFRO has a drive capability of 1.0mA (peak
value), with a max AC swing of 2Vpp.
In order to get the best noise performances it is
recommended to keep the GRX value as close as
possible to the maximum (FFh) setting properly
the additional attenuation by means of RXG.
PCM INTERFACE
The STLC5046 dedicate five pins (six in pin strap
mode) to the interface with the PCM highways.
MCLK represents the bit clock and is also used
by the device as a source for the clock of the in-
ternal Sigma Delta converter timings. Four possi-
ble frequencies can be used: 1.536/1.544MHz
(24 channels PCM frame); 2048MHz (32 chan-
nels PCM frame); 4.096MHz (64 channels PCM
frame); 8.192MHz (128 channels PCM frame).
The operating frequency is automatically de-
tected by the device when both MCLK and FS
are applied. MCLK is synchronizing both the
transmit data (DX) and the receive data (DR).
MCU mode: The Frame Sync. signal FS is the common time
base for all the four channels; Short (one MCLK
period) or Long (more than one MCLK period)
FS are allowed.
Transmit and Receive programmable Time-Slots
are framed to an internal sync. signal that can be
coincident with FS or delayed of 1 to 7 MCLK cy-
cles depending on the programming of PCMSH
Figure 3. MCU mode: Time - Slot Assignment
STLC5046
register.
DX represent the transmit PCM interface. It re-
mains in high impedance state except during the
assigned time slots during which the PCM data
byte is shifted out on the rising edge of MCLK.
The four channels can be shifted out in any pos-
sible timeslot as defined by the DXA0 to DXA3
registers. If one codec is set in Power Down by
software programming the corresponding timeslot
is set in High Impedance. When linear coding
mode is selected by CONF register programming
the output channel will need two consecutive
timeslots (see register description).
DR represent the receive PCM interface. It re-
mains inactive except during the assigned time
slots during wich the PCM data byte is shifted in
on the falling edge of MCLK. The four channels
are shifted in any possible timeslot as defined by
the DRA0 to DRA3 registers.
Pin Strap ModeWhen pinstrap mode is selected, dedicated
Frame Sync. FS3..0 are provided on dual func-
tion pins:
The PCMSH register cannot be accessed, there-
fore the beginning of the transmit and receive
frame is identified by the rising edge of the FSn
signal.
Each channel has its dedicated Frame Sync. sig-
nal FSn. Short or Long frame timing is automat-
ically selected; depending on the FS signal ap-
plied to FS0 input. The assigned Time Slot
(Transmit and Receive) takes place in the 8
MCLK cycles following the falling edge of FSn in
case of Short Frame or the rising edge in case of
Long Frame. If one codec is set in Power Down
by proper pin strap configuration the correspond-
ing timeslot is not loaded and the VFRO output is
kept at steady AGND level.
Finally by means of the LOOPB register is possi-
ble to implement a digital or analog loopback on
any of the selected channels.
TSX represent the Transmit Time Slot (open
drain output, 3.2mA). Normally it is floating in
high impedance state except when a time slot is
active on the DX output. In this case TSX output
pulls low to enable the backplane line driver.
Should be strapped to VSS when not used.
CONTROL INTERFACE
STLC5046 has two control modes, a microproc-
essor control mode and a pin strap control mode.
The two modes are selected by M0 and M1 pins.
When M0 = low, M1 = high (MCU control mode)
the MCU port is activated; and the 41 registers of
the device can be programmed. When M0 = high,
M1 = low (Pin-strap mode) the microprocessor
control port is disabled and some of the digital
pins change their function allowing to perform a
very basic programming of the device.
Figure 4. Pin Strap mode: Time Slot Assignment
Table 1. Control byte structure.R/W = 0: Write Register
R/W = 1: Read Register
D/S = 0: Single byte
D/S = 1: Two bytes
A5..A0: Register Address
STLC5046
In pin-strap mode the status of the control pins is
entered at power-on reset and refreshed at any
Frame Sync. cycle.
In MCU mode the control information is written to
or read from STLC5046 via the serial four wires
control bus :
CCLK : Control Clock
CS : Chip Select input
CI : Serial Data input
CO : Serial Data output
All control instructions require 2 bytes, with the ex-
ception of the single byte for command synchroni-
zation. The first byte specify the register address,
and the type of access (Read or Write).
The second byte contain the data to be loaded into
the register (on CI wire) or carried out the register
content (on CO wire) depending on the R/W bit of
the first byte. CO wire is normally in High Imped-
ance and goes to low impedance only during the
second byte in case of Read operation. This allows
to use a common wire for both CI/CO.
Serial data CI is shifted to the serial input register
on the rising edge of CCLK and CO is shifted out
CS, normally High, is set Low during the trans-
mission / reception of a byte, lasting 8CCLK
pulses .
Though, in general, two bytes of the same in-
struction take two CS separated cycles ,
STLC5046 can handle the data transfer in a sin-
gle 16 CCLK CS cycle, in both the directions.
One additional wire provided to the control inter-
face is an open drain interrupt output (INT) that
goes low when a change of status is detected on
the I/O pins.
SLIC CONTROL INTERFACE
The device provides 12 I/O pins plus 4 CS signals.
The interface can work in dynamic or static mode: it
can be selected by means of DIR register.
Dynamic Mode: the I/O pins are configured as
input or output by means of DIR register. The
CS signals are used to select the different SLIC
interface. In this case the I/O pin can be multi-
plexed. The data loaded from SLIC#n via I/O
pins configured as input can be read in the
DATAn register. The data written in a DATAn
register will be loaded on the I/O pins configured
as output when the Csn signal will be active.
Static Mode: The CS signal can be used as I/O
pins. They can be configured as input or out-
put I/O by means of DATA1 register. The data
corresponding to the CS signal can be read or
written by means of DATA2 register. All data
related to th other I/O pins can be read or writ-
ten by means of DATA0 register.
REGISTERS ADDRESSES (only MCU mode)
STLC5046
REGISTERS DESCRIPTION
Configuration Register (CONF)Addr=00h; Reset Value=3Fh
RES=0Normal Operation
RES=1 Device Reset: I/0n and CSn are all inputs,
DX is H.I. (equivalent to Hw. reset).
LIN=0 A or μ law PCM encoding
LIN=1 Linear encoding (16 bits), two’s comple-
ment.
AMU=0μ law selection
AMU=1 A law selection (even bits inverted)
STA=0 CS0 to CS3 scan the four SLICs con-
nected to the I/O control port, each CS has a
31.25μs repetition time.
STA=1; I/O are static, CS0 to CS3 are config-
ured as generic static I/O
PD3..0=0 Codec 3..0 is active
PD3..0=1 Codec 3..0 is in power Down. When
one codec is in Power Down the corresponding
VFRO output is forced to AGND. and the corre-
sponding transmit time slot on DX is set in H.I.
Pin strap value:
I/O Direction Register (DIR)Addr=01h; Reset Value=00h
Addr=02h; Reset Value=X0h
IO11..0 = 0; I/O pin 11..0 is an input, data on the
I/O input is written in DATAn register bit 11..0.
IO11..0 = 1; I/O pin 11..0 is an output, data con-
tained in DATAn register bit11..0 is transferred to
the I/O output.
Pin strap value:
I/O Data Register channel #0 (DATA0) Addr=03h; Reset Value=00h
Addr=04h; Reset Value=X0h
If bit 4 of CONF register (STA)=0
Dynamic I/O mode:
When CS0 is active D011..0 are transferred to the
corresponding I/O pins configured as outputs
(see DIR register). For the I/O pins configured as
inputs the corresponding D011..0 will be written by
the values applied to those pins while CS0 is low.
If bit 4 of CONF register (STA)=1
Static I/O mode:
D11..0 are transferred to the corresponding I/O
pins configured as outputs (see DIR register). For
the I/O pins configured as inputs the correspond-
ing D11..0 will be written by the values applied to
those pins.
Pin strap value:
I/O Data Register channel #1 (DATA1) Addr=05h; Reset Value=00h
Addr=06h; Reset Value=X0h
If bit 4 of CONF register (STA)=0
Dynamic I/O mode:
When CS1 is active D11..0 are transferred to the
corresponding I/O pins configured as outputs
(see DIR register). For the I/O pins configured as
inputs the corresponding D11..0 will be written by
the values applied to those pins while CS1 is low.
If bit 4 of CONF register (STA)=1
STLC5046
Static I/O mode:
CIO0..3=0 The CS0..3 is a static input, DATA is
written in DATA2 register bits 0..3.
CIO0..3=1 The CS0..3 is a static output, DATA is
taken from DATA2 register bits 0..3.
Pin strap value:
I/O Data Register channel #2 (DATA2) Addr=07h; Reset Value=00h
Addr=08h; Reset Value=X0h
If bit 4 of CONF register (STA)=0
Dynamic I/O mode:
When CS2 is active D211..0 are transferred to the
corresponding I/O pins configured as outputs
(see DIR register). For the I/O pins configured as
inputs the corresponding D11..0 will be written by
the values applied to those pins while CS2 is low.
If bit 4 of CONF register (STA)=1
Static I/O mode:
CD3..0 are transferred to the corresponding CS
pin if configured as static output (see register
DATA1). For the CS pins configured as static in-
puts the corresponding CD3..0 will be written by
the values applied to those pins.
Pin strap value:
I/O Data Register channel #3 (DATA3) Addr=09h; Reset Value=00h
Addr=0Ah; Reset Value=X0h
Used only if bit 4 of CONF register (STA)=0; Dy-
namic I/O mode:
When CS3 is active D11..0 are transferred to the
corresponding I/O pins configured as outputs
(see DIR register). For the I/O pins configured as
inputs the corresponding D11..0 will be written by
the values applied to those pins while CS3 is low.
If bit4 of CONF register (STA)=1
Static I/O mode:
can be used as general purpose R/W registers,
without any direct action on the control of the de-
vice.
Pin strap value:
Transmit Gain channel #0 (GTX0) Addr=0Bh; Reset Value=00h
00h:Stop any trasmit signal, null level is transmit-
ted in the corresponding timeslot on DX output.
>00h:Digital gain is inserted in the TX path equal
to:
20log[0.25+0.75*(progr. value/256)]
Pin strap values:
GX0=1: 0dB gain (value = FFh):
GX0=0: -3.5dB gain (value = 8Fh):
Transmit Gain channel #1 (GTX1) Addr=0Ch; Reset Value=00h
00h:Stop any trasmit signal, null level is transmit-
STLC5046
ted in the corresponding timeslot on DX output.
>00h:Digital gain is inserted in the TX path equal to:
20log[0.25+0.75*(progr. value/256)]
Pin strap values:
GX0=1: 0dB gain (value = FFh):
GX0=0: -3.5dB gain (value = 8Fh):
Transmit Gain channel #2 (GTX2) Addr=0Dh; Reset Value=00h
00h: Stop any trasmit signal, null level is transmit-
ted in the corresponding timeslot on DX output.
>00h:Digital gain is inserted in the TX path equal to:
20log[0.25+0.75*(progr. value/256)]
Pin strap values:
GX0=1: 0dB gain (value = FFh):
GX0=0: -3.5dB gain (value = 8Fh):
Transmit Gain channel #3 (GTX3) Addr=0Eh; Reset Value=00h
00h:Stop any trasmit signal, null level is transmit-
ted in the corresponding timeslot on DX output.
>00h:Digital gain is inserted in the TX path equal to:
20log[0.25+0.75*(progr. value/256)]
Pin strap values:
GX0=1: 0dB gan (value = FFh):
GX0=0: -3.5dB gain (value = 8Fh):
Receive Gain channel #0 (GRX0) Addr=0Fh; Reset Value=00h
00h:Stop any received signal, AGND level is
forced on the VFRO0 analog output.
>00h:Digital gain is inserted in the RX path equal to:
20log[0.25+0.75*(progr. value/256)]
Pin strap values:
GR0=1: -0.8dB gain (value = E2h):
GR0=0: -2.36dB gain (value = AFh):
Overall gain including also RXG:
GR0 = 1:-0.8dB; GR0 = 0: -4.3dB
Receive Gain channel #1 (GRX1)Addr=10h; Reset Value=00h
00h:Stop any received signal, AGND level is
forced on the VFRO1 analog output.
>00h:Digital gain is inserted in the RX path equal to:
20log[0.25+0.75*(progr. value/256)]
Pin strap values:
GR1=1: -0.8dB gain (value = E2h):
GR1=0: -2.36dB gain (value = AFh):
Overall gain including also RXG:
GR1= 1:-0.8dB; GR1 = 0: -4.3dB
Receive Gain channel #2 (GRX2) Addr=11h; Reset Value=00h
00h:Stop any received signal, AGND level is
forced on the VFRO2 analog output.
>00h:Digital gain is inserted in the RX path equal to:
STLC5046
20log[0.25+0.75*(progr. value/256)]
Pin strap values:
GR2=1: -0.8dB gain (value = E2h):
GR2=0: -2.36dB gain (value = AFh):
Overall gain including also RXG:
GR2 = 1:-0.8dB; GR2 = 0: -4.3dB
Receive Gain channel #3 (GRX3) Addr=12h; Reset Value=00h
00h:Stop any received signal, AGND level is
forced on the VFRO3 analog output.
>00h:Digital gain is inserted in the TX path equal to:
20log[0.25+0.75*(progr. value/256)]
Pin strap values:
GR3=1: -0.8dB gain (value = E2h):
GX3=0: -4.3dB gain (value = AFh):
Overall gain including also RXG:
GR3 = 1:-0.8dB; GR3 = 0: -4.3dB
Transmit Time Slot channel #0 (DXA0)Addr=13h; Reset Value=00h
EN0=0: Selected transmit time slot on DX output
is in H.I.
EN0=1: Selected transmit time slot on DX output
is active carrying out the PCM encoded
signal of VFXI0.
T06..0: Define time slot number (0 to 127) on
which PCM encoded signal of VFXI0 is
carried out.
If linear mode is selected (LIN=1 of CONF regis-
ter) the 16 bits will be carried out as follows: the 8
most significative bits in the programmed time
slot, the 8 least significative bits in the following
timeslot.
Example: if T06..T00=00:
Pin strap value (value 80h):
Referred to FS0.
Transmit Time Slot channel#1 (DXA1)Addr=14h; Reset Value=00h
EN1=0: Selected transmit time slot on DX output
is in H.I.
EN1=1: Selected transmit time slot on DX output
is active carrying out the PCM encoded
signal of VFXI1.
T16..0:Define time slot number (0 to 127) on
which PCM encoded signal of VFXI1 is carried
out.
If linear mode is selected (LIN=1 of CONF regis-
ter) the 16 bits will be carried out as follows: the 8
most significative bits in the programmed time
slot, the 8 least significative bits in the following
timeslot.
Example: if T16..T10=00:
Pin strap value (value=80h)
Referred to FS1.
Transmit Time Slot channel #2 (DXA2)Addr=15h; Reset Value=00h
EN2=0: Selected transmit time slot on DX output
is in H.I.
EN2=1: Selected transmit time slot on DX output
is active carrying out the PCM encoded
signal of VFXI2.
T26..0:Define time slot number (0 to 127) on
which PCM encoded signal of VFXI2 is carried
out.
If linear mode is selected (LIN=1 of CONF regis-
STLC5046
