STLC3055-STLC3055N Fast Delivery |IC PHOENIX CO.,LIMITED

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STLC3055-STLC3055N
WLL & ISDN-TA SUBSCRIBER LINE INTERFACE CIRCUIT
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STLC3055N
January 2005 FEATURES MONOCHIP SLIC OPTIMISED FOR WLL &
VoIP APPLICATIONS IMPLEMENT ALL KEY FEATURES OF THE
BORSHT FUNCTION SINGLE SUPPLY (5.5 TO 12V) BUILT IN DC/DC CONVERTER
CONTROLLER SOFT BATTERY REVERSAL WITH
PROGRAMMABLE TRANSITION TIME. ON-HOOK TRANSMISSION. PROGRAMMABLE OFF-HOOK DETECTOR
THRESHOLD METERING PULSE GENERATION AND
FILTER INTEGRATED RINGING INTEGRATED RING TRIP PARALLEL CONTROL INTERFACE (3.3V
LOGIC LEVEL) PROGRAMMABLE CONSTANT CURRENT
FEED SURFACE MOUNT PACKAGE INTEGRATED THERMAL PROTECTION DUAL GAIN VALUE OPTION BCD III S, 90V TECHNOLOGY -40 TO +85°C OPERATING RANGE DESCRIPTION
The STLC3055N is a SLIC device specifically de-
signed for WLL (Wireless Local Loop) and ISDN-
Terminal Adaptors and VoIP applications. One of
the distinctive characteristic of this device is the
ability to operate with a single supply voltage (from
+5.5V to +12V) and self generate the negative bat-
tery by means of an on chip DC/DC converter con-
troller that drives an external MOS switch.
WLL & ISDN-TA SUBSCRIBER LINE INTERFACE CIRCUIT
Figure 2. Block Diagram
Rev.8
STLC3055N
2 DESCRIPTION (continued)
The battery level is properly adjusted depending on the operating mode. A useful characteristic for these
applications is the integrated ringing generator.
The control interface is a parallel type with open drain output and 3.3V logic levels.
The metering pulses are generated on chip starting from two logic signals (0, 3.3V) one define the meter-
ing pulse frequency and the other the metering pulse duration. An on chip circuit then provides the proper
shaping and filtering. Metering pulse amplitude and shaping (rising and decay time) can be programmed
by external components. A dedicated cancellation circuit avoid possible CODEC input saturation due to
Metering pulse echo.
Constant current feed can be set from 20mA to 40mA. Off-hook detection threshold is programmable from
5mA to 9mA.
The device, developed in BCDIIIS technology (90V process), operates in the extended temperature range
and integrates a thermal protection that sets the device in power down when Tj exceeds 140°C.
Figure 3. Pin Connection
Table 2. Absolute Maximum Ratings
(1) Vbat is self generated by the on chip DC/DC converter and can be programmed via RF1 and RF2.
RF1 and RF2 shall be selected in order to fulfil the a.m limits (see External Components Table page 10)
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STLC3055N
Table 3. Operating Range
(1) Vbat is self generated by the on chip DC/DC converter and can be programmed via RF1 and RF2.
RF1 and RF2 shall be selected in order to fulfil the a.m limits (see External Components Table page 11)
Table 4. Thermal Data
Table 5. Pin Description
STLC3055N FUNCTIONAL DESCRIPTION
The STLC3055N is a device specifically developed for WLL VoIP and ISDN-TA applications.
It is based on a SLIC core, on purpose optimised for these applications, with the addition of a DC/DC con-
verter controller to fulfil the WLL and ISDN-TA design requirements.
The SLIC performs the standard feeding, signalling and transmission functions.
It can be set in four different operating modes via the D0, D1, D2 pins of the control logic interface (0 to
3.3V logic levels). The loop status is carried out on the DET pin (active low).
The DET pin is an open drain output to allow easy interfacing with both 3.3V and 5V logic levels.
The four possible SLIC’s operating modes are: Power Down High Impedance Feeding (HI-Z) Active Ringing
Table 6 shows how to set the different SLIC operating modes.
Table 5. (continued)
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STLC3055N
Table 6. SLIC Operating Modes.
3.1 DC/DC Converter
The DC/DC converter controller is driving an external power MOS transistor (P-Channel) in order to gen-
erate the negative battery voltage needed for device operation.
The DC/DC converter controller is synchronised with an external CLK (125KHz typ.)or with an internal
clock generated when the pin CLK is connected to CVCC. One sensing resistor in series to Vpos supply
allows to fix the maximum allowed input peak current. This feature is implemented in order to avoid over-
load on Vpos supply in case of line transient (ex. ring trip detection).
The typical value is obtained for a sensing resistor equal to 110mΩ that will guarantee an average current
consumption from Vpos < 700mA. When in on-hook the self generated battery voltage is set to a pre-
defined value.
This value can be adjusted via one external resistor (RF1) and it is typical -50V. When RING mode is se-
lected this value is increased to -70V typ.
Once the line goes in off-hook condition, the DC/DC converter automatically adjust the generated battery
voltage in order to feed the line with a fixed DC current (programmable via RLIM) optimising in this way
the power dissipation.
3.2 OPERATING MODES
3.2.1 Power Down
When this mode is selected the SLIC is switched off and the TIP and RING pins are in high impedance.
Also the line detectors are disabled therefore the off-hook condition cannot be detected.
This mode can be selected in emergency condition when it is necessary to cut any current delivered to the
line.
This mode is also forced by STLC3055N in case of thermal overload (Tj > 140°C).
In this case the device goes back to the previous status as soon as the junction temperature decrease
under the hysteresis threshold.
No AC transmission is possible in this mode.
3.2.2 High Impedance Feeding (HI-Z)
This operating mode is normally selected when the telephone is in on-hook in order to monitor the line
status keeping the power consumption at the minimum.
The output voltage in on-hook condition is equal to the self generated battery voltage (-50V typ).
When off-hook occurs the DET becomes active (low logic level).
The off-hook threshold in HI-Z mode is the same value as programmed in ACTIVE mode.
The DC characteristic in HI-Z mode is just equal to the self generated battery with 2x(1600Ω+Rp) in series
STLC3055N
(see fig. 4), where Rp is the external protection resistance.
No AC transmission is possible in this mode.
Figure 4. DC Characteristic in HI-Z Mode.
3.2.3 Active
3.2.3.1 DC Characteristics & Supervision
When this mode is selected the STLC3055N provides both DC feeding and AC transmission.
The STLC3055N feeds the line with a constant current fixed by RLIM (20mA to 40mA range). The on-hook
voltage is typically 40V allowing on-hook transmission; the self generated Vbat is -50V typ.
If the loop resistance is very high and the line current cannot reach the programmed constant current feed
value, the STLC3055N behaves like a 40V voltage source with a series impedance equal to the protection
resistors 2xRp (typ. 2x50Ω). Fig. 5 shows the typical DC characteristic in ACTIVE mode.
Figure 5. DC Characteristic in ACTIVE Mode
The line status (on/off hook) is monitored by the SLIC’S supervision circuit. The off-hook threshold can
be programmed via the external resistor RTH in the range from 5mA to 9mA.
Independently on the programmed constant current value, the TIP and RING buffers have a current
source capability limited to 80mA typ. Moreover the power available at Vbat is controlled by the DC/DC
converter that limits the peak current drawn from the Vpos supply. The maximum allowed current peak is
set by RSENSE resistor.
3.2.3.2 AC Characteristics
The SLIC provides the standard SLIC transmission functions:
Once in active mode the SLIC can operate with two different Tx, Rx Gain. Setting properly by the Gain set
control bit (see table 7).
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STLC3055N
Table 7. Gain Set in Active Mode Input impedance synthesis: can be real or complex and is set by a scaled (x50 or x25) external ZAC
impedance. Transmit and receive: The AC signal present on the 2W port (TIP/RING) is transferred to the TX output
with a -6dB or -12dB gain and from the RX input to the 2W port with a 0dB or +6dB gain. 2 to 4 wire conversion: The balance impedance can be real or complex, the proper cancellation is
obtained by means of two external impedance ZA and ZB
Once in Active mode (D1=1) the SLIC can operate in different states setting properly D0 and D2 control
bits (see also Table 8).
Table 8. SLIC states in ACTIVE mode
3.2.3.3 Polarity Reversal
The D2 bit controls the line polarity, the transition between the two polarities is performed in a "soft" way.
This means that the TIP and RING wire exchange their polarities following a ramp transition (see fig.6).
The transition time is controlled by an external capacitor CREV. This capacitor is also setting the shape
of the ringing trapezoidal waveform. When the control pins set battery reversal the line polarity is reversed
with a proper transition time set via an external capacitor (CREV).
Figure 6. TIP/RING Typical Transition from Direct to Reverse Polarity
3.2.3.4 Metering Pulse Injection (Ttx)
The metering pulses circuit consists of a burst shaping generator that gives a square wave shaped and a
low pass filter to reduce the harmonic distortion of the output signal.
The metering pulse is obtained starting from two logic signals: CKTTX: is a square wave at the TTX frequency (12 or 16KHz) and should be permanently applied to
the CKTTX pin or at least for all the duration of the TTX pulse (including rising and decay phases). D0: enable the TTX generation circuit and define the TTX pulse duration.
STLC3055N
These two signals are processed by a dedicated circuitry integrated on chip that generate the metering
pulse as an amplitude modulated shaped squarewave (SQTTX) (see fig.7).
Both the amplitude and the envelope of the squarewave (SQTTX) can be programmed by means of ex-
ternal components. In particular the amplitude is set by the two resistors RLV and the shaping by the ca-
pacitor CS.
Figure 7. Metering Pulse Generation Circuit.
The waveform so generated is then filtered and injected on the line.
The low pass filter can be obtained using the integrated buffer OP1 connected between pin FTTX (OP1
non inverting input) and RTTX (OP1 output) (see fig.7) and implementing a "Sallen and Key" configuration.
Depending on the external components count it is possible to build an optimised application depending
on the distortion level required. In particular harmonic distortion levels equal to 13%, 6% and 3% can be
obtained respectively with first, second and third order filters (see fig.7).
The circuit showed in the "Application diagram" is related to the simple first order filter.
Once the shaped and filtered signal is obtained at RTTX buffer output it is injected on the TIP/RING pins
with a +6dB gain or +12dB gain.
It should be noted that this is the nominal condition obtained in presence of ideal TTX echo cancellation
(obtained via proper setting of RTTX and CTTX).
In addition the effective level obtained on the line will depend on the line impedance and the protection re-
sistors value. In the typical application (TTX line impedance =200Ω, RP = 50Ω, and ideal TTX echo cancel-
lation) the metering pulse level on the line will be 1.33 or 2.66 times the level applied to the RTTX pin.
As already mentioned the metering pulse echo cancellation is obtained by means of two external compo-
nents (RTTX and CTTX) that should match the line impedance at the TTX frequency. This simple network
has a double effect: Synthesize a low output impedance at the TIP/RING pins at the TTX frequency. Cut the eventual TTX echo that will be transferred from the line to the TX output.
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STLC3055N
3.2.4 Ringing
When this mode is selected STLC3055N self generate an higher negative battery (-70V typ.) in order to
allow a balanced ringing signal of typically 65Vpeak.
In this condition both the DC and AC feedback are disabled and the SLIC line drivers operate as voltage
buffers. The ring waveform is obtained toggling the D2 control bit at the desired ring frequency. This bit in
fact controls the line polarity (0=direct; 1=reverse). As in the ACTIVE mode the line voltage transition is
performed with a ramp transition, obtaining in this way a trapezoidal balanced ring waveform (see fig.8).
The shaping is defined by the CREV external capacitor.
Selecting the proper capacitor value it is possible to get different crest factor values.
The following table shows the crest factor values obtained with a 20Hz and 25Hz ring frequency and with
1REN. These value are valid either with European or USA specification
Figure 8. TIP/RING Typical Ringing Waveform
Table 9. :
(*) Distorsion already less than 10%.
The ring trip detection is performed sensing the variation of the AC line impedance from on hook (relatively
high) to off-hook (low). This particular ring trip method allows to operate without DC offset superimposed
on the ring signal and therefore obtaining the maximum possible ring level on the load starting from a given
negative battery. It should be noted that such a method is optimised for operation on short loop applica-
tions and may not operate properly in presence of long loop applications (> 500Ω ). Once ring trip is de-
tected, the DET output is activated (logic level low), at this point the card controller or a simple logic circuit
should stop the D2 toggling in order to effectively disconnect the ring signal and then set the STLC3055N
in the proper operating mode (normally ACTIVE).
3.2.4.1 Ring Level in Presence of More Telephone in Parallel
As already mentioned above the maximum current that can be drawn from the Vpos supply is controlled
and limited via the external RSENSE. This will limit also the power available at the self generated negative
battery.
If for any reason the ringer load will be too low the self generated battery will drop in order to keep the
power consumption to the fixed limit and therefore also the ring voltage level will be reduced.
In the typical application with RSENSE = 110mΩ the peak current from Vpos is limited to about 900mA,
which correspond to an average current of 700mA max. In this condition the STLC3055N can drive up to
STLC3055N
3REN with a ring frequency fr=25Hz (1REN = 1800Ω + 1.0µF, European standard).
In order to drive up to 5REN (1REN= 6930Ω + 8µF, US standard) it is necessary to modify the external
components as follows:
CREV = 15nF
RD = 2.2KΩ
Rsense = 100mΩ
3.3 Layout Recommendation
A properly designed PCB layout is a basic issue to guarantee a correct behaviour and good noise perfor-
mances. Noise sources can be identified in not enough good grounds, not enough low impedance sup-
plies and parasitic coupling between PCB tracks and high impedance pins of the device.
Particular care must be taken on the ground connection and in this case the star configuration allows sure-
ly to avoid possible problems (see Application Diagram Figg. 9 and 10).
The ground of the power supply (VPOS) has to be connected to the center of the star, let’s call this point
Supply GND. This point should show a resistance as low as possible, that means it should be a ground
plane.
In particular to avoid noise problems the layout should prevent any coupling between the DC/DC convert-
er components that are referred to PGND (CVPOS, CD, L) and analog pins that are referred to AGND (ex:
RD, IREF, RTH, RLIM, VF). AGND and BGND must be shorter together. The GND connection of protec-
tion components have to be connected to the Supply GDND.
As a first reccomendation the components CV, L, D1, CVPOS, RSENSE should be kept as close as pos-
sible to each other and isolated from the other components.
Additional improvements can be obtained: decoupling the center of the star from the analog ground of STLC3055N using small chokes. adding a capacitor in the range of 100nF between VPOS and AGND in order to filter the switch
frequency on VPOS.
3.4 External Components List
In order to properly define the external components value the following system parameters have to be de-
fined: The AC input impedance shown by the SLIC at the line terminals "Zs" to which the return loss
measurement is referred. It can be real (typ. 600Ω) or complex. The AC balance impedance, it is the equivalent impedance of the line "Zl" used for evaluation of the
trans-hybrid loss performances (2/4 wire conversion). It is usually a complex impedance. The value of the two protection resistors Rp in series with the line termination. The line impedance at
the TTX frequency "Zlttx". The metering pulse level amplitude measured at line termination "VLOTTX". In case of low order
filtering, VLOTTX represents the amplitude (Vrms) of the fundamental frequency component. (typ 12 or
16KHz). Pulse metering envelope rise and decay time constant "τ". The slope of the ringing waveform "∆VTR/∆T ". The value of the constant current limit current "Ilim". The value of the off-hook current threshold "ITH". The value of the ring trip rectified average threshold current "IRTH". The value of the required self generated negative battery "VBATR" in ring mode (max value is 70V).
This value can be obtained from the desired ring peak level + 5V. The value of the maximum current peak sunk from Vpos "IPK".
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STLC3055N
Table 10. External Components
Table 11. External Components @Gain Set = 0
STLC3055N
Table 12. External Components @Gain Set = 1
(1) In case Zs=Zl, ZA and ZB can be replaced by two resistors of same value: RA=RB=|Zs|.
(2) In this case CTTX is just operating as a DC decoupling capacitor (fp=100Hz).
(3) Defining ZTTX as the impedance of RTTX in series with CTTX, RTTX and CTTX can also be calculated from the following formula:
ZTTX=50*(Zlttx+2Rp).
(4) CVpos should be defined depending on the power supply current capability and maximum allowable ripple.
(5) For low ripple application use 2x47µ F in parallel.
(6) Can be saved if proper PCB layout avoid noise coupling on RD pin (high impedance input).
(7) RF1 sets the self generated battery voltage in RING and ACTIVE(Il=0) mode as follows:
VBATR should be defined considering the ring peak level required (Vringpeak=VBATR-6V typ.).
The above relation is valid provided that the Vpos power supply current capability and the RSENSE programming allow to source all the
current requested by the particular ringer load configuration.
(8) For high efficiency in HI-Z mode coil resistance @125kHz must be < 3Ω
Table 11. External Components @Gain Set = 0 (continued)

Partno	Mfg	Dc	Qty	Available	Descript
STLC3055	ST	N/a	242	avai	WLL & ISDN-TA SUBSCRIBER LINE INTERFACE CIRCUIT
STLC3055	ST Pb-free	N/a	21	avai	WLL & ISDN-TA SUBSCRIBER LINE INTERFACE CIRCUIT
STLC3055N	STM	N/a	39	avai	WLL & ISDN-TA SUBSCRIBER LINE INTERFACE CIRCUIT
STLC3055N	ST	N/a	36983	avai	WLL & ISDN-TA SUBSCRIBER LINE INTERFACE CIRCUIT