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STHVDAC-303C6
High voltage BST capacitance controller
November 2012 Doc ID 18317 Rev 3 1/24
STHVDAC-303High voltage BST capacitance controller
Datasheet production data
Features Dedicated ASIC to control BST tunable
capacitances Operation compliant with cellular systems
requirements Integrated boost converter with 3
programmable outputs (from 0 to 30 V) Low power consumption 3-wire serial interface (30 or 32 bit SPI) Available in WLCSP for stand-alone or SiP
module integration RF tunable passive implementation in mobile
phones to optimize the radiated performances
Application Cellular antenna tunable matching network in
multi-band GSM/WCDMA mobile phone Compatible with open loop antenna tuner
applications
Figure 1. Pin configuration (bump view)
DescriptionThe ST BST capacitance controller
STHVDAC-303 is a high voltage digital to analog
converter (DAC), specifically designed to control
and meet the wide tuning bias voltage
requirement of the BST tunable capacitances.
It provides 3 independent high voltage outputs,
thus having the capability to control 3 different
capacitances in parallel. It is fully controlled
through a 3-wire serial interface.
BST capacitances are tunable capacitances
intended for use in mobile phone application, and
dedicated to RF tunable applications. These
tunable capacitances are controlled through a
bias voltage ranging from 0 to 30 V. The
implementation of BST tunable capacitance in
mobile phones enables significant improvement in
terms of radiated performance, making the
performance almost insensitive to the external
environment.
Contents STHVDAC-3032/24 Doc ID 18317 Rev 3
Contents Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83.1 HVDAC output voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4 3-wire serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.5 Power-up / down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.6 Settling time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.7 Power supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.8 Timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Register table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Serial interface specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Serial interface frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Ordering information schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
STHVDAC-303 Electrical characteristics
Doc ID 18317 Rev 3 3/24
1 Electrical characteristics
Table 1. Absolute maximum ratings (limiting value)
Table 2. Recommended operating conditions
Electrical characteristics STHVDAC-303
4/24 Doc ID 18317 Rev 3
Table 3. DC characteristics Typical value with typical application condition, VHV = 20 V, AVDD = 3.3 V, 25 °C, Iload = 3*1µA
Table 4. Boost converter characteristics
STHVDAC-303 Electrical characteristics
Doc ID 18317 Rev 3 5/24
Table 5. High voltage DAC output characteristics
Electrical characteristics STHVDAC-303
6/24 Doc ID 18317 Rev 3
Table 6. Recommended settings for DAC outputs and DAC_boost
STHVDAC-303 Functional block diagram
Doc ID 18317 Rev 3 7/24 Functional block diagram
Figure 2. HVDAC functional block diagram
Table 7. Signal descriptions
Theory of operation STHVDAC-303
8/24 Doc ID 18317 Rev 3 Theory of operation
3.1 HVDAC output voltages
The HVDAC outputs are directly controlled by programming the 8-bit DAC (DAC A, DAC B
and DAC C) through the 3-wire serial interface.
The DAC stages are driven from a reference voltage, generating an analog output voltage
driving a high voltage amplifier supplied from the boost converter (see HVDAC block
diagram - Figure2).
The HVDAC output voltages are scaled from 0 to 30 V , with 255 steps of 117 mV (30/255 =
0.11764 V). The nominal HVDAC output can be approximated to 117 mV x (DAC value).
For performance optimization, it is also possible to control the boost output voltage (VHV)
from 15 V to 30 V, by programming the DAC_boost value (4 bits / 1 V step).
For proper operation, ST recommends the operation of the HVDAC outputs 2 V below the
actual boost output voltage (VHV), to avoid clamping the HVDAC outputs to the boost output
voltage.
Recommended settings for DAC A, DAC B and DAC C according to DAC_boost settings are
described in Table 6., considering the overall HVDAC accuracy. These recommended
settings are further described on Figure5
Minimum HVDAC output voltage is also limited to 2 V, meaning minimum DAC command is
equal to 19 (or 13h), independent of the DAC_boost setting.
DAC settings can be programmed outside this recommended operating range, but in this
case the HVDAC performance (accuracy and noise) be outside the specified range.
If DAC value is set to 00 h, then the corresponding output is directly connected to GND
through a pull-down resistor (500 ).
Figure 3. Recommended DAC commands versus DAC_boost setting
STHVDAC-303 Theory of operation
Doc ID 18317 Rev 3 9/24
3.2 Operating modes
The following operating modes are accessible through the serial interface: Shutdown mode: The HVDAC is switched off, and all the blocks in the control ASIC
are switched off. Power consumption is almost zero in this mode, the DAC outputs are
in high Z state. The shutdown mode is set by sending a dedicated command through
the serial interface. Active mode: The HVDAC is switched on and the DAC outputs are fully controlled
through the serial interface. The DAC settings can be dynamically modified and the HV
outputs will be adjusted according to the specified timing diagrams. Each DAC can be
individually controlled and/or switched off according to application requirements. This
mode is set and controlled through serial interface commands.
3.3 Power-on reset
Power-on reset is implemented on the Vdig supply input, ensuring the HVDAC will be reset
to default mode once Vdig supply line rises above a given threshold (typically 1 V). This
trigger will force all registers to their default value.
3.4 3-wire serial interface
The HVDAC is fully controlled through a 3-wire serial interface (DAT A, CS, CLOCK).This
interface is further described in the next sections of this document.
3.5 Power-up / down sequence
Table 8 and Figure 5 describe the HVDAC settling time requirements and recommended
timing diagrams.
Switching from shutdown to active mode is triggered by sending a dedicated serial interface
command.
Switching from active to shutdown mode will occur after sending the related command
through the 3-wire serial interface.
Active mode can be directly activated from shutdown. In any case the HVDAC will be
operational only after Tactive (max 300 µs). A settling time (Tset) is required following each
DAC command in active mode. During this settling time the HVDAC output voltages will vary
from the initial to the updated DAC command.
3.6 Settling time
The ST HVDAC will set the bias voltage of the tuner within 35 µs after the chip select is
released. The setting time is defined as the time it takes for the output to reach 95% of its
final value. A positive setting time (Tset +) is defined when the output voltage rises and a
negative setting time (Tset -) when it decreases to its final value. See Figure 4 for details.
Theory of operation STHVDAC-303
10/24 Doc ID 18317 Rev 3
Figure 4. Bias voltage of the tuner
3.7 Power supply sequencing
The ST HVDAC does not require any specific power supply sequencing. It is assumed that
the AVDD input will be directly supplied from the battery and will then be the first on.
If Vdig supply is pulsed, 5 µs are required (max) to settle internal voltages before sending the
first command through the 3-wire serial interface.
STHVDAC-303 Theory of operation
Doc ID 18317 Rev 3 11/24
3.8 Timing parameters
Figure 5. Timing diagram example
Table 8. Timing parameters
Register table STHVDAC-303
12/24 Doc ID 18317 Rev 3
4 Register table
The HVDAC embeds 5 x 16-bit registers. Registers content is described in Table 9.
Registers 1 to 3 are used to control the mode of operations and the HVDAC settings.
HVDAC control and settings are thus fully ensured by programming these three registers.
Registers 4 and 5 are reserved for test purpose, and should not be addressed.
Table 9. Register table
