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STG4159BJR
Low Voltage 0.3 Ohm Max Single SPDT Switch with Break-Before-Make Feature and 10kV Contact ESD Protection
August 2012 Doc ID 12493 Rev 6 1/18
STG4159Low-voltage 0.3 Ω max. single SPDT switch with break-before-make
feature and 10 kV contact ESD protection
Datasheet − production data
Features Wide operating voltage range:
VCC (opr.) = 1.65 to 4.8 V Low power dissipation:
ICC = 0.2 µA (max.) at TA = 85 °C Low on-resistance VIN = 0 V:
–RON = 0.40 Ω (max. TA = 25 °C) at
VCC = 2.25 V
–RON = 0.35 Ω (max. TA = 25 °C) at
VCC = 3.0 V
–RON = 0.30 Ω (max. TA = 25 °C) at
VCC = 4.3 V Separate supply voltage for switch and control
pin Latch-up performance exceeds 100 mA per
JESD 78, class II ESD performance tested on common channel
(D pin) 10 kV IEC-61000-4-2 ESD, contact
discharge 15 kV IEC-61000-4-2 ESD, air discharge ESD performance test on all other pins 10 kV IEC-61000-4-2 ESD, contact
discharge 500 V machine model (JESD22 A115-A) 1500 V charged-device model
(JESD22 C101)
DescriptionThe STG4159 device is a high-speed CMOS low-
voltage single-analog SPDT (single-pole dual-
throw) switch or 2:1 multiplexer/demultiplexer
switch fabricated in silicon gate C2 MOS
technology. It is designed to operate from 1.65 to
4.8 V, making this device ideal for portable
applications. It offers low on-resistance (0.30 Ω) at
VCC = 4.3 V. The SEL inputs are provided to
control the switches.
The switch S1 is ON (connected to common port
D) when the SEL input is held high and OFF (high
impedance state exists between the two ports)
when SEL is held low; the switch S2 is ON (it is
connected to common port D) when the SEL input
is held low and OFF (high impedance state exists
between the two ports) when SEL is held high.
Additional key features are fast switching speed,
break-before-make delay time and ultra low-power
consumption. All inputs and outputs are equipped
with protection circuits against static discharge,
giving them ESD immunity and transient excess
voltage.
Table 1. Device summary
Contents STG41592/18 Doc ID 12493 Rev 6
Contents Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
STG4159 Logic diagramDoc ID 12493 Rev 6 3/18
1 Logic diagram Figure 1. Functional diagram
Figure 2. Input equivalent circuit
Table 2. Truth table High impedance.
Logic diagram STG41594/18 Doc ID 12493 Rev 6
Figure 3. Pin connections
Table 3. Pin assignment
STG4159 Maximum ratingDoc ID 12493 Rev 6 5/18
2 Maximum ratingStressing the device above the rating listed in T able 4: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in Table 5: Recommended
operating conditions of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Table 4. Absolute maximum ratings Derate above 70 °C by 18.5 mW/C.
Table 5. Recommended operating conditions VL pin should not be left floating.
