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STF19NM65N
N-channel 650 V, 0.25 Ohm, 15.5 A, MDmesh(TM) 2 Power MOSFET in a TO-220FP package
February 2008 Rev 1 1/19
STF19NM65N-STI19NM65N-STW19NM65N
STB19NM65N - STP19NM65NN-channel 650 V - 0.25 Ω - 15.5 A - TO-220/FP-D2/I2 PAK-TO-247
second generation MDmesh™ Power MOSFET
Features 100% avalanche tested Low input capacitance and gate charge Low gate input resistance
Application Switching applications
DescriptionThis series of devices implements the second
generation of MDmesh™ T echnology. This
revolutionary Power MOSFET associates a new
vertical structure to the Company’s strip layout to
yield one of the world’s lowest on-resistance and
gate charge. It is therefore suitable for the most
demanding high efficiency converters
Figure 1. Internal schematic diagram Limited only by maximum temperature allowed
Table 1. Device summary
Contents STB19NM65N-STI19NM65N-STF19NM65N-STP/W19NM65N2/19
Contents Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
STB19NM65N-STI19NM65N-STF19NM65N-STP/W19NM65N Electrical ratings
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1 Electrical ratings
Table 2. Absolute maximum ratings Limited only by maximum temperature allowed Pulse width limited by safe operating area ISD ≤ 15.5 A, di/dt ≤ 400 A/µs, VDD = 80% V(BR)DSS
Table 3. Thermal data
Electrical ratings STB19NM65N-STI19NM65N-STF19NM65N-STP/W19NM65N
4/19
Table 4. Avalanche characteristics
STB19NM65N-STI19NM65N-STF19NM65N-STP/W19NM65N Electrical characteristics
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2 Electrical characteristics
(TCASE=25°C unless otherwise specified)
Table 5. On/off states Characteristics value at turn off on inductive load
Table 6. Dynamic Pulsed: pulse duration = 300µs, duty cycle 1.5% Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS
increases from 0 to 80% VDSS
Electrical characteristics STB19NM65N-STI19NM65N-STF19NM65N-STP/W19NM65N
6/19
Table 7. Switching times
Table 8. Source drain diode Pulse width limited by safe operating area Pulsed: pulse duration = 300µs, duty cycle 1.5%
STB19NM65N-STI19NM65N-STF19NM65N-STP/W19NM65N Electrical characteristics
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2.1 Electrical characteristics (curves)
Figure 2. Safe operating area for TO-220 - 2 PAK - I2 PAK
Figure 3. Thermal impedance for TO-220 - 2 PAK - I2 PAK
Figure 4. Safe operating area for TO-220FP Figure 5. Thermal impedance for TO-220FP
Figure 6. Safe operating area for TO-247 Figure 7. Thermal impedance for TO-247
Electrical characteristics STB19NM65N-STI19NM65N-STF19NM65N-STP/W19NM65N
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Figure 8. Output characteristics Figure 9. Transfer characteristics
Figure 10. Transconductance Figure 11. Static drain-source on resistance
Figure 12. Gate charge vs gate-source voltage Figure 13. Capacitance variations
STB19NM65N-STI19NM65N-STF19NM65N-STP/W19NM65N Electrical characteristics
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Figure 14. Normalized gate threshold voltage
vs temperature
Figure 15. Normalized on resistance vs
temperature
Figure 16. Source-drain diode forward
characteristics
Figure 17. Normalized B VDSS vs temperature
Test circuit STB19NM65N-STI19NM65N-STF19NM65N-STP/W19NM65N
10/19 Test circuit
Figure 18. Switching times test circuit for
resistive load
Figure 19. Gate charge test circuit
Figure 20. Test circuit for inductive load
switching and diode recovery times
Figure 21. Unclamped Inductive load test
circuit
Figure 22. Unclamped inductive waveform Figure 23. Switching time waveform
