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STE53NA50STMN/a2avaiN-CHANNEL ENHANCEMENT MODE FAST POWER MOS TRANSISTOR


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STE53NA50
N-CHANNEL ENHANCEMENT MODE FAST POWER MOS TRANSISTOR
STE53NA50
N - CHANNEL ENHANCEMENT MODE
FAST POWER MOS TRANSISTOR TYPICAL RDS(on) = 0.075 Ω HIGH CURRENT POWER MODULE AVALANCHE RUGGED TECHNOLOGY VERY LARGE SOA - LARGE PEAK POWER
CAPABILITY EASY TO MOUNT SAME CURRENT CAPABILITY FOR THE
TWO SOURCE TERMINALS EXTREMELY LOW Rth (Junction to case) VERY LOW INTERNAL PARASITIC
INDUCTANCE ISOLATED PACKAGE UL RECOGNIZED
APPLICATIONS
SMPS & UPS MOTOR CONTROL WELDING EQUIPMENT OUTPUT STAGE FOR PWM, ULTRASONIC
CIRCUITS
February 1998
ABSOLUTE MAXIMUM RATINGS

(•) Pulse width limited by safe operating area
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THERMAL DATA
AVALANCHE CHARACTERISTICS
ELECTRICAL CHARACTERISTICS (Tcase = 25
o C unless otherwise specified)
OFF
ON (∗)
DYNAMIC
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ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
SWITCHING OFF
SOURCE DRAIN DIODE
(∗) Pulsed: Pulse duration = 300 μs, duty cycle 1.5 %
(•) Pulse width limited by safe operating area
Safe Operating Area for Thermal Impedance
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Output Characteristics
Transconductance
Gate Charge vs Gate-source Voltage
Transfer Characteristics
Static Drain-source On Resistance
Capacitance Variations
STE53NA50

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Normalized Gate Threshold Voltage vs
Temperature
Source-drain Diode Forward Characteristics
Fig. 2: Gate Charge test Circuit

Normalized On Resistance vs Temperature
Fig. 1: Switching Times Test Circuits For

Resistive Load
Fig. 3: Test Circuit For Inductive Load Switching

And Diode Recovery Times
STE53NA50

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STE53NA50
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