STQ1NK60ZR-AP ,N-CHANNEL 600VFEATURES OF GATE-TO-SOURCE ZENER DIODESThe built-in back-to-back Zener diodes have specifically bee ..
STQ1NK60ZR-AP ,N-CHANNEL 600VAPPLICATIONS
STD1LNK60Z-1-STN1NK60Z-STQ1NK60ZR-STQ1NK60ZR-AP
N-CHANNEL 600V
1/13February 2005
STD1LNK60Z-1
STQ1NK60ZR - STN1NK60ZN-CHANNEL 600V 13Ω 0.8A TO-92/IPAK/SOT-223
Zener-Protected SuperMESH™MOSFET
Rev. 5
STD1LNK60Z-1 - STQ1NK60ZR - STN1NK60Z2/13
Table 3: Absolute Maximum ratings ) Pulse width limited by safe operating area
(1) ISD ≤0.3A, di/dt ≤200A/µs, V DD ≤ V(BR)DSS, Tj ≤ TJMAX.
Table 4: Thermal Data (#) When mounted on 1 inch² Fr-4 board, 2 Oz Cu
Table 5: Avalanche Characteristics
Table 6: Gate-Source Zener Diode
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODESThe built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the
usage of external components.
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STD1LNK60Z-1 - STQ1NK60ZR - STN1NK60Z
ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED)
Table 7: On /Off
Table 8: Dynamic
Table 9: Source Drain Diode Note:1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. Pulse width limited by safe operating area. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80%
VDSS.
STD1LNK60Z-1 - STQ1NK60ZR - STN1NK60Z4/13
Figure 3: Safe Operating Area for IPAK
Figure 4: Safe Operating Area for TO-92
Figure 5: Safe Operating Area for SOT-223
Figure 6: Thermal Impedance for IPAK
Figure 7: Thermal Impedance for TO-92
Figure 8: Thermal Impedance for SOT-223
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STD1LNK60Z-1 - STQ1NK60ZR - STN1NK60Z
Figure 9: Output Characteristics
Figure 10: Transconductance
Figure 11: Gate Charge vs Gate-source Voltage
Figure 12: Transfer Characteristics
Figure 13: Statis Drain-Source On Resistance
Figure 14: Capacitance Variation
STD1LNK60Z-1 - STQ1NK60ZR - STN1NK60Z6/13
Figure 15: Normalized Gate Thereshold Volt-
age vs Temperature
acteristics
Figure 17: Maximum Avalanche Energy vs
Temperature
Figure 18: Normalized On Resistance vs Tem-
perature
Figure 20: Max Id Current vs Tc
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STD1LNK60Z-1 - STQ1NK60ZR - STN1NK60Z
Figure 21: Unclamped Inductive Load Test Cir-
cuit
Figure 23: Test Circuit For Inductive Load
Switching and Diode Recovery Times
Figure 24: Unclamped Inductive Wafeform
Figure 25: Gate Charge Test Circuit
