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STBP120CVDK6F-STBP120DVDK6F
Overvoltage protection device with thermal shutdown
September 2009 Doc ID15492 Rev 5 1/36
STBP120Overvoltage protection device with thermal shutdown
Features Input overvoltage protection up to 28 V Integrated high voltage N-channel MOSFET
switch Low RDS(on) of 90 mΩ Integrated charge pump Thermal shutdown protection Softstart feature to control the inrush current Enable input (EN) Fault indication output (FLT) IN input ESD withstand voltage up to ±15 kV
(air discharge), up to ±8 kV (contact discharge)
in typical application circuit with 1µF input
capacitor (±2 kV HBM for standalone device) Certain overvoltage options compliant with the
China Communications Standard YD/T 1591-
2006 (overvoltage protection only) Small, RoHS compliant 2.5 x 2 mm TDFN –
10-lead package.
Applications Smart phones Digital cameras PDA and palmtop devices MP3 players Low-power handheld devices.
Contents STBP1202/36 Doc ID 15492 Rev 5
Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.1 Input (IN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Power output (OUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Fault indication output (FLT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4 Enable input (EN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5 No Connect (NC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6 Ground (GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103.1 Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2 Normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.3 Undervoltage lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.4 Overvoltage lockout (OVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.5 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124.1 Calculating the power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 Calculating the junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3 PCB layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Typical application performance (STBP120DVDK6F) . . . . . . . . . . . . . 19 Typical thermal characteristics (STBP120DVDK6F) . . . . . . . . . . . . . . . 24 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
STBP120 Contents
Doc ID 15492 Rev 5 3/36
Tape and reel specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Package marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
List of tables STBP120
4/36 Doc ID 15492 Rev 5
List of tables
Table 1. Pin description and signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4. Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5. DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 6. TDFN – 10-lead, 2.5 x 2.0 x 0.75 mm body, pitch 0.50 mm,
package mechanical data dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 7. Carrier tape dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 8. Further tape and reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 9. Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 10. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 11. Marking description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 12. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
STBP120 List of figures
Doc ID15492 Rev 5 5/36
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. Typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5. Maximum MOSFET current at TA = 85 °C for various PCB thermal performance
and TJ = 125 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 6. Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7. Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 8. Disable (EN = high). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 9. FLT behavior in disable (EN = high) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10. Startup delay, ton . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 11. FLT indication delay (OK), t start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12. Output turn-off time, toff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 13. FLT indication delay (FAULT), t stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 14. Disable time, tdis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 15. Startup to overvoltage and startup V O(FLT) delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 16. Startup inrush current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 17. Output short-circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 18. Output short-circuit detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 19.ICC vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 20.I CC(STDBY) vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 21.I CC(UVLO) at 2.9 V vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 22. V OVLO vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 23. V UVLO vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 24. V OL(FLT) at 1 mA vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 25. R DS(on) at 1 A vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 26. TDFN – 10-lead, 2.5 x 2.0 x 0.75 mm body, pitch 0.50 mm,
package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 27. Tape and reel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 28. Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 29. Tape trailer/leader. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 30. Pin 1 orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Description STBP120
6/36 Doc ID 15492 Rev 5
1 Description
The STBP120 device provides overvoltage protection for input voltage up to +28 V. Its low DS(on) N-channel MOSFET switch protects the systems connected to the OUT pin against
failures of the DC power supplies in accordance with the China MII Communications
Standard YD/T 1591-2006.
In the event of an input overvoltage condition, the device immediately disconnects the DC
power supply by turning off an internal low RDS(on) N-channel MOSFET to prevent damage
to protected systems.
In addition, the device also monitors its own junction temperature and switches off the
internal MOSFET if the junction temperature exceeds the specified limit.
The device can be controlled by the microcontroller and can also provide status information
about fault conditions.
The STBP120 is offered in a small, RoHS-compliant TDFN – 10-lead (2.5 mm x 2 mm)
package.
Figure 1. Logic diagram
Figure 2. Pinout(1) Pin 1, PAD1 and PAD2 are No Connect (NC) and may be tied to IN or GND.
STBP120 Pin descriptions
Doc ID 15492 Rev 5 7/36
2 Pin descriptions
2.1 Input (IN)
Input voltage pin. This pin is connected to the DC power supply. External low ESR ceramic
capacitor of minimum value 1 µF must be connected between IN and GND. This capacitor is
for decoupling and also protects the IC against dangerous voltage spikes and ESD events.
This capacitor should be located as close to the IN pins as possible.
All IN pins (4, 5) must be hardwired to common supply.
2.2 Power output (OUT)
Output voltage pin. This pin is connected to the input through a low RDS(on) N-channel
MOSFET switch.
If no fault is detected and the STBP120 is not disabled (controlled by the EN input), this
switch is turned on and the output voltage follows the input voltage.
The output is disconnected from the input when the input voltage is under the UVLO
threshold or above the OVLO threshold, when the chip temperature is above the thermal
shutdown threshold or when the chip is disabled by the EN input.
There is a 50 ms delay, ton, between input voltage or junction temperature returns to
specified range and the power output is connected to the input (see Figure6).
All OUT pins (6, 7) must be hardwired to common supply.
2.3 Fault indication output (FLT)
The fault indication output (active-low - open-drain) provides information on the STBP120
state to the application controller. When FLT is active (i.e. driven low), this indicates the
STBP120 is in the undervoltage or overvoltage condition or thermal shutdown mode is
active. When the input voltage and junction temperature is in specified range, the FLT output
is in high impedance (Hi-Z) state.
There is an additional 50 ms delay, tstart, between the power output is connected to the input
and the FLT output is deactivated (i.e. in Hi-Z state) (see Figure6).
Since the FLT output is of open-drain type, it may be pulled up by an external resistor RP to
the controller supply voltage. If there is no need to use this output, it may be left
disconnected. The suitable RP resistor value is in range of 10 kΩ to 1 MΩ . o improve safety and to prevent damage to application circuits in the event of extreme
voltage or current conditions, an optional protective resistor RFLT can be connected between
the FLT output and the controller input. The suitable RFLT resistor value is in range of 22 kΩ
to 100 kΩ .
The function of the FLT output is not affected by the EN input state (see Figure 9).
Pin descriptions STBP120
8/36 Doc ID 15492 Rev 5
2.4 Enable input (EN)
This logical input (active-low) can be used to enable or disable the device. When EN input is
driven high, the STBP120 enters the standby mode and the power output is disconnected
from the input. When EN input is driven low and all operating conditions are within specified
limits, the power output is connected to the input.
Since the EN input has no internal pull-down resistor, its logical level must be defined by the
controller or by an external resistor. If there is no need to use this input, it should be
connected to the GND. o improve safety and to prevent damage to application circuits in the event of extreme
voltage or current conditions, an optional protective resistor REN can be connected between
the EN input and the controller output. The suitable resistor value is in range of 22 kΩ to
100 kΩ .
The EN input level has no impact on the functionality of FLT output (see Figure 8 and
Figure9).
2.5 No Connect (NC)
Pins 1, 8, 9 and exposed pads PAD1, PAD2 are No Connect. Pin 1 and exposed pads PAD1,
PAD2 may be tied to IN or GND if necessary.
2.6 Ground (GND)
Ground. All voltages are referenced to GND.
Table 1. Pin description and signal names
STBP120 Pin descriptions
Doc ID 15492 Rev 5 9/36
Figure 4. Typical application circuit(1)(2) Optional resistors REN, RFLT prevent damage to the controller under extreme voltage or current conditions and are not
required. Low ESR ceramic capacitor C1 is necessary to ensure proper function of the STBP120. Capacitor C2 is not
necessary for STBP120 but may be required by the charger IC. The STBP120 MOSFET switch topology allows the current to also flow in the reverse direction, from OUT to IN, which can
be useful for powering external peripherals from the system connector. The charger IC should not contain the reverse
diode to prevent the battery pack voltage from appearing on the system connector. If the reverse current (supply current) is
undesirable, it may be prevented by connecting a Schottky diode in series with the OUT pin. The voltage drop between IN
and charger is increased by the voltage drop across the diode.
Operation STBP120
10/36 Doc ID 15492 Rev 5
3 Operation
The STBP120 provides overvoltage protection for positive input voltage up to 28 V using
a built-in low R DS(on) N-channel MOSFET switch.
3.1 Power-up
At power-up, with EN = low, the MOSFET switch is turned on after a 50 ms delay, ton , after
the input voltage exceeds the UVLO threshold to ensure the input voltage is stabilized. After
an additional 50 ms delay, t start , the FLT indication output is deactivated (see Figure 6).
The FLT output state is valid for VIN input voltage 1.2 V or higher.
3.2 Normal operation
The device continuously monitors the input voltage and its own internal temperature so the
output voltage is kept within the specified range. Internal MOSFET switch is turned on and
the FLT output is not active.
The STBP120 enters normal operation state if the input voltage returns to the interval
between VUVLO and VOVLO - VHYS(OVLO) and the junction temperature falls below TOFF -
THYS(OFF). Internal MOSFET is turned on after the 50 ms delay ton to ensure that the
conditions have stabilized. Then, after an additional 50 ms delay, tstart, the FLT output is
deactivated (i.e. driven high). This behavior is equivalent to the startup shown on Figure6.
Note: The STBP120 MOSFET switch topology allows the current to also flow in the reverse
direction, i.e. from OUT to IN, which can be useful e.g. for powering external peripherals
from the system connector (see the supply current in Figure 4). At first, the current flows
through the MOSFET body diode. If the voltage that appears on the IN terminal is above the
UVLO threshold, the MOSFET is (after the 50 ms startup delay) turned on so the voltage
drop across STBP120 is significantly reduced. The charger IC should not contain the
reverse diode to prevent the battery pack voltage from appearing on the system connector.
If the reverse current is undesirable, it may be prevented by connecting a properly rated low
drop Schottky diode in series with the OUT pin. The voltage drop between IN and charger is
increased by the voltage drop across the diode.
Due to the MOSFET body diode, thermal shutdown protection is not functional for the
supply current.
3.3 Undervoltage lockout (UVLO) o ensure proper operation under any conditions, the STBP120 has an undervoltage lockout
(UVLO) threshold. For rising input voltage, the output remains disconnected from input until
VIN voltage exceeds the VUVLO threshold (3.25 V typ). The FLT output is driven low as long
as VIN is below the UVLO threshold (assuming the input voltage is above 1.2 V). For falling
input voltage, the UVLO circuit has a 50 mV hysteresis, VHYS(UVLO), to improve noise
immunity under transient conditions.
STBP120 Operation
Doc ID 15492 Rev 5 11/36
3.4 Overvoltage lockout (OVLO)
If the input voltage VIN rises above the threshold level VOVLO, the MOSFET switch is
immediately turned off (see Figure 7). At the same time, the fault indication output FLT is
activated (i.e. driven low). This device is equipped with hysteresis, VHYS(OVLO), to improve
noise immunity under transient conditions.
For available OVLO thresholds and hystereses, please see the Table5.
3.5 Thermal shutdown
If the STBP120 internal junction temperature exceeds the TOFF threshold, internal MOSFET
switch is turned off and the fault indication output FLT is driven low. o improve thermal stability, this circuit has a 20 °C hysteresis, THYS(OFF).
Application information STBP120
12/36 Doc ID 15492 Rev 5
4 Application information
4.1 Calculating the power dissipation
The maximum power dissipation of the STBP120 internal power MOSFET can be calculated
using following formula:D = I2 x R DS(on)(max),
Where I is current flowing through the MOSFET and R DS(on)(max) is maximum value of
MOSFET resistance.
Example:
Rload = 5 Ω, VIN = 5 V, R DS(on)(max) = 150 mΩ
I = VIN / (R DS(on)(max) + R load ) = 5 / (5 + 0.150) = 0.97 AD = 0.972 x 0.15 = 0.14 W
The power dissipation of reverse diode (in powering peripherals mode) can be estimated as D = (V OUT - VIN ) x I ≈ 0.7 x I.
4.2 Calculating the junction temperature
The maximum junction temperature for given power dissipation, ambient temperature and
thermal resistance junction - to - ambient can be calculated as
TJ = TA + 1.15 x PD x RthJA = TA + 1.15 x I2 x RDS(on)(max) x RthJA,
where TJ is junction temperature, TA is given ambient temperature, 1.15 is a derating factor
and RthJA is thermal resistance junction - to - ambient, depending on shape, dimension and
design of PCB. Two examples of PCB with appropriate thermal resistance are listed in
Table 3. The junction temperature may not exceed 125 °C (see Table 4), due to TOFF
(thermal shutdown threshold temperature).
Maximum allowed MOSFET current for ambient temperature TA = 85 °C and various RthJA
values are listed in Figure5.
Example: For conditions listed in previous example, well designed PCB (RthJA = 82 °C/W)
and TA = 85 °C, the maximum junction temperature is
85 + 1.15 x 0.14 x 82 = 98.2 °C.
4.3 PCB layout recommendations This device is intended as a protection device to the application from overvoltage.
It must be ensured that the clearances between PCB tracks satisfy the high voltage
design rules. Input capacitor, C1, should be located as close as possible to the STBP120 device.
It should be a Low-ESR ceramic capacitor. Also the protective resistors RFLT, REN
(if used) should be located close to the STBP120. For good thermal performance, it is recommended to connect the STBP120 exposed
thermal pads with the PCB ground plane. In most designs, this requires thermal vias
between the copper pads on PCB and the ground plane.
STBP120 Maximum rating
Doc ID 15492 Rev 5 13/36
5 Maximum rating
Stressing the device above the rating listed in the “absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 2. Absolute maximum ratings Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds. Maximum junction temperature is internally limited by the thermal shutdown circuit (not valid for reverse
current, see Chapter 3.2). System-level value (see Figure 4, C1 ≥ 1 µF low ESR ceramic capacitor). Human body model, 100 pF discharged through a 1.5kΩ resistor according the JESD22/A114
specification. Machine model, 200 pF discharged through all pins according the JESD22/A115 specification.
Maximum rating STBP120
14/36 Doc ID 15492 Rev 5
.
Figure 5. Maximum MOSFET current at TA = 85 °C for various PCB thermal
performance and TJ = 125 °C
Table 3. Thermal data The package is mounted on a 2-layers (1S) JEDEC board as per JESD51-7 without thermal vias
underneath the exposed pads. The package is mounted on a 4-layers (2S2P) JEDEC board as per JESD51-7 with 2 thermal vias (one
underneath each exposed pad) as per JESD-51-5. Thermal vias connected from exposed pad to 1'st buried copper plane of PCB.
STBP120 DC and AC parameters
Doc ID 15492 Rev 5 15/36 DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics tables that
follow are derived from tests performed under the measurement conditions summarized in
Table 4. Designers should check that the operating conditions in their circuit match the
operating conditions when relying on the quoted parameters.
Table 4. Operating and AC measurement conditions
Table 5. DC and AC characteristics
DC and AC parameters STBP120
16/36 Doc ID 15492 Rev 5 Test conditions described in Table 4 (except where noted). Guaranteed by design. Not tested in production.
Table 5. DC and AC characteristics (continued)
STBP120 Timing diagrams
Doc ID 15492 Rev 5 17/36
7 Timing diagrams
Figure 6. Startup(1) EN input is low.
Figure 7. Overvoltage protection(1) EN input is low.
Timing diagrams STBP120
18/36 Doc ID 15492 Rev 5
Figure 8. Disable (EN = high)(1) FLT output still indicates the VIN status.
Figure 9. FLT behavior in disable (EN = high)
