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T1001NL , TELECOMMUNICATIONS PRODUCTS
T1005 , TELECOMMUNICATIONS PRODUCTS
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STB9NK60ZT4-STP9NK60ZFP
N-CHANNEL 600V 0.85 OHM 7A TO-220/TO-220FP/D2PAK/I2PAK ZENER-PROTECTED SUPERMESH POWER MOSFET
1/13June 2002
STP9NK60Z - STP9NK60ZFP
STB9NK60Z - STB9NK60Z-1N-CHANNEL 600V - 0.85Ω - 7A TO-220/FP/D2 PAK/I2 PAK
Zener-Protected SuperMESH™Power MOSFET TYPICAL RDS(on) = 0.85 Ω EXTREMELY HIGH dv/dt CAPABILITY IMPROVED ESD CAPABILITY 100% AVALANCHE RATED GATE CHARGE MINIMIZED VERY LOW INTRINSIC CAPACITANCES VERY GOOD MANUFACTURING
REPEATIBILITY
DESCRIPTIONThe SuperMESH™ series is obtained through an
extreme optimization of ST’s well established strip-
based PowerMESH™ layout. In addition to pushing
on-resistance significantly down, special care is tak-
en to ensure a very good dv/dt capability for the
most demanding applications. Such series comple-
ments ST full range of high voltage MOSFETs in-
cluding revolutionary MDmesh™ products.
APPLICATIONS HIGH CURRENT, HIGH SPEED SWITCHING IDEAL FOR OFF-LINE POWER SUPPLIES,
ADAPTORS AND PFC
ORDERING INFORMATION
STP9NK60Z / STP9NK60ZFP / STB9NK60Z / STB9NK60Z-1
ABSOLUTE MAXIMUM RATINGS ) Pulse width limited by safe operating area
(1) ISD ≤7A, di/dt ≤200 μA, VDD ≤ V(BR)DSS, Tj ≤ TJMAX.
(*) Limited only by maximum temperature allowed
THERMAL DATA
AVALANCHE CHARACTERISTICS
GATE-SOURCE ZENER DIODE
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODESThe built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to souce. In this respect the Zener voltage is appropriate to achieve an efficient and cost-
effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage
of external components.
3/13
STP9NK60Z / STP9NK60ZFP / STB9NK60Z / STB9NK60Z-1
ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED)ON/OFF
DYNAMIC
SWITCHING ON
SWITCHING OFF
SOURCE DRAIN DIODE
Note:1. Pulsed: Pulse duration = 300 μs, duty cycle 1.5 %. Pulse width limited by safe operating area. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80%
VDSS.
STP9NK60Z / STP9NK60ZFP / STB9NK60Z / STB9NK60Z-1
Thermal Impedance For TO-220/D2PAK/I2PAK
Safe Operating Area For TO-220FPSafe Operating Area For TO-220/D2PAK/I2PAK
Output Characteristics
5/13
STP9NK60Z / STP9NK60ZFP / STB9NK60Z / STB9NK60Z-1
Normalized On Resistance vs Temperature
Capacitance VariationsGate Charge vs Gate-source Voltage
Static Drain-source On ResistanceTransconductance
Normalized Gate Threshold Voltage vs Temp.
STP9NK60Z / STP9NK60ZFP / STB9NK60Z / STB9NK60Z-1
Maximum Avalanche Energy vs Temperature
Normalized BVDSS vs TemperatureSource-drain Diode Forward Characteristics
7/13
STP9NK60Z / STP9NK60ZFP / STB9NK60Z / STB9NK60Z-1
Fig. 5: Test Circuit For Inductive Load Switching
Fig. 4: Gate Charge test Circuit
Fig. 3: Switching Times Test Circuit For Resistive Load
