STB5600 ,GPS RF FRONT-END ICFUNCTIONAL DESCRIPTIONThe STB5600 GPS front-end is fed with the signal from an active antenna, via ..
STB5NC50 ,N-CHANNEL 500VABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitSTP5NC50STP5NC50FPSTB5NC50/-1V Drain-source Volt ..
STB5NC50-1 ,N-CHANNEL 500VAPPLICATIONS■ HIGH CURRENT, HIGH SPEED SWITCHING■ SWITH MODE POWER SUPPLIES (SMPS)■ DC-AC CONVERTER ..
STB5NC70Z ,N-CHANNEL 700V 1.8 OHM 4.6A TO-220/TO-220FP/D2PAK/I2PAK ZENER-PROTECTED POWERMESH III MOSFETELECTRICAL CHARACTERISTICS (CONTINUED)SWITCHING ONSymbol Parameter Test Conditions Min. Typ. Max. U ..
STB5NK50Z ,N-CHANNEL 500VFeatures Figure 1: PackageTYPE V R I PwDSS DS(on) DSTB5NK50Z 500 V < 1.5 Ω 4.4 A 70 WSTB5NK50Z-1 50 ..
STB6000 ,QPSK DVB/DIRECTVTM DIRECT CONVERSION TUNER IC STB6000applications. The STB6000 is controlled by a simple two wire interface and has been designed to min ..
STV0987B/TR ,8 Megapixel imaging processorfeatures include face tracking, video stabilization and a smooth digital zoom, bringing an outstand ..
STV1601A ,SERIAL INTERFACE TRANSMISSION ENCODERAPPLICATIONS EXAMPLES.Serial data transmission of digital televisionsignal 525-625 lines.4:2:2 comp ..
STV160NF02L ,NELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED)OFFSymbol Parameter Test Condi ..
STV160NF02LAT4 ,N-CHANNEL 20V 0.0018 OHM 160A POWERSO-10 STRIPFET POWER MOSFETELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED)OFFSymbol Parameter Test Condi ..
STV160NF02LT4 ,N-CHANNEL 20VSTV160NF02LN-CHANNEL 20V - 0.0016Ω - 160A PowerSO-10STripFET™ II POWER MOSFETTYPE V R IDSS DS(on) D ..
STV160NF03L ,N-CHANNEL 30VELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED)OFFSymbol Parameter Test Condi ..
STB5600
GPS RF FRONT-END IC
STB5600GPS RF FRONT-END IC ONE CHIP SYSTEM TO INTERFACE
ACTIVE ANTENNA TO ST20GP1
MICROCONTROLLER COMPLETE RECEIVER USING NOVEL
DUAL CONVERSION ARCHITECTURE WITH
SINGLEIF FILTER MINIMUMEXTERNAL COMPONENTS COMPATIBLE WITH GPSL1 SPS SIGNAL INTERNALLY STABILISED POWER RAILS CMOS OUTPUT LEVELS FROM 3.3 TO 5.9V SUPPLY VOLTAGE TQFP32 PACKAGE
DESCRIPTIONThe STB5600, using STMicroelectronics HSB2,
High Speed Bipolar technology, implementsa
Global Positioning System RF front-end.
The chip provides down conversion from the GPS
(L1) signalat 1575 MHz via anIFof 20MHztoan
output frequencyof 4MHz suitable for ST20GP1
GPS processor. usesa single external reference oscillatorto
generate both RF local oscillator signals and the
processor reference clock.
PIN CONNECTION (top view)August 1998
TQFP32
MARKING:STB5600
TRACEAB. CODE
ASSY CODE
1/10
FUNCTIONAL DESCRIPTIONThe STB5600 GPS front-endis fed with the signal froman active antenna, viaa ceramic RF filter. The
gain between the antenna element and the STB5600is expectedto be between 10dB and 35dB
overall, madeupof the antenna LNA gain, the feeder loss, connector loss, and the ceramic filter loss. orderto usean off-the-shelfceramic filter, conventionally50 Ohms single ended,a matchingcircuitis
used. (see appendix A.1), which providesa 300 Ohm differential driveto the STB5600.A similar circuit
canbe usedto feed the LO signalif using the recommended low-cost oscillator circuit (appendix A.3).
Note that the STB5600 radio architecture and the oscillator described here are covered by various
patents heldby SGS-Thomson andby others. The useof the circuits describedin this data-sheetfor any
other purpose may infringesuch patents. RF SECTION
The differential input signalis amplifiedby the RF-Amp and mixed with the oscillator signal amplified
from the LO+,LO- inputsto generatea balanced 20.46MHzIF signal. The LO buffer amplifier may be
fed differentialor single ended signals,at levels between -60dBm and -20dBm. IF SECTION
The 20MHz differential signal from the mixeris fed throughan external LC filterto suppressundesirable
signals and mixer products. The multi-stage high-sensitivity limiting amplifieris connectedtoa D-type
latch clockedbyan internally derived 16MHz clock.. The effectof sampling the 20MHz signalat 16MHzto createa sub-sampling aliasat 4MHz. Thisis fedto the outputlevel-converters. DIVIDER SECTION
The 80MHz oscillator signal may be provided single-endedor differentiallyto the high impedance
80MHz+, 80MHz- inputs. Any unused inputs shouldbe connectedto GNDLOGIC viaa 1nF capacitor.
The 80MHz signalis amplified, then divided by5to create the 16.368MHz clock required by the
ST20GP1 processor, also usedto clock the outputlatchof the STB5600. OUTPUT SECTION
The output latch samples the 20.46MHz intermediate frequencyata 16.368MHz rate, performing the
dual functionof second downconversion and latching. The downconversion occurs by sub-sampling
aliasing, such that the digital output representsa 4.096MHz centre frequency
The output buffers perform level translation from the internal ECL levelsto CMOS compatible outputs
referredto external ground.
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value UnitVCC DC Supply Voltage 5.9 V
RF+, RF- RF Input 8 dBm Junction Temperature 150 oC
Tstg Storage Temperature Range -40to 125 oC
Rthj-amb Thermal Resistance Junction-ambient 80 o C/W
STB56002/10
PIN CONFIGURATIONApply 5Vat the CE, VCCRF,VCCIF,VCCLOGIC pins, apply3Vat the VCCDRIVE
Pin Symbol Typ. DC Bias Dexription External circuit IF1+ 3.6V Mixer Output1 see application circuit IF1- 3.6V Mixer Output2 see application circuit
3VCCRF 5V RF Power Supply 100nFto VEERF RF+ 3.5V RF Input AC Coupled RF- 3.5V RF Input AC Coupled
6VCCRF 5V RF Power Supply 100nFto VEERF
7VEERF 2V RF Voltage Reference 100nFto VCCRF GNDRF 0V RF Ground
9VCCRF 5V RF Power Supply 100nFto VEERF LO+ 3.5V Local Oscillator Input AC Coupled LO- 3.5V Local Oscillator Input AC Coupled VCCRF 5V RF Power Supply 100nFto VEERF VCCLOGIC 5V Logic Power Supply 100 nFto VEELOGIC 80 MHz+ 4V 80 MHz Clock Input AC Coupled 80 MHz- 4V 80 MHz Clock Input AC Coupled VCCLOGIC 5V Logic Power Supply 100 nFto VEELOGIC VEELOGIC 2V Logic Voltage Reference 100nFto VCCLOGIC CLOCK+ 0.3Vor3V 16 MHz Clock CMOS Output 7pFto GNDDRIVE Not Connected GNDDRIVE 0V CMOS Drive Ground DATA 0.3Vor3V 4 MHz Data CMOS Output 7pFto GNDDRIVE GNDDRIVE 0V CMOS Drive Ground VCCDRIVE 3V CMOS Drive Power Supply CE 3V Chip Enable GND 0V Substrate Ground GNDLOGIC 0V Logic Ground GNDIF 0V IF Ground VEEIF 2V IF Voltage Reference 100nFto VCCIF VCCIF 5V IF Power Supply 100 nFto VEEIF IF2- 4V Limiting Amplifier Input see application circuit IF2+ 4V Limiting Amplifier Input see application circuit VCCIF 5V IF Power Supply 100 nFto VEEIF
STB56003/10
ELECTRICAL SPECIFICATION (VVCCRF= 3.3V ...5.9V; VVCCIF= 3.3V ...5.9V; VVCC LOGIC= 3.3V
...5.9V VVCCDRIVE=3V;Ta =25oC unless otherwise specified)
LNA MIXER
Symbol Parameter Note Min. Typ. Max. UnitIVCCRF Supply Current VVCCRF=5V 20 25 mA
Zin Differential Input
Impedance 1575 MHz AC Coupledat RF+
RF- inputs
Zout Differential Output
Impedance20 MHz AC Coupledat IF1+ IF1-
outputs Voltage Conversion
Gain >3KΩ,PIN= -80 dBm
(Vin =75 μVpon 300Ω) dB
IIP1 Input Compression
Point (1dB)
(see application circuit) -60 dBm Noise figure 5 dB
fRF Input Signal
Frequency (L1)
1575 MHz
fIF Output Signal
Frequency MHz INPUT BUFFER
Symbol Parameter Note Min. Typ. Max. UnitZin Differential Input
Impedance 1555 MHz AC Coupledat LO+
LO- inputs
Input Signal Level -60 -40 -20 dBm
LIMITING AMPLIFIER
Symbol Parameter Note Min. Typ. Max. UnitIVCCIF Supply Current VVCCIF=5V 2.5 3.5 mA
Zin Differential Input
Impedance20 MHz AC Coupledat IF2+ IF2-
inputs KΩ Bandwidth 3dB 5 80 MHz
Sens Limiter sensitivity Input Signal@20 MHz AC Coupled 100 μVp
VINMAX Maximum Input Signal Input Signal@20 MHz AC Coupled 0.5 Vp
CLOCK INPUT BUFFER
Symbol Parameter Note Min. Typ. Max. UnitIVCCLOGIC Supply Current VVCC LOGIC=5V 5 7 mA
Zin Differential Input
Impedance80 MHz AC Coupledat 8O MHz+ MHz- inputs
Input Signal Level @80 MHz AC Coupledat 8O MHz+ MHz- inputs
5100 mVp Division Ratio 5
STB56004/10
ELECTRICAL CHARACTERISTICS (Continued)OUTPUT SECTION
Symbol Parameter Note Min. Typ. Max. UnitIVCCDRIVE Supply Current VVCCDRIVE =3V 8 mA
VOH High output voltage Vp= VVCCDRIVE =3V Vp-0.4 Vp V
VOL Low output voltage Vn= GNDDRIVE Vn Vn+0.4 V Rise Time CLOAD =7pF 6 ns Fall Time CLOAD =7pF 2 ns
APPLICATION CIRCUIT typical application circuitis shownin figure1. The RF input from the antenna downleadis fed viaa
ceramic filter and matching circuitto the RF+,RF- pins. The external LNAin the antenna should have
between10 and 35dBof amplifier gain,so the noise measuredina one MHz bandwidth shouldbe
-114dBmfor kTBin1 MHz 2dB LNA noise figure
+10/35 dB LNA gain (net)
Total -102/ 77dBmat connector.
Allowing 2dBfor filter loss, -104/-79is availableat the matching circuit.
Fig.1 Typical Application Circuit
STB56005/10
A.1 Matching NetworkThe
matching circuit maybea50 Ohm/ 300 Ohm balun transformer (figure2), buta more economical
solutionisa tuned matchas shown below.A single 10nH inductoris optimalin cost, but may not meet
the users tolerance requirements over spreadsof silicon and pcb material,asit has only around 1pF
tuning capacitance( 2pFin series with 2pF inside the package).
The first example (figure3) increases the capacitance witha discrete capacitor, and usesa lower
inductance value. Both examples assume that the ceramic filterisdc blocking, both inputto output, and
outputto ground.
The second (figure4) example allows optimum matching by rationing the capacitors appropriatelyto
achieve voltage gain commensurate with the impedance translation. Whileit hasa higher component
count,itis the version most tolerantof componentvariations and board capacitance.
Fig.2 Matching Network with Balun
Fig.3 Matching Network with two elements
STB56006/10
