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STA8058
GPS multi-chip module
A8058TESEO™
high performance GPS multichip module (MCM)
Data brief production data
Features GPS multichip module: STA2058 TESEO Baseband STA5620 RF Front-end Complete embedded memory system: Flash 256 KB + 16 Kbytes RAM 64 Kbytes. 66-MHz ARM7TDMI 32 bit processor High performance GPS engine (HPGPS) SBAS (WAAS and EGNOS) supported Sensitivity (-146 dBm acquisition, -159 dBm
tracking) Time to first fix (1 s reacquisition, 2.5 s hot start,
34 s warm start, 39 s cold start) Accuracy (2 m autonomous) Extensive GPS receiver interfaces: 32 GPIOs,
4 UARTs, 2 SPIs, 2 I2Cs, 1 CAN 2.0,
1 USB 1.1, 1 HDLC and 4 channels ADC Compatible with L1 signal (C/A code) ST proprietary technology CMOS Flash embebbed technology for
STA2058 BiCMOS Sige technology for STA5620 LFBGA104 lead-free package -40 °C to 85 °C operating temperature range Evaluation kits: STA8058 module reference designs
(17x19 mm and 25x25 mm) Evaluation board hosting STA8058 module
DescriptionSTA8058 TESEO MCM is a fully embedded GPS
engine integrating STA2058 TESEO baseband.
and STA5620 RF front-end. The embedded Flash
memory enables the equipment manufacturer to
load the entire GPS software (including tracking,
acquisition, navigation and data output) after
customising its interfaces to his needs.
A standard GPS library is available from ST. By
combining the ARM7TDMI microcontroller core
with on-chip Flash/RAM, 16-channel GPS
correlator DSP , RF Front-end and an extensive
range of interfaces on single package solution,
the ST A8058 provides a highly-flexible and cost-
effective solution for GPS applications.
Table 1. Device summary
Contents STA8058
Contents Features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52.1 Logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 System block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 LFBGA104 ball out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
STA8058 Features summary
1 Features summary ARM7TDMI 16/32 bit RISC CPU based host microcontroller running at a frequency up
to 66 MHz. Complete Embedded Memory System: Flash 256 Kbytes + 16 Kbytes (100 KB erasing/programming cycles) RAM 64 Kbytes. 16 channel High performance GPS correlation DSP. ST propietary technology: CMOS Flash embedded technology for baseband BiCMOS Sige for radio front-end SBAS (WAAS and EGNOS) supported. -40 °C to 85 °C operating temperature range. 104-pin LFBGA104 package. Power supply: 3.0 V to 3.6 V operating supply range for input/output periphery 3.0 V to 3.6 V operating supply range for A/D converter reference 1.8 V operating supply range for core supply provided by internal voltage regulator
with external stabilization capacitor or by external supply voltage 2.4 V to 3 V operating supply range for RF front-end section Reset and clock control unit able to provide low power modes (WAIT , SLOW, STOP,
Standby) and to generate the internal clock from the external reference through
integrated PLL. 32 programmable general purpose I/O, each pin programmable independently as
digital input or digital output; 30 are multiplexed with peripheral functions; 16 can
generate an interrupt on input level/transition. Real time clock module with 32 kHz low power oscillator and separate power supply to
continue running during stand-by mode. 16-bit Watchdog timer with 8 bits prescaler for system reliability and integrity. One CAN module compliant with the CAN specification V2.0 part B (active) and bit rate
can be programmed up to 1 MBaud. Four 16-bit programmable timers with 7 bit prescaler, up to two input capture/output
compare, one pulse counter function, one PWM channel with selectable frequency
each. 4 channels 12-bit sigma-delta analog to digital converter, single channel or multi
channel conversion modes, single-shot or continuous conversion modes, sample rate kHz, conversion range 0-2.5V . Three serial communication interfaces (UART) allow full duplex, asynchronous,
communications with external devices, independently programmable TX and RX baud
rates up to 625K baud. One UART adapted to suit smart card interface needs, for asynchronous SC as defined
by ISO 7816-3. It includes SC clock generation. Two serial peripheral interfaces (SPI) allow full duplex, synchronous communications
with external devices, master or slave operation, max baud rate of 5.5Mb/s. One SPI
may be used as multimedia card interface.
Features summary STA8058 Two I2 C interfaces provide multi-master and slave functions, support normal and fast 2 C mode (400 KHz), 7/10 bit addressing modes. One I2 C Interface is multiplexed with
one SPI, so either 2 x SPI + 1 x I2 C or 1 x SPI + 2 x I2 C may be used at a time. Enhanced interrupt controller supports 32 interrupt vectors, independently maskable,
with interrupt vector table for faster response and 16 priority levels, software
programmable for each source. Up to 2 maskable interrupts may be mapped on FIQ. Wake-up unit allows exiting from powerdown modes by detection of an event on two
external pins (one is active high and other is active low) or on internal Real Time Clock
alarm. USB unit V1.1 compliant, software configurable endpoint setting, USB suspend/resume
support High level data link controller (HDLC) unit supports full duplex operating mode, NRZ,
NRZI, FM0 and MANCHESTER modes, and internal 8-bit Baud Rate Generator. RF front-end features: LOW IF (4 MHz) architecture Compatible with GPS L1 signal VGA gain internally regulated On chip programmable PLL SPI interface
STA8058 Pin description
2 Pin description
2.1 Logic symbol
Figure 1. STA8058 TESEO MCM symbol
Pin description STA8058
2.2 System block diagram
Figure 2. STA8058 TESEO baseband block diagram
STA8058 Pin description
Figure 3. STA5620 RF front-end
