STA559BW13TR ,Digital Audio ICs, Sound Terminalsthermal characteristics . . . . . . 639 Package mechanical data . . . . 6410 Revision histor ..
STA5620A ,Automotive Fully integrated RF front-end receiver for GPS applicationsElectrical characteristics . . . . . . 125 Pin and I/O cells . . . . 155.1 Mode . . ..
STA5620A ,Automotive Fully integrated RF front-end receiver for GPS applicationsFeatures■ Low IF architecture (f = 4f )IF O■ Minimum external components■ VGA gain internally regul ..
STA575 ,100+100W STEREO BASH POWER AMPLIFIERSTA575100+100W STEREO POWER AMPLIFIERPRODUCT PREVIEW■ MONOCHIP BRIDGE STEREO AMPLIFIER ®ON BASH ARC ..
STA6610 , Dual N-Channel E nhancement Mode F ield E ffect Transistor
STA7360 ,20W BRIDGE/STEREO AUDIO AMPLIFIER WITH CLIPPING DETECTORSTA736020W BRIDGE/STEREO AUDIO AMPLIFIERWITH CLIPPING DETECTOR■ VERY FEW EXTERNAL COMPONENTS■ NO BO ..
STTH1R06A ,TURBO 2 ULTRAFAST HIGH VOLTAGE RECTIFIERFEATURES AND BENEFITS■ Ultrafast switching■ Low reverse recovery current■ Low thermal resistance■ R ..
STTH1R06RL ,TURBO 2 ULTRAFAST HIGH VOLTAGE RECTIFIERFEATURES AND BENEFITS■ Ultrafast switching■ Low reverse recovery current■ Low thermal resistance■ R ..
STTH1R06U ,TURBO 2 ULTRAFAST HIGH VOLTAGE RECTIFIERSTTH1R06®TURBO 2 ULTRAFAST HIGH VOLTAGE RECTIFIERTable 1: Main Product CharacteristicsI1 AF(AV)V600 ..
STTH20002TV1 ,TURBO 2 ULTRAFAST HIGH VOLTAGE RECTIFIERapplications.ABSOLUTE RATINGS (limiting values, per diode)Symbol Parameter Value UnitV Repetitive p ..
STTH20003TV1 ,HIGH FREQUENCY SECONDARY RECTIFIERFEATURES AND BENEFITSCOMBINES HIGHEST RECOVERY AND A2REVERSE VOLTAGE PERFORMANCEULTRAFAST, SOFT AND ..
STTH20004TV1 ,Ultrafast high voltage rectifierapplications, as an output Table 1. Device summaryrectification diode.Symbol ValueI Up to 2 x 120 A ..
STA559BW-STA559BW13TR
Digital Audio ICs, Sound Terminals
February 2014 DocID18190 Rev 2 1/67
A559BW5 V, 2 A, 2.1 channel high-efficiency digital audio system
Sound T erminal®
Datasheet - production data
Features Wide-range supply voltage, 4.5 V to 16V Three power output configurations: 2 channels of ternary PWM (2 x 3 W into at 5 V) + PWM output 2 channels of ternary PWM (2 x 3 W into at 5 V) + ternary stereo line-out 2.1 channels of binary PWM (left, right,
LFE) (2 x 0.7 W + 1 x 3 W into 4 at 5 V)
(2 x 1.4 W + 1 x 6 W into 2 at 5V) FFX with 100-dB SNR and dynamic range Selectable 32-to 192-kHz input sample rates I²C control with selectable device address Digital gain/attenuation +48dB to -80dB with
0.5-dB/step resolution Soft volume update Individual channel and master gain/attenuation Two independent limiters/compressors Dynamic range compression or anti-clipping
modes Audio presets: 15 preset crossover filters 5 preset anti-clipping modes Preset night-time listening mode Individual channel soft/hard mute Independent channel volume and DSP bypass 2-channel I²S input data interface Input and output channel mapping Automatic invalid-input detect Mute Automatic zero-detect mute Up to 4 user-programmable biquads/channel Three coefficients banks for EQ presets storing
with fast recall via I²C interface Bass/treble tones and de-emphasis control Selectable high-pass filter for DC blocking Advanced AM interference frequency
switching and noise suppression modes Selectable high- or low-bandwidth
noise-shaping topologies Selectable clock input ratio Thermal overload and short-circuit protection
embedded Video apps: 576 x fS input mode supported
Table 1. Device summary
Contents STA559BW2/67 DocID18190 Rev 2
Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.1 Connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4 Electrical specifications for the digital section . . . . . . . . . . . . . . . . . . . . . 12
3.5 Electrical specifications for the power section . . . . . . . . . . . . . . . . . . . . . 13
3.6 Power on/off sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Processing data paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 I²C bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185.1 Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1.1 Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1.2 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1.3 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1.4 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.3 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.3.1 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.3.2 Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.4 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.4.1 Current address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.4.2 Current address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.4.3 Random address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.4.4 Random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DocID18190 Rev 2 3/67
STA559BW Contents
6.1 Configuration registers (addr 0x00 to 0x05) . . . . . . . . . . . . . . . . . . . . . . . 22
6.1.1 Configuration register A (addr 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1.2 Configuration register B (addr 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.1.3 Configuration register C (addr 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1.4 Configuration register D (addr 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.1.5 Configuration register E (addr 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.1.6 Configuration register F (addr 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.2 Volume control registers (addr 0x06 - 0x0A) . . . . . . . . . . . . . . . . . . . . . . 40
6.2.1 Mute/line output configuration register (addr 0x06) . . . . . . . . . . . . . . . . 41
6.2.2 Master volume register (addr 0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.2.3 Channel 1 volume (addr 0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.2.4 Channel 2 volume (addr 0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.2.5 Channel 3 / line output volume (addr 0x0A) . . . . . . . . . . . . . . . . . . . . . 42
6.3 Audio preset registers (addr 0x0B and 0x0C) . . . . . . . . . . . . . . . . . . . . . 43
6.3.1 Audio preset register 1 (addr 0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.3.2 Audio preset register 2 (addr 0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.4 Channel configuration registers (addr 0x0E - 0x10) . . . . . . . . . . . . . . . . . 45
6.5 T one control register (addr 0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.6 Dynamic control registers (addr 0x12 - 0x15) . . . . . . . . . . . . . . . . . . . . . 47
6.6.1 Limiter 1 attack/release rate (addr 0x12) . . . . . . . . . . . . . . . . . . . . . . . . 47
6.6.2 Limiter 1 attack/release threshold (addr 0x13) . . . . . . . . . . . . . . . . . . . 47
6.6.3 Limiter 2 attack/release rate (addr 0x14) . . . . . . . . . . . . . . . . . . . . . . . . 48
6.6.4 Limiter 2 attack/release threshold (addr 0x15) . . . . . . . . . . . . . . . . . . . 48
6.6.5 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.7 User-defined coefficient control registers (addr 0x16 - 0x26) . . . . . . . . . . 52
6.7.1 Coefficient address register (addr 0x16) . . . . . . . . . . . . . . . . . . . . . . . . 52
6.7.2 Coefficient b1 data register bits (addr 0x17 - 0x19) . . . . . . . . . . . . . . . . 53
6.7.3 Coefficient b2 data register bits (addr 0x1A - 0x1C) . . . . . . . . . . . . . . . 53
6.7.4 Coefficient a1 data register bits (addr 0x1D - 0x1F) . . . . . . . . . . . . . . . 53
6.7.5 Coefficient a2 data register bits (addr 0x20 - 0x22) . . . . . . . . . . . . . . . . 53
6.7.6 Coefficient b0 data register bits (addr 0x23 - 0x25) . . . . . . . . . . . . . . . . 54
6.7.7 Coefficient read/write control register (addr 0x26) . . . . . . . . . . . . . . . . . 54
6.7.8 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.8 Variable max power correction registers (addr 0x27 - 0x28) . . . . . . . . . . 59
6.9 Distortion compensation registers (addr 0x29 - 0x2A) . . . . . . . . . . . . . . . 59
6.10 Fault detect recovery constant registers (addr 0x2B - 0x2C) . . . . . . . . . . 59
Contents STA559BW
4/67 DocID18190 Rev 2
6.11 Device status register (addr 0x2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
7.1 Applications schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
7.2 PLL filter circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
7.3 Typical output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
DocID18190 Rev 2 5/67
STA559BW List of figures
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 2. Pin connection PowerSSO-36 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3. Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 4. Power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 5. Power-off sequence for pop-free turn-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6. Left and right processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7. Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 8. Read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9. OCFG = 00 (default value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 10. OCFG = 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 11. OCFG = 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 12. OCFG = 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 13. Output mapping scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 14. 2.0 channels (OCFG = 00) PWM slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 15. 2.1 channels (OCFG = 01) PWM slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 16. 2.1 channels (OCFG = 10) PWM slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 17. Basic limiter and volume flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 18. Output configuration for stereo BTL mode (RL = 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 19. Applications circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 20. PowerSSO-36 power derating curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 21. PowerSSO-36 EPD outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
