STA450A ,XMRADIO SDARS SERVICE LAYER & SOURCE DECODERBlock DiagramI2C MASTER I2C SLAVE GPIO EXTERNALRS232(CAP I/F) (SYSCON I/F) INTERFACE INTERRUPTSPDIF ..
STA457C , PNP NPN Darlington H-bridge
STA457C , PNP NPN Darlington H-bridge
STA458C , PNPNPN H-bridge
STA458C , PNPNPN H-bridge
STA461 , Power Transistor Array
STT13005D ,High voltage fast-switching NPN power transistorElectrical characteristicsSymbol Parameter Test Conditions Min. Typ. Max. UnitCollector cut-off cur ..
STT1NF100 ,N-CHANNEL 100 VELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED)OFFSymbol Parameter Test Condi ..
STT2PF60L ,P-CHANNEL 60VELECTRICAL CHARACTERISTICS (T = 25 °C unless otherwise specified)caseOFFSymbol Parameter Test Condi ..
STT2PF60L ,P-CHANNEL 60VABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V = 0) 60 VDS GSV Drain- ..
STT3PF20V ,P-CHANNEL 20VSTT3PF20VP-CHANNEL 20V - 0.14 W - 2.2A SOT23-6L2.7-DRIVE STripFET™ II POWER MOSFETTYPE V R IDSS DS( ..
STT3PF30L ,P-CHANNEL 30VSTT3PF30LP-CHANNEL 30V - 0.14 Ω - 3A SOT23-6LSTripFET™ II POWER MOSFETTYPE V R IDSS DS(on) DSTT3PF3 ..
STA450A
XMRADIO SDARS SERVICE LAYER & SOURCE DECODER
1/66
STA450ASeptember 2003
FUNCTIONS XMRADIO SERVICE LAYER
DEMULTIPLEXING CHANNEL AUXILIARY DATA MANAGEMENT CONDITIONAL ACCESS CONTROL SERVICE COMPONENTS EXTRACTION SERVICE COMPONENTS DECRYPTION HIGH QUALITY AUDIO DECODING WITH
DATA RATE FROM 24kbps TO 96kbps HIGH QUALITY SPEECH DECODING WITH
DATA RATE FROM 4kbps TO 16kbps 44.1 AND 32KHz SAMPLING FREQUENCIES
SUPPORTED SYNCHRONIZATION ERROR DETECTION
WITH SW INDICATORS
PERIPHERALS HIGH SPEED SERIAL INPUT INTERFACE
(PCBITSTREAM INTERFACE) FULLY PROGRAMMABLE SERIAL PCM
OUTPUT INTERFACE IEC958 OUTPUT (S/PDIF) DATA OUTPUT PORT INTERFACE CONDITIONAL ACCESS PROCESSOR
INTERFACE (I2C MASTER) RS232 RX & TX INTERFACES EMBEDDED SYSTEM PLL EMBEDDED AUDIO PLL
LOW POWER TECHNOLOGY 1.8V 0.18μm TECHNOLOGY 3.3V CAPABLE I/Os
CONTROL I2C SLAVE CONTROL DEVICE ADDRESS: 1011100
DESCRIPTIONThe STA450A is designed for digital radio receivers
compatible with the XMRadio SDARS System and in-
tegrates all the functions needed to perform the Ser-
vice Layer and Source Decoding: Bitstream Synchronization Service Layer (SL) Demultiplexing Auxiliary Data Management Conditional Access (CA) Control Service Components Extraction Service Components Decryption Audio and Voice Decoding
The extracted Audio and Data are made available
through different interfaces: I2S Audio Output S/PDIF Output Data Output Port
XMRADIO SDARS SERVICE LAYER & SOURCE DECODER
STA450A 2/66
Figure 1. Service Layer and Source Decoder Block Diagram
Figure 2. Pin Connection
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STA450A
PIN FUNCTION
STA450A 4/66
A more detailed description of each pad type can be found in section 4.
Note: After an Hardware reset or power on all Bi Dir pins are configured as inputs.
PIN FUNCTION (continued)
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STA450A
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
DC ELECTRICAL CHARACTERISTCS (Tamb = -40 to 85°C, VDD = APLL_VDD = 1.65 to 1.95V, VDD_IO = 3.0to 3.6V unless otherwise specified).
(1) According to JEDEC specification on a 4 layers board
STA450A 6/66
Note 1. Guaranteed by Design
Note 2. Take into account 200 mV voltage drop in supply lines and Input/Output levels for frequency > 20MHz.
Note 3. Guaranteed by Ipu measurements
Note 4: Performed on all the input pins excluded the pull-down ones
Note 5: Performed on the I/O pins in tristate mode
1.0 FUNCTIONAL DESCRIPTION
1.1 PC BITSTREAM INTERFACEThe STA450A receives a serial data stream from the STA400A Channel Decoder via the PC Bitstream Inter-
face.
Figure 3 shows the stream format outputs from the CDEC (STA400A).
Figure 3. PC Bitstream Interface protocolTable 1 shows the correspondence between CDEC output clock divider register and the data rate on the bus
DC ELECTRICAL CHARACTERISTCS (continued)
7/66
STA450A
Table 1. Suggested CDEC clock divider/output rate correspondence.The 432ms frame is divided in slots of 448 bytes; the minimum number af slots in a 432ms frame is 50, corre-
sponding to a Tslot of 8.64ms. The transmission is on bursts, whose duration can go from 299us up to 1.199ms
(refer to table 1) according to the clock divider factor selected in the STA400A.
An overview of the connection between the STA400A and the STA450A is given in Figure 4.
Figure 4. STA400A/STA450A Connection.The synchronization process is started after a PCFS pulse is received through a Fast Interrupt port (pin 39). In
the case the PC Bitstream is stopped or the clock line is perturbed, the PCFS signal is used to reset the firmware
State Machine in the PC Bitsteam Interface (STA450A); this mechanism guarantees the start of the resync pro-
cess from a stable state.
The PC Bitstream Interface receives the data and fills the Header and the PC buffers; the Header buffer contains
the Header byte 1, the Header byte 2 and the Service preamble, the PC buffer contains the Payload channels
data.
1.2 STA450A Clocks Generation SystemThe STA450A Clocks generation System is shown in Figure 5: the 23.92MHz reference signal is entered in the
pin CLK_IN and is used to generate an internal system clock, with a System PLL, and an internal PCM clock,
with an Audio Fractional PLL .
A clock is made available at the output through the pin CLK_OUT.
STA450A 8/66
Figure 5. STA450A Clocks Generation System
The system clockThe system clock sent to the DSP core and the peripherals can be derived from 4 sources of clock and the se-
lection is performed by m4. The control of m4 is performed by the 2 input pins (CLK_M1 & CLK_M0): 00 sys_clk = CLK_IN 01 sys_clk = CLK_IN divided by 2 10 sys_clk = sys_clockout 11sys_clk = sys_clockout divided by 2
In the chip, the duty cycle of the internal system clock must be as close as possible 50%.
When the sys_clk is derived from the external clock source (CLK_IN), the divider by 2 can be used to ensure a
50% duty cycle.
When the sys_clk is derived from the system PLL, the duty cycle of the sys_clockout signal is 50%. The divider
by 2 can be used to slow down the clock at a lower frequency than the minimum that can achieve the System
PLL.
The CLK_OUT pad is driven by the sys_clk divided by a programmable division factor ranging from 1 to 16; the
sys_clk frequency is divided by 2 * (N+1), where N is the value programmed with register sys_paddiv [3:0].
Configuration Equations for the System PLL:
X = pllsys_Xmoduloout+------------- FrefIN+----------------- M1 reference
65536-----------------------------++ ⋅⋅=
9/66
STA450AN = pllsys_Nmodulo
M = pllsys_Mmodulo
The System PLL registers are configured through an indirection mechanism using the HOST_pll_add,
HOST_pll_data and HOST_pll_cmd registers; the HOST_pll_cmd register allows to update the control registers
of the PLL.
There are two levels of registers (Level 1 & Level 2). The first level of registers (Level 1) is configured through
the indirection mechanism. The second level of registers (Level 2) is a copy of the previous level in order to
update all the configuration bits at the same time. This mechanism avoids to have, during the configuration
phase, intermediate configurations that are not in line with the final desired configuration.
Assuming a 23.92MHz CLK input frequncy and CLK_M[1:0] = “11”, the default system frequency is 59.8MHz
See also the register description.
The Audio PLLThe "internal_pcmclk" of STA450A can be provided by two different sources: the Audio PLL or the OCLK port
of the chip.
The "m5" multiplexor and the direction of the OCLK tri-state port are configured by the register HOST_Pllpcm
(address 0x12).
An Audio PLL is embedded in STA450A.
The particularity of STA450A Audio PLL is the possibility to modify the Audio Sampling Frequency (LRCKT) in
steps of a few p.p.m. to compensate dynamically the audio sampling frequency offset between the receiver and
the broadcasting station; this compensation produces a jittering effect outside the audible range.
The STA450A receives from the STA400A (Channel Decoder) a dedicated signal every 432ms (PLL_SYNC)
and uses this signal to perform the audio sampling rate compensation; the control is done by the DSP core up-
dating the internal PLL registers.
Some PLL configuration registers are made available to the user to configure the PCM output according to the
used DAC.
The programmation for the desired Fs should be accomplished for both the Fs = 48KHz and Fs =
44.1KHz families before the start-up of the DSP (write in the register 0 x 4D)The OCLK frequency can be derived from the following formula: X is the value of the HOST_APLL48_XDIV register (HOST_APLL441_XDIV) register. M is the value of the HOST_APLL48_MDIV register (HOST_APLL441_MDIV) register. N is the value of the HOST_APLL48_NDIV register (HOST_APLL441_NDIV) register. FRAC is the decimal value of the concatenated registers HOST_APLL48_LSB and
HOST_APLL48_MSB (HOST_APLL441_LSB and HOST_APLL441_MSB) as follows:
FRAC = 256 * HOST_APLL48_MSB + HOST_APLL48_LSB (= 256 * HOST_APLL441_MSB +
HOST_APLL441_LSB)
The changes in the registers are not effective once the DSP has been started.
OCLK_freq 1+------------- 23.92MHz+ ---------------------------- M1 FRAC
65536-----------------++ ⋅⋅=
STA450A 10/66
According to the chosen oversampling factor, the following table permits to configure the dividers of the Audio PLL:
See also the register description.
1.3 PCM Output InterfaceThe decoded audio data can be output in serial PCM format.
The interface consists of the following signals:
SDO PCM Serial data output
SCKT PCM serial Clock Output
LRCKT Left/Right Channel Selection Clock
The output samples precision is selectable from 16 to 24 bits/word by setting the output precision (16, 18, 20
and 24bits) with the HOST_PCMCNF register; the same register is used to output data either with the most sig-
nificant bit first (MS) or least significant bit first (LS).
Figure 6 gives a description of the STA450A PCM Output Formats.
The SCKT signal is the bit clock for the serial output and is derived from the PCMCLK (OCLK) as in the following
formula:
SCKT = OCLK / 2*(HOST_PCMDIV + 1)
The number of bits to be transmitted to the DAC during one LRCKT clock period depends on the DAC precision
(16, 18, 20 or 24bits) and on the mode used to transmit the data (LRCKT_period equal to 16x2 or 32x2
SCKT_period - refer to figure 6).
The value of the HOST_PCMDIV register must be set accordingly to the previous consideration and to the DAC
Oversampling Factor (O_FAC). LRCKT_period = 16x2 SCKT_period
HOST_PCMDIV = (O_FAC/64) - 1 LRCKT_period = 32x2 SCKT_period
HOST_PCMDIV = (O_FAC/128) - 1
See also the register description.
11/66
STA450A
Figure 6. PCM Output Formats
1.4 Master Interface I2C The I2C master interface is used by the STA450A to communicate with the external Conditional Access Pro-
cessor (CAP) with the following protocol:
a) Write sequencesSTA450A 12/66
b) Read sequences
1.5 Data Output PortThe STA450A sends data through the Data Port. The Data Port consists of 3 lines: DP_CLK, DP_DATA,
DP_EN. The communication protocol is in burst.
The data changes on the DP_DATA line on the raising edge of the clock line DP_CLK, the DP_EN line defines
when the data is valid; DP_DATA and DP_EN must be sampled on the falling edge of DP_CLK.
The Service Component is output through the Data Port without adding a flag indicating the frame.
The Data Port burst rate is selectable through the XM Stack Command DATAPORT_CH_FREQUENCY (op-
code 0x07) from 1 MHz to 12 MHz, the default rate is 2 MHz.
Figure 7. Data Port Protocol Waveform Diagram
1.6 IEC958 Output (SPDIF)The SPDIF output is a Fully IEC958 formatted, single ended output for linear PCM output (left and right channel,
16,18, 20 & 24 bits) supporting the Consumer Mode.
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STA450A
1.7 Test Interfaces (RS232)The STA450A provides a RS232 RX and a RS232TX interfaces for testing purposes.
2.0 I2C BUS SPECIFICATIONThe STA450A supports the I2C protocol to communicate with the System Controller; the STA450A is always a
slave in its communication to the System Controller.
2.1 COMMUNICATION PROTOCOLA data change on the SDA line must only occur when SCLKI2C clock is low except for START and STOP con-
ditions. In that case, the transition is done when the clock is High.
A START condition is identified by a High to Low transition of the SDA line while the clock signal is High. A
START condition must precede any command for a data transfer.
A STOP condition is identified by a Low to High transition of the SDA line while the clock signal SCLKI2C is
High. A STOP condition terminates the communications between the IC and the master of the I2C bus.
An Acknowledge bit is used to indicate a successful data transfer. The bus transmitter, either the master or the
slave, releases the SDA line after sending 8 bits of data. During the 9th clock pulse, the receiver pulls the SDA
line to Low to acknowledge the reception of 8 bits of data.
During the data transfer, the I2C slave interface of the IC samples the SDA line on the rising edge of the
SCLKI2C clock. The SDA signal has to be stable during the rising edge of the clock and the data can change
only when the SCLKI2C clock line is low.
2.2 DEVICE ADDRESSINGTo start the communications between the master and the IC, the master must initiate the transfer with a START
condition. Then, the master has to send on the SDA line 8 bits (MSB first) corresponding to the device I2C ad-
dress (7 bits) and the mode bit RW (Read or Write).
The 7 most significant bits are the address of the device. For the STA450A the address is 0x5C (1011100 ad-
dress on 7 bits).
The 8th bit (LSB) selects a read (bit set to 1) or write (bit set to 0) operation. After a START condition, the IC
I2C slave interface identifies on the I2C bus the device address and, if the address matches, the IC acknowl-
edges this match on the SDA line during the 9th bit time frame. The byte following the device identification byte
is the address of the Host register to be accessed.
2.2.1 Sub-address initializationThis mode is used for the initialization of the Host address register (sub-address value). The Host address reg-
ister is the register that points the data register to be accessed (read or write).
2.2.2 "Sub-address + single write" & "Sub-address + multiple write"The second mode, the multiple write, exploits the autoincrementation of the sub-address pointer to avoid to ini-
tialize, for sequential accesses of the Host registers, the sub-address at each write operation. The length of a
multiple write is limited to the size of the Host register area (256 locations).
After a writing in the I2C interface a interrupt is generated to the core if the System controller set the bit in the
HOST_Cmd0 register.
STA450A 14/66
2.2.3 "Single read" & "multiple read" & "sub-address + single read" & "sub-address + multiple
read"The single read operations are performed from the current sub-address value. The sub-address value can be
initialized using the "sub_address" initialization" sequence presented in the previous transfer chart : see the
"combined format - sub-address + single read" diagram in the following chart.
The multiple read operations are performed from the current sub-address value and the sub-address register is
automatically incremented at each access. The sub-address value can be initialized using the "sub_address ini-
tialization" sequence presented in the previous transfer chart : see the "combined format - sub-address + mul-
tiple read" diagram in the following chart. The length of a multiple read is limited to the size of the Host register
area (256 locations). A multiple read is terminated by a Non Master Acknowledge followed by a STOP condition.
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STA450A
2.3 REGISTER MAPThe DSP HOST interface includes 256 registers.
STA450A 16/66
17/66
STA450ANote: NA: Not Applicable, NC: Not Change, R: Read Only, W: Write Only
Note1: These registers must be programmed before the start-up of the DSP (writing in register 0x4D)
2.4 REGISTER DESCRIPTION
HOST_VERSIONAddress : 0x00
Type : R
Software Reset : 0x10
Hardware Reset : 0x10
Description
The VERSION register is read-only and is used to identify the IC cut . The VERSION register holds the
cut number (binary decimal encoded)
HOST_IDAddress : 0x01
Type : R
Software Reset : 0x20
Hardware Reset : 0x20
Description
The HOST_ID register is read-only and is used to identify the IC on an application board. The ID is fixed
for all IC cut. The STA450A has the ID 0xAC.
7654 3210
7654 3210
STA450A 18/66
HOST_SOFTRESETAddress : 0x10
Type : W
Software Reset : NA
Hardware Reset : NA
Description
When bit 0 of this register is set, a soft reset occurs. The command registers and the interrupt registers
are cleared. The STA450A goes into idle mode.
HOST_PllpcmAddress : 0x12
Type : R - W
Software Reset : NC
Hardware Reset : 0x01
Description Not used
01 The PCMCLK pad is in input. This external PCMCLK source is sent to the I2S PCM output. The PCMCLK pad is in output. The internal audio PLL is generating the PCM clock for the I2S
PCM output. Same case as 10 but the PCMCLK is in tri-state mode
HOST_PlldataAddress : 0x11
Type : R/W
Software Reset : 0
Hardware Reset : 0
Description
Data to be copied in the Level 1 register for system PLL.
This register should be used in conjunction with registers HOST_Pllcmd and HOST_Plladd
HOST_PllcmdAddress : 0x18
Type : R/W
Software Reset : 0
7654 3210
7654 3210
7654 3210
7654 3210
19/66
STA450AHardware Reset : 0
Description
Bit [1:0] 00: no action is performed on the configuration registers of the Level 1.
01: Read action of the configuration registers. During this phase, the content of a selected (by
HOST_pll_add) configuration register of the Level 1 is copied into the HOST_pll_data register.
10: Write action of the configuration registers. During this phase, the content of the
HOST_pll_data
register is copied into a selected (by HOST_pll_add) configuration register of the Level 1.
11: do not use.
Bit 2 The bit controls the transfer of the data between the Level 1 and the Level 2 for the System
PLL. When this bit is set, all the registers of the Level 1 (sys_ndiv, sys_pdiv, sys_setupH,
sys_setupL, sys_enable) are copied into the registers of the Level 2 at the same time.
When this bit is cleared, all the Level 2 registers have a stable state independently of the Level
1 registers.
Bit3 Reserved
Bit 4 This bit must be used when switching from one System PLL configuration to the other one.
This bit must be used in conjunction with the bit [2].
HOST_PlladdAddress : 0x1D
Type : R/W
Software Reset : 0
Hardware Reset : 0
Description
In the follow table the description of the registers addressable by the HOST_Plladd to control the system PLL
7654 3210
STA450A 20/66
HOST_Cmd0Address : 0x13
Type : R/W
Software Reset : 0
Hardware Reset : 0
Description
A write into the bits 0 of this register generates a interrupt to the DSP core
HOST_I2cdivAddress : 0x1C
Type : R/W
Software Reset : 0x0B
Hardware Reset : 0x0B
Description
Hold time = HOST_I2cdiv/fc where the fc is the DSP system frequency.
HOST_SerialDivH - HOST_SerialDivL Address : 0x1F - 0x1E
Type : R/W
Software Reset : 0x00(HOST_SerialDivH) - 0x00 (HOST_SerialDivL)
Hardware Reset : 0x00 (HOST_SerialDivH) - 0x00 (HOST_SerialDivL)
Description
These registers are used to specify the frequency division factor of the system clock for the RS232
interface used for the emulation; bit rate = fc/(( HOST_SerialDivH << 8) | HOST_SerialDivL)
HOST_MemoryAccessAddress : 0x2B
Type : W
Software Reset : NA
Hardware Reset : 0
Description
Setting the bit 3 the core is enabled to access the ucode inside the memory
7654 3210
7654 3210
7654 3210
7654 3210
21/66
STA450A
HOST_ClkStopAddress : 0x3A
Type : R
Software Reset : NA
Hardware Reset : 0
Description
Clearing the bit 0 the clock to the core is started.
HOST_SOFTVERAddress : 0x40
Type : R/W
Software Reset : NA
Hardware Reset : NA
Description
The SOFTVER register is the version of the microcode which is running on the device (BCD).
This register is updated just after a soft reset of the device.
HOST_EVENTINTE 0 -1 -2 -3Address : 0x44 - 0x41
Type : R/W
Software Reset : NA
Hardware Reset : NA
Description
These registers are associated to error condition inside the STA450A.
The STA450A contains a 32 bits interrupt register associated with 32 bits enable register.
A bit set in this register will enable the generation of an external interrupt on the interrupt line.
The interrupt associated with each bit is given in the register INT description.
HOST_EVENTINT 0 - 1 - 2 - 3 7654 3210
7654 3210
7654 3210
7654 3210
STA450A 22/66
Address : 0x48 - 0x45
Type : R/W
Software Reset : NA
Hardware Reset : NA
Description
These registers are associated to error condition inside the STA450A.
A bit set in this table indicates the corresponding event has been occurred. Whenever the corresponding
bit in the INTE table has been set an external interrupt is generated.
To clear the bit a fast command has to be issued (see command description).
23/66
STA450A
HOST_ERRINTEH - HOST_ERRINTEL Address : 0x4A - 0x49
Type : R/W
Software Reset : NA
Hardware Reset : NA
Description
These registers are associated to error condition inside the STA450A.
The STA450A contains a 16 bit interrupt register associated with 16 bit enable register.
A bit set in this register will enable the generation of an external interrupt on the interrupt line. The
interrupt associated with each bit is given in the register INT description.
HOST_ERRINTH - HOST_ERRINTL Address : 0x4B - 0x4C
Type : R/W
Software Reset : NA
Hardware Reset : NA
Description
These registers are associated to error condition inside the STA450A.
A bit set in this table indicates the corresponding event has been occurred. Whenever the corresponding
bit in the INTE table has been set an external interrupt is generated.
To clear the bit a fast command has to be issued (see command description).
7654 3210
7654 3210
STA450A 24/66
HOST_STARTUPAddress : 0x4D
Type : R/W
Software Reset : NA
Hardware Reset : NA
Description
Writing 0x01 in this register enables the STA450A sw to leave the wait mode and to start normal process.
Using this register is also possible select special mode for silicon evaluation
Before to set this register is mandatory to program the system PLL , the Audio Fractional PLL and to
configure the PCM output format according to the application DAC.
HOST_PcmdivAddress : 0x4E
Type : R/W
Software Reset : NA
Hardware Reset : NA
Description
This register is red by STA450A before to leave the wait mode.
The SCLK signal is derived from the clock PCMCLK.
HOST_pcmdiv = (0_FAC/64) -1 in 16 bit mode
HOST_pcmdiv = (0_FAC/128) -1 in 18/20/24 bit mode
If Pcm_div is set to 0, the SCLK frequency is equal to the PCMCLK frequency.
HOST_PcmcnfAddress : 0x4F
Type : R/W
Software Reset : NA
Hardware Reset : NA
Description
This register is red by STA450A before to leave the wait mode.
Pcm_prec
Bit [1:0] 00: 16 bits mode.
01: 18 bits mode
10: 20 bits mode
11: 24 bits mode
7654 3210
7654 3210
7654 3210
25/66
STA450AInvert_sclk
Bit 2 0: LRCLK and PCM_OUT sampled on the falling edge of the SCLK
1: LRCLK and PCM_OUT sampled on the raising edge of the SCLK
Format
Bit 3 0: the output is in I2S format.
1: the output is in SONY format.
Invert_lrclk
Bit 4 0: LRCLK = 0 (low) will select the left channel.
1: LRCLK = 1 (high) will select the left channel
Pcm_dif
Bit 5 0: data are in the last SCLK cycles of LRCLK (right aligned)
1: data are in the first SCLK cycles of LRCLK (left aligned)
Pcm_ord
Bit 6 0: the transmission is done LSB first.
1: the transmission is done MSB first.
Pcm_iec_chansel
Bit 7 0: no iec958 output.
1: iec958 output, data on I2 S pin (PCSD) are no more valid.
HOST_APLL48_LSBAddress : 0x50
Type : R/W
Software Reset : NA
Hardware Reset : NA
HOST_APLL48_MSBAddress : 0x51
Type : R/W
Software Reset : NA
Hardware Reset : NA
Description
The HOST_APLL48_LSB and the HOST_APLL48_MSB are considered logically concatenated and
contain the fractional values for the Audio Fractional PLL for the Fs = 48KHz family.
The registers have to be programmed before the start_up of the DSP.
HOST_APLL48_XDIVAddress : 0x52
7654 3210
7654 3210
7654 3210
STA450A 26/66
Type : R/W
Software Reset : NA
Hardware Reset : NA
HOST_APLL48_MDIVAddress : 0x53
Type : R/W
Software Reset : NA
Hardware Reset : NA
HOST_APLL48_NDIVAddress : 0x54
Type : R/W
Software Reset : NA
Hardware Reset : NA
Description
The HOST_APLL48_XDIV, HOST_APLL48_MDIV and HOST_APLL48_NDIV registers are used to
configure the X, M and N divider of the Audio Fractional PLL for the Fs = 48KHz family.
The registers have to be programmed before the start_up of the DSP.
.HOST_APLL441_LSB
Address : 0x55
Type : R/W
Software Reset : NA
Hardware Reset : NA
HOST_APLL441_MSBAddress : 0x56
Type : R/W
Software Reset : NA
Hardware Reset : NA
Description
The HOST_APLL441_LSB and the HOST_APLL441_MSB are considered logically concatenated and
7654 3210
7654 3210
7654 3210
7654 3210
27/66
STA450Acontain the fractional values for the Audio Fractional PLL for the Fs = 44.1KHz family.
The registers have to be programmed before the start_up of the DSP.
HOST_APLL441_XDIVAddress : 0x57
Type : R/W
Software Reset : NA
Hardware Reset : NA
HOST_APLL441_MDIVAddress : 0x58
Type : R/W
Software Reset : NA
Hardware Reset : NA
HOST_APLL441_NDIVAddress : 0x59
Type : R/W
Software Reset : NA
Hardware Reset : NA
Description
The HOST_APLL441_XDIV, HOST_APLL441_MDIV and HOST_APLL441_NDIV registers are used to
configure the X, M and N divider of the Audio Fractional PLL for the Fs = 44.1KHz family.
The registers have to be programmed before the start_up of the DSP
ENABLE_IT432Address : 0x5A
Type : R/W
Software Reset : NA
Hardware Reset : NA
Description
Enabling of the Audio Fractional PLL control through the external 432ms interrupt on pin PLL_SYNC.
0: Disabled
1: Enabled
7654 3210
7654 3210
7654 3210
7654 3210
STA450A 28/66
IT432_CONFAddress : 0x5B
Type : R/W
Software Reset : NA
Hardware Reset : NA
Description
Allows to configure if the 432ms interrupt is rising or falling edge sensitive.
0: sensitive to falling edge
1: sensitive to rising edge
HOST_MAXDEVAddress : 0x5C
Type : R/W
Software Reset : NA
Hardware Reset : NA
Description
Divider factor for deviation value window
HOST_Decoder BitRateAddress : 0x5D
Type : R/W
Software Reset : NA
Hardware Reset : NA
Description
Audio decoder bit rate / 1K
HOST_BitstreamSynchroAddress : 0x5E
Type : R/W
Software Reset : NA
Hardware Reset : NA
Description
01: Not synchronised
10: Synchronised
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HOST_DataPortBitRateAddress : 0x5F
Type : R/W
Software Reset : NA
Hardware Reset : NA
Description
Data port bit rate / 1K (for bitrates ≥ 128Kbps 0xFF is reported)
10: Synchronised
HOST_EVENTINTE 4-5 Address : 0x66 - 0x67
Type : R - W
Software Reset : NA
Hardware Reset : NA
Description
These registers are associated to event condition inside the SDEC.
The SDEC contains a 16 bits interrupt register associated with 16 bits enable register.
A bit set in this register will enable the generation of an external interrupt on the interrupt line.
The interrupt associated with each bit is given in the register INT description.
HOST_EVENTINT 4-5Address : 0x68 - 0x69
Type : R - W
Software Reset : NA
Hardware Reset : NA
Description
These registers are associated to event condition inside the SDEC.
A bit set in this table indicates the corresponding event has been occurred. Whenever the corresponding
bit in the INTE table has been set an external interrupt is generated.
To clear the bit a fast command has to be issued (see command description).
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HOST_ AudioDecResultAddress : 0x6B
Type : R/W
Software Reset : NA
Hardware Reset : NA
Description
Upper nibble defines the decoder type:
0x10: AMBE
0x20: AAC
Lower nibble defines the Audio decoder result.
0x00 data ok
0x01 error concealment (only for AAC)
0x02 synchronization lost, output muted
HOST_ MFCAddress : 0x6C
Type : R/W
Software Reset : NA
Hardware Reset : NA
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STA450ADescription
Master Frame Counter LSB part (7 bits).
HOST_Page CtrlAddress : 0x7F
Type : R/W
Software Reset : NA
Hardware Reset : NA
Description
Bit 7 :more page to be download.
This bit is used also as Hand Shake bit.
The STA450A sets the bit as soon as the page is available and the System Controller clears the bit using
the dedicated Fast command (see command description) as soon as the page has been read. In case
the System Controller sends a new command and the MORE bit is set, the STA450A clears it
automatically.
Bit [6:0] :number - 1 of valid bytes in the current page
3.0 DSP COMMANDS QUICK REFERENCE
References: Service Layer Specification
XM Stack API Specification
3.1 CategoriesINIT 0x0X
SELECT 0x1X
INFO 0x2X
MISC 0x3X
FASTCMD 0x5X
3.2 COMMANDS7654 3210
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3.3 DSP COMMAND DESCRIPTIONThe commands are composed by two parts: the REQ one (request) and the CFM one (confirmation).
The REQ has to be written in the Command registers (0x6D - 0x7E); the CFM has to be read in the Data Page
registers (0x80 - 0xFF).
After a REQ has been issued the STA450A replies with a CFM within 5 MFP (5 x 432ms).
3.3.1 DSP_PWRUP_REQ
