STA369BWS ,2.1-channel 40-W high-efficiency digital audio system Sound TerminalFeatures2with fast recall via I C interface Wide-range supply voltage, 4.5 V to 21.5 V Extended ..
STA369BWSTR ,2.1-channel 40-W high-efficiency digital audio system Sound TerminalSTA369BWS2.1-channel 40-watt high-efficiency digital audio system® Sound TerminalDatasheet - produc ..
STA400A ,V(cc: -0.5 to +4V; V(in/out): -0.5 to +0.5V; XMRADIO SDARS channel decoderSTA400AXMRADIO SDARS CHANNEL DECODERFRONT END INTERFACE■ TWO INTERNAL 10 BIT A/D CONVERTERS■ TWO Q ..
STA401A. , NPN Darlington With built-in avalanche diode
STA402 , PNP Darlington General purpose
STA402 , PNP Darlington General purpose
STS7C4F30L ,N-P-CHANNEL 30V- 0.018 OHM- 7AELECTRICAL CHARACTERISTICS (T = 25 °C unless otherwise specified)caseOFFSymbol Parameter Test Condi ..
STS7DNF30L ,DUAL N-CHANNEL 30VELECTRICAL CHARACTERISTICS (T = 25 °C unless otherwise specified)caseOFFSymbol Parameter Test Condi ..
STS7NF30L ,NSTS7NF30L®N - CHANNEL 30V - 0.021Ω - 7A SO-8STripFET™ POWER MOSFETPRELIMINARY DATATYPE V R IDSS D ..
STS7NF60L ,N-CHANNEL 60VABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V = 0) 60 VDS GSV Drain- ..
STS7NF60L ,N-CHANNEL 60VELECTRICAL CHARACTERISTICS (T = 25 °C unless otherwise specified)caseOFFSymbol Parameter Test Condi ..
STS7PF30L ,P-CHANNEL 30VELECTRICAL CHARACTERISTICS (T = 25 °C UNLESS OTHERRWISE SPECIFIED)JOFFSymbol Parameter Test Conditi ..
STA369BWS-STA369BWSTR
2.1-channel 40-W high-efficiency digital audio system Sound Terminal
September 2014 DocID016861 Rev 7 1/92
A369BWS2.1-channel 40-watt high-efficiency digital audio system
Sound Terminal®
Datasheet - production data
Features Wide-range supply voltage, 4.5 V to 21.5 V Three power output configurations: 2 channels of ternary PWM
(2 x 20 W into 8 at 18 V) + PWM output 2 channels of ternary PWM
(2 x 20 W into 8 at 18 V) + ternary stereo
line-out 2.1 channels of binary PWM (left, right,
LFE) (2 x 9 W into 4 +1 x 20 W into 8
at 18 V) FFX with 100-dB SNR and dynamic range Scalable FFX modulation index (up to 100%) Selectable 32- to 192-kHz input sample ratesI2 C control with selectable device address Digital gain/attenuation +48 dB to -80 dB with
0.125-dB/step resolution Soft volume update with programmable ratio Individual channel and master gain/attenuation Two independent DRCs configurable as a
dual-band anti-clipper (B2 DRC) or as
independent limiters/compressors with
optional global DRC capability EQ-DRC for DRC based on filtered signals Dedicated LFE processing for bass boosting
with 0.125-dB/step resolution Audio presets: 15 preset crossover filters 5 preset anti-clipping modes Preset night-time listening mode Individual channel soft/hard mute Independent channel volume and DSP bypassI2 S input data interface Input and output channel mapping Automatic invalid input-detect mute Up to 8 user-programmable biquads/channel Three coefficients banks for EQ presets storing
with fast recall via I2 C interface Extended filter dynamics +4/-4 for better sound
shaping and easier filter implementation Bass/treble tones and de-emphasis control Selectable high-pass filter for DC blocking Advanced AM interference frequency
switching and noise suppression modes F3X™ advanced PWM modulation scheme for
carrier suppression (headphone or line output) Selectable high- or low-bandwidth
noise-shaping topologies Selectable clock input ratio 96-kHz internal processing sample rate with
quantization error noise shaping for very low
cut-off frequency filters Thermal overload and short-circuit protection
embedded Video apps: 576 x fS input mode supported PCB manufacturing short-circuit protection
technology
Table 1. Device summary
Order code Package PackagingSTA369BWS PowerSSO-36 EPD Tube
STA369BWSTR PowerSSO-36 EPD Tape and reel
Contents STA369BWS2/92 DocID016861 Rev 7
Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112.1 Connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.4 Electrical specifications for the digital section . . . . . . . . . . . . . . . . . . . . . 14
3.5 Electrical specifications for the power section . . . . . . . . . . . . . . . . . . . . . 15
3.6 Power on/off sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Serial audio interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184.0.1 Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.0.2 Delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.0.3 Channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Processing data paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 C bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216.1 Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1.1 Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
6.1.2 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
6.1.3 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
6.1.4 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
6.2 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.3 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.3.1 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
6.3.2 Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
6.4 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.4.1 Current address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
DocID016861 Rev 7 3/92
STA369BWS Contents6.4.2 Current address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
6.4.3 Random address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
6.4.4 Random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247.1 Configuration registers (addr 0x00 to 0x05) . . . . . . . . . . . . . . . . . . . . . . . 27
7.1.1 Configuration register A (addr 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . .27
7.1.2 Configuration register B (addr 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . .29
7.1.3 Configuration register C (addr 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . .32
7.1.4 Configuration register D (addr 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . .33
7.1.5 Configuration register E (addr 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . .35
7.1.6 Configuration register F (addr 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . .37
7.2 Volume control registers (addr 0x06 - 0x0A) . . . . . . . . . . . . . . . . . . . . . . 46
7.2.1 Mute/line output configuration register (addr 0x06) . . . . . . . . . . . . . . . .47
7.2.2 Master volume register (addr 0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
7.2.3 Channel 1 volume (addr 0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
7.2.4 Channel 2 volume (addr 0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
7.2.5 Channel 3 / line output volume (addr 0x0A) . . . . . . . . . . . . . . . . . . . . .48
7.3 Audio preset registers (addr 0x0B and 0x0C) . . . . . . . . . . . . . . . . . . . . . 49
7.3.1 Audio preset register 1 (addr 0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
7.3.2 Audio preset register 2 (addr 0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
7.4 Channel configuration registers (addr 0x0E - 0x10) . . . . . . . . . . . . . . . . . 51
7.5 Tone control register (addr 0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
7.6 Dynamic control registers (addr 0x12 - 0x15) . . . . . . . . . . . . . . . . . . . . . 53
7.6.1 Limiter 1 attack/release rate (addr 0x12) . . . . . . . . . . . . . . . . . . . . . . . .53
7.6.2 Limiter 1 attack/release threshold (addr 0x13) . . . . . . . . . . . . . . . . . . .53
7.6.3 Limiter 2 attack/release rate (addr 0x14) . . . . . . . . . . . . . . . . . . . . . . . .54
7.6.4 Limiter 2 attack/release threshold (addr 0x15) . . . . . . . . . . . . . . . . . . .54
7.6.5 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
7.6.6 Limiter 1 extended attack threshold (addr 0x32) . . . . . . . . . . . . . . . . . .58
7.6.7 Limiter 1 extended release threshold (addr 0x33) . . . . . . . . . . . . . . . . .59
7.6.8 Limiter 2 extended attack threshold (addr 0x34) . . . . . . . . . . . . . . . . . .59
7.6.9 Limiter 2 extended release threshold (addr 0x35) . . . . . . . . . . . . . . . . .59
7.7 User-defined coefficient control registers (addr 0x16 - 0x26) . . . . . . . . . . 59
7.7.1 Coefficient address register (addr 0x16) . . . . . . . . . . . . . . . . . . . . . . . .59
7.7.2 Coefficient b1 data register bits (addr 0x17 - 0x19) . . . . . . . . . . . . . . . .59
Contents STA369BWS4/92 DocID016861 Rev 7
7.7.3 Coefficient b2 data register bits (addr 0x1A - 0x1C) . . . . . . . . . . . . . . .60
7.7.4 Coefficient a1 data register bits (addr 0x1D - 0x1F) . . . . . . . . . . . . . . .60
7.7.5 Coefficient a2 data register bits (addr 0x20 - 0x22) . . . . . . . . . . . . . . . .60
7.7.6 Coefficient b0 data register bits (addr 0x23 - 0x25) . . . . . . . . . . . . . . . .61
7.7.7 Coefficient read/write control register (addr 0x26) . . . . . . . . . . . . . . . . .61
7.7.8 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
7.8 Variable max power correction registers (addr 0x27 - 0x28) . . . . . . . . . . 66
7.9 Distortion compensation registers (addr 0x29 - 0x2A) . . . . . . . . . . . . . . . 66
7.10 Fault detect recovery constant registers (addr 0x2B - 0x2C) . . . . . . . . . . 66
7.11 Device status register (addr 0x2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
7.12 EQ coefficients and DRC configuration register (addr 0x31) . . . . . . . . . . 68
7.13 Extended configuration register (addr 0x36) . . . . . . . . . . . . . . . . . . . . . . 69
7.13.1 Dual-band DRC (B2 DRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
7.13.2 EQ DRC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
7.14 Soft volume configuration registers (addr 0x37 - 0x38) . . . . . . . . . . . . . . 72
7.15 DRC RMS filter coefficients (addr 0x39-0x3E) . . . . . . . . . . . . . . . . . . . . . 73
7.16 Extra volume resolution configuration registers (addr 0x3F) . . . . . . . . . . 74
7.17 Short-circuit protection mode registers SHOK (addr 0x46) . . . . . . . . . . . 75
7.18 Quantization error noise correction (addr 0x48) . . . . . . . . . . . . . . . . . . . . 76
7.19 Extended coefficient range up to +4/-4 (addr 0x49, 0x4A) . . . . . . . . . . . . 77
7.20 Miscellaneous registers (addr 0x4B, 0x4C) . . . . . . . . . . . . . . . . . . . . . . . 78
7.20.1 MISC1 (addr 0x4B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
7.20.2 MISC2 (addr 0x4C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
7.21 Global DRC after B2DRC (GDRC) bit (addr 0x4D, bit D0) . . . . . . . . . . . . 81
7.22 Bad PWM detection registers (addr 0x4D, 0x4E, 0x4F) . . . . . . . . . . . . . . 82
7.23 Coefficient RAM CRC protection (addr 0x60-0x6C) . . . . . . . . . . . . . . . . . 82
7.23.1 BQCHKE registers (addr 0x60 - 0x62) . . . . . . . . . . . . . . . . . . . . . . . . .82
7.23.2 XCCHKE registers (addr 0x63 - 0x65) . . . . . . . . . . . . . . . . . . . . . . . . . .83
7.23.3 BQCHKR registers (addr 0x66 - 0x68) . . . . . . . . . . . . . . . . . . . . . . . . .83
7.23.4 XCCHKR registers (addr 0x69 - 0x6B) . . . . . . . . . . . . . . . . . . . . . . . . .83
7.23.5 CHKCTRL register (addr 0x6C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
7.23.6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858.1 Application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
DocID016861 Rev 7 5/92
STA369BWS Contents8.2 PLL filter circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
8.3 Typical output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
