STA309A13TR applications the additional 2 channels can be – Preset TV channel/commercial AGC mode used for audi ..
STA309A13TR applications. It provides output capabilities for ® ®DDX . In conjunction with a DDX power device, ..
STA310 ,6+2-CH. MULTISTANDARD AUDIO DECODERAPPLICATIONS■ Downmix for Dolby Prologic compatible.■ High-end audio equipment.❚ A separate (2-ch) ..
STA310 ,6+2-CH. MULTISTANDARD AUDIO DECODERFEATURES■ DVD Audio decoder:❚ Meridian Lossless Packing (MLP), with up to 6 channels,❚ Uncompressed ..
STA312A , NPN General purpose
STA321 ,4-channel digital audio system with FFX driverFeatures High efficiency FFX™ class-D modulator 100-dB dynamic range2 Two stereo channels with I ..
STS3C2F100 ,N-CHANNEL 100VELECTRICAL CHARACTERISTICS (T = 25 °C unless otherwise specified)jTAB.2 OFFSymbol Parameter Test Co ..
STS3C3F30L ,N-CHANNEL 30VELECTRICAL CHARACTERISTICS (T = 25 °C unless otherwise specified)caseOFFSymbol Parameter Test Condi ..
STS3DNE60L ,DUAL N-CHANNEL 60VSTS3DNE60L®N - CHANNEL 60V - 0.065W - 3A SO-8STripFET
STA309A-STA309A13TR
October 2009 Doc ID 13855 Rev 4 1/67
STA309A 5.1 to 2-channel downmix Simultaneous 5.1- and 2-channel downmix
outputs 3 preset volume curves 2 preset anti-clipping modes Preset movie nighttime listening mode Preset TV channel/commercial AGC mode 5.1, 2.1 bass management configurations 8 preset crossover filters Individual channel and master soft/hard mute Automatic zero-detect and invalid input mute Automatic invalid input detect mute Advanced PopFree operation
the STA309A provides high-quality,
high-efficiency, all digital amplification. The device
is extremely versatile, allowing inputs of most
digital formats including 6.1/7.1-channel and
192 kHz, 24-bit DVD-audio, DSD/SACD. In 5.1
applications the additional 2 channels can be
used for audio line-out or headphone drive. In
speaker mode, with 8 channel outputs in parallel,
the STA309A can deliver more than 1 W.
Table 1. Device summary
Contents STA309A
2/67 Doc ID 13855 Rev 4
Contents Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 C bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1 Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1.1 Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1.2 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1.3 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1.4 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.3.1 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.3.2 Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Application reference schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1 Register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.2 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.2.1 Configuration register A (0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.2.2 Configuration register B (0x01) - serial input formats . . . . . . . . . . . . . . 24
7.2.3 Configuration register C (0x02) - serial output formats . . . . . . . . . . . . . 26
7.2.4 Configuration register D (0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.2.5 Configuration register E (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.2.6 Configuration register F (0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
STA309A Contents
Doc ID 13855 Rev 4 3/67
7.2.7 Configuration register G (0x06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.2.8 Configuration register H (0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.2.9 Configuration register I (0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.2.10 Master mute register (0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.2.11 Master volume register (0x0A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.2.12 Channel 1 volume (0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.2.13 Channel 2 volume (0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.2.14 Channel 3 volume (0x0D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.2.15 Channel 4 volume (0x0E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.2.16 Channel 5 volume (0x0F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.2.17 Channel 6 volume (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.2.18 Channel 7 volume (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.2.19 Channel 8 volume (0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.2.20 Channel 1 volume trim, mute, bypass (0x13) . . . . . . . . . . . . . . . . . . . . 35
7.2.21 Channel 2 volume trim, mute, bypass (0x14) . . . . . . . . . . . . . . . . . . . . 35
7.2.22 Channel 3 volume trim, mute, bypass (0x15) . . . . . . . . . . . . . . . . . . . . 35
7.2.23 Channel 4 volume trim, mute, bypass (0x16) . . . . . . . . . . . . . . . . . . . . 36
7.2.24 Channel 5 volume trim, mute, bypass (0x17) . . . . . . . . . . . . . . . . . . . . 36
7.2.25 Channel 6 volume trim, mute, bypass (0x18) . . . . . . . . . . . . . . . . . . . . 36
7.2.26 Channel 7 volume trim, mute, bypass (0x19) . . . . . . . . . . . . . . . . . . . . 36
7.2.27 Channel 8 volume trim, mute, bypass (0x1A) . . . . . . . . . . . . . . . . . . . . 36
7.2.28 Channel input mapping channels 1 and 2 (0x1B) . . . . . . . . . . . . . . . . . 38
7.2.29 Channel input mapping channels 3 and 4 (0x1C) . . . . . . . . . . . . . . . . . 38
7.2.30 Channel input mapping channels 5 and 6 (0x1D) . . . . . . . . . . . . . . . . . 38
7.2.31 Channel input mapping channels 7 and 8 (0x1E) . . . . . . . . . . . . . . . . . 38
7.2.32 AUTO1 - Automode™ EQ, volume, GC (0x1F) . . . . . . . . . . . . . . . . . . . 39
7.2.33 AUTO2 - Automode™ bass management2 (0x20) . . . . . . . . . . . . . . . . 40
7.2.34 AUTO3 - Automode™ AM/prescale/bass management scale (0x21) . . 41
7.2.35 PREEQ - Preset EQ settings (0x22) . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.2.36 AGEQ - graphic EQ 80-Hz band (0x23) . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.2.37 BGEQ - graphic EQ 300-Hz band (0x24) . . . . . . . . . . . . . . . . . . . . . . . . 44
7.2.38 CGEQ - graphic EQ 1-kHz band (0x25) . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.2.39 DGEQ - graphic EQ 3-kHz band (0x26) . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.2.40 EGEQ - graphic EQ 8-kHz band (0x27) . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.2.41 Biquad internal channel loop-through (0x28) . . . . . . . . . . . . . . . . . . . . . 45
7.2.42 Mix internal channel loop-through (0x29) . . . . . . . . . . . . . . . . . . . . . . . 45
7.2.43 EQ bypass (0x2A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Contents STA309A
4/67 Doc ID 13855 Rev 4
7.2.44 Tone control bypass (0x2B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.2.45 Tone control (0x2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.2.46 Channel limiter select channels 1,2,3,4 (0x2D) . . . . . . . . . . . . . . . . . . . 47
7.2.47 Channel limiter select channels 5,6,7,8 (0x2E) . . . . . . . . . . . . . . . . . . . 47
7.2.48 Limiter 1 attack/release rate (0x2F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.2.49 Limiter 1 attack/release threshold (0x30) . . . . . . . . . . . . . . . . . . . . . . . . 48
7.2.50 Limiter 2 attack/release rate (0x31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.2.51 Limiter 2 attack/release threshold (0x32) . . . . . . . . . . . . . . . . . . . . . . . . 48
7.2.52 Bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.2.53 Channel 1 and 2 output timing (0x33) . . . . . . . . . . . . . . . . . . . . . . . . . . 53
7.2.54 Channel 3 and 4 output timing (0x34) . . . . . . . . . . . . . . . . . . . . . . . . . . 53
7.2.55 Channel 5 and 6 output timing (0x35) . . . . . . . . . . . . . . . . . . . . . . . . . . 53
7.2.56 Channel 7 and 8 output timing (0x36) . . . . . . . . . . . . . . . . . . . . . . . . . . 53
7.2.57 Channel I2 S output mapping channels 1 and 2 (0x37) . . . . . . . . . . . . . 54
7.2.58 Channel I2 S output mapping channels 3 and 4 (0x38) . . . . . . . . . . . . . 54
7.2.59 Channel I2 S output mapping channels 5 and 6 (0x39) . . . . . . . . . . . . . 54
7.2.60 Channel I2 S output mapping channels 7 and 8 (0x3A) . . . . . . . . . . . . . 54
7.2.61 Coefficient address register 1 (0x3B) . . . . . . . . . . . . . . . . . . . . . . . . . . 55
7.2.62 Coefficient address register 2 (0x3C) . . . . . . . . . . . . . . . . . . . . . . . . . . 55
7.2.63 Coefficient b1 data register, bits 23:16 (0x3D) . . . . . . . . . . . . . . . . . . . . 55
7.2.64 Coefficient b1 data register, bits 15:8 (0x3E) . . . . . . . . . . . . . . . . . . . . . 55
7.2.65 Coefficient b1 data register, bits 7:0 (0x3F) . . . . . . . . . . . . . . . . . . . . . . 55
7.2.66 Coefficient b2 data register, bits 23:16 (0x40) . . . . . . . . . . . . . . . . . . . . 55
7.2.67 Coefficient b2 data register, bits 15:8 (0x41) . . . . . . . . . . . . . . . . . . . . . 55
7.2.68 Coefficient b2 data register, bits 7:0 (0x42) . . . . . . . . . . . . . . . . . . . . . . 56
7.2.69 Coefficient a1 data register, bits 23:16 (0x43) . . . . . . . . . . . . . . . . . . . . 56
7.2.70 Coefficient a1 data register, bits 15:8 (0x44) . . . . . . . . . . . . . . . . . . . . . 56
7.2.71 Coefficient a1 data register, bits 7:0 (0x45) . . . . . . . . . . . . . . . . . . . . . . 56
7.2.72 Coefficient a2 data register, bits 23:16 (0x46) . . . . . . . . . . . . . . . . . . . . 56
7.2.73 Coefficient a2 data register, bits 15:8 (0x47) . . . . . . . . . . . . . . . . . . . . . 56
7.2.74 Coefficient a2 data register, bits 7:0 (0x48) . . . . . . . . . . . . . . . . . . . . . . 56
7.2.75 Coefficient b0 data register, bits 23:16 (0x49) . . . . . . . . . . . . . . . . . . . . 56
7.2.76 Coefficient b0 data register, bits 15:8 (0x4A) . . . . . . . . . . . . . . . . . . . . . 57
7.2.77 Coefficient b0 data register, bits 7:0 (0x4B) . . . . . . . . . . . . . . . . . . . . . . 57
7.2.78 Coefficient write control register (0x4C) . . . . . . . . . . . . . . . . . . . . . . . . . 57
7.3 Reading a coefficient from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
7.4 Reading a set of coefficients from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 58
STA309A Contents
Doc ID 13855 Rev 4 5/67
7.5 Writing a single coefficient to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
7.6 Writing a set of coefficients to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Equalization and mixing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
8.1 Postscale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
8.2 Variable max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
8.2.1 MPCC1-2 (0x4D, 0x4E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
8.3 Variable distortion compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
8.3.1 DCC1-2 (0x4F , 0x50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
8.4 PSCorrect registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
8.4.1 PSC1-2: ripple correction value (RCV) (0x51, 0x52) . . . . . . . . . . . . . . . 63
8.4.2 PSC3: correction normalization value (CNV) (0x53) . . . . . . . . . . . . . . . 63
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Trademarks and other acknowledgements . . . . . . . . . . . . . . . . . . . . . . 65 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
List of tables STA309A
6/67 Doc ID 13855 Rev 4
List of tables
Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 5. Recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 6. General interface electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 7. DC electrical characteristics: 3.3-V buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 8. Register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 9. MSC bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 10. MSC sample rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 11. Interpolation ratio bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 12. IR sample rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 13. DSPB bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 14. COS bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 15. SAI bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 16. SAIFB bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 17. SAI and SAIFB serial clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 18. SAO bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 19. SAOFB bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 20. SAO serial clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 21. OM bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 22. Output stage mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 23. CSZ bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 24. CSZ definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 25. MPC bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 26. CnBO bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 27. HPB bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 28. DRC bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 29. DEMP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 30. PSL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 31. BQL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 32. PWMS bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 33. PWM output speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 34. Register G bit definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 35. AM2E bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 36. HPE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 37. DCCV bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 38. MPCV bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 39. NSBW bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 40. ZCE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 41. SVE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 42. ZDE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 43. IDE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 44. BCLE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 45. LDTE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 46. ECLE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 47. PSCE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 48. EAPD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
STA309A List of tables
Doc ID 13855 Rev 4 7/67
Table 49. MV bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 50. CnV bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 51. CnVT bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 52. CnIM bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 53. AMEQ bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 54. AMV bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 55. AMDM bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 56. AMBMME bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 57. AMBMXE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 58. CSS and RSS bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 59. FSS and SUB bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 60. AMPS bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 61. MSA bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 62. AMAME bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 63. AMAM bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 64. XO bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 65. PEQ bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 66. xGEQ bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 67. CnBLP bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 68. CnMXLP bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 69. CnEQBP bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 70. BTC and TTC bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 71. Channel limiter mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 72. Attack rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 73. Release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 74. LnAT bits, anti-clipping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 75. LnRT bits, anti-clipping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 76. LnAT bits, dynamic range compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 77. LnRT bits, dynamic range compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 78. PWM slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 79. CnOM serial output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 80. RAM block for biquads, mixing, and bass management. . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 81. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
List of figures STA309A
8/67 Doc ID 13855 Rev 4
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 2. Channel signal flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 5. Read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 6. Reference schematic for STA309A-based application . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 7. Basic limiter and volume flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 8. Channel mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 9. TQFP64 (10 x 10 x 1.4 mm) package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
STA309A Block diagram
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1 Block diagram
Figure 1. Block diagram
Figure 2. Channel signal flow
Pin connections STA309A
10/67 Doc ID 13855 Rev 4
2 Pin connections
Figure 3. Pin connection (top view)
Table 2. Pin description
STA309A Pin connections
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Table 2. Pin description (continued)
Pin connections STA309A
12/67 Doc ID 13855 Rev 4
Table 2. Pin description (continued)
STA309A Electrical specification
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3 Electrical specification
3.1 Absolute maximum ratings
3.2 Thermal data
3.3 Recommended operating condition
Table 3. Absolute maximum ratings
Table 4. Thermal data
Table 5. Recommended operating condition
Electrical specification STA309A
14/67 Doc ID 13855 Rev 4
3.4 Electrical specifications
The following specifications are valid for VDD = 3.3 V ± 0.3 V, VDDA = 3.3 V ± 0.3 V and
Tamb= 0 to 70 °C, unless otherwise stated
Table 6. General interface electrical specifications The leakage currents are generally very small, < 1 nA. The values given here are maximum after an
electrostatic stress on the pin.
Table 7. DC electrical characteristics: 3.3-V buffers
STA309A Pin description
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4 Pin description
Master volume override (MVO)
This pin enables the user to bypass the volume control on all channels. When MVO is pulled
high, the master volume register is set to 0x00, which corresponds to its full scale setting.
The master volume register setting offsets the individual channel volume settings, which
default to 0 dB.
Serial data in (SDI_12, SDI_34, SDI_56, SDI_78)
Audio information enters the device here. Six format choices are available including I2S,
left-or right-justified, LSB or MSB first, with word widths of 16, 18, 20 and 24 bits.
RESET
Driving this pin low turns off the outputs and returns all settings to their defaults.2 C bus
The SA, SDA and SCL pins operate per the Phillips I2 C specification. See Section 5.
Phase locked loop (PLL)
The phase locked loop section provides the system timing signals and CKOUT.
Clock output (CKOUT)
System synchronization and master clocks are provided by the CKOUT.
PWM outputs (OUT1 through OUT8)
The PWM outputs provide the input signal for the power devices.
External amplifier power-down (EAPD)
This signal can be used to control the power-down of DDX power devices.
Serial data out (SDO_12, SDO_34, SDO_56, SDO_78)
These are the outputs for audio information. Six different formats are available including I2S,
left- or right-justified, LSB or MSB first, with word widths of 16, 18, 20 and 24 bits.
Device power-down (PWDN)
Pulling PWDN low begins the power-down sequence which puts the STA309A into a
low-power state. EAPD (pin 51) goes low approximately 30 ms later.
2 C bus operation STA309A16/67 Doc ID 13855 Rev 4
5 I2 C bus operation
The STA309A supports the I2 C protocol via the input ports SCL and SDA_IN (master to
slave) and the output port SDA_OUT (slave to master).
This protocol defines any device that sends data on to the bus as a transmitter and any
device that reads the data as a receiver.
The device that controls the data transfer is known as the master and the other as the slave.
The master always starts the transfer and provides the serial clock for synchronization. The
STA309A is always a slave device in all of its communications.
5.1 Communication protocol
5.1.1 Data transition or change
Data changes on the SDA line must only occur when the SCL clock is low. SDA transition
while the clock is high is used to identify a START or STOP condition.
5.1.2 Start condition
START is identified by a high to low transition of the data bus SDA signal while the clock
signal SCL is stable in the high state. A START condition must precede any command for
data transfer.
5.1.3 Stop condition
STOP is identified by low to high transition of the data bus SDA signal while the clock signal
SCL is stable in the high state. A STOP condition terminates communication between
STA309A and the bus master.
5.1.4 Data input
During the data input the STA309A samples the SDA signal on the rising edge of clock SCL.
For correct device operation the SDA signal must be stable during the rising edge of the
clock and the data can change only when the SCL line is low.
5.2 Device addressing
To start communication between the master and the Omega DDX core, the master must
initiate with a start condition. Following this, the master sends 8 bits onto the SDA line (MSB
first) corresponding to the device select address and read or write mode.
The 7 most significant bits are the device address identifiers, corresponding to the I2 C bus
definition. In the STA309A the I2 C interface has two device addresses depending on the SA
port configuration, 0x40 or 0100000x when SA = 0, and 0x42 or 0100001x when SA = 1.
The 8th bit (LSB) identifies read or write operation RW, this bit is set to 1 in read mode and 0
for write mode. After a START condition the STA309A identifies on the bus the device
STA309A I2 C bus operation
Doc ID 13855 Rev 4 17/67
address and if a match is found, it acknowledges the identification on SDA bus during the th -bit time. The byte following the device identification byte is the internal space address.
5.3 Write operation
Following the START condition the master sends a device select code with the RW bit set 0. The STA309A acknowledges this and the writes for the byte of internal address.
After receiving the internal byte address the STA309A again responds with an
acknowledgement.
5.3.1 Byte write
In the byte write mode the master sends one data byte, this is acknowledged by the Omega
DDX core. The master then terminates the transfer by generating a STOP condition.
5.3.2 Multi-byte write
The multi-byte write modes can start from any internal address. The master generating a
STOP condition terminates the transfer.
Figure 4. Write mode sequence
Figure 5. Read mode sequence
Application reference schematic STA309A
18/67 Doc ID 13855 Rev 4 Application reference schematic
Figure 6. Reference schematic for STA309A-based application
STA309A Registers
Doc ID 13855 Rev 4 19/67
7 Registers
7.1 Register summary
Table 8. Register summary
Registers STA309A
20/67 Doc ID 13855 Rev 4
Table 8. Register summary (continued)
STA309A Registers
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Table 8. Register summary (continued)
Registers STA309A
22/67 Doc ID 13855 Rev 4
7.2 Register description
7.2.1 Configuration register A (0x00)
The STA309A supports sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz,
176.4 kHz, 192 kHz, and 2.8224 MHz DSD. Therefore, the internal clocks are: 65.536 MHz for 32 kHz 90.3168 MHz for 44.1 kHz, 88.2 kHz, 176.4 kHz, and DSD 98.304 MHz for 48 kHz, 96 kHz, and 192 kHz
The external clock frequency provided to the XTI pin must be a multiple of the input sample
frequency (fs). The relationship between the input clock and the input sample rate is
determined by both the MCSn and the IRn (input rate) register bits. The MCSn bits
determine the PLL factor generating the internal clock and the IRn bits determine the
oversampling ratio used internally.
Table 9. MSC bits
Table 10. MSC sample rates
STA309A Registers
Doc ID 13855 Rev 4 23/67
Interpolation ratio select
The STA309A has variable interpolation (oversampling) settings such that internal
processing and DDX output rates remain consistent. The first processing block interpolates
by either 4 times, 2 times, or 1 time (pass-through).
The oversampling ratio of this interpolation is determined by the IR bits.
I
Setting the DSPB bit bypasses the biquad function of the Omega DDX core.
Table 11. Interpolation ratio bits
Table 12. IR sample rates
Table 13. DSPB bit
Table 14. COS bits
Registers STA309A
24/67 Doc ID 13855 Rev 4
7.2.2 Configuration register B (0x01) - serial input formats
Serial data interface
The STA309A audio serial input interfaces with standard digital audio components and
accepts a number of serial data formats. STA309A always acts a slave when receiving audio
input from standard digital audio components. Serial data for eight channels is provided
using 6 input pins: left/right clock LRCKI (pin 10), serial clock BICKI (pin 11), serial data 1
and 2 SDI12 (pin 9), serial data 3 and 4 SDI34 (pin 8), serial data 5 and 6 SDI56 (pin 7), and
serial data 7 and 8 SDI78 (pin 6). The SAI/SAIFB register (Configuration Register B,
address 0x01) is used to specify the serial data format. The default serial data format is I2S,
MSB-first. Available formats are shown in the tables and figure that follow.
Note: Serial input and output formats are specified separately
For example, SAI = 1110 and SAIFB = 1 would specify right-justified 16-bit data, LSB-first.
Table 15. SAI bits
Table 16. SAIFB bit
STA309A Registers
Doc ID 13855 Rev 4 25/67
The table below lists the serial audio input formats supported by STA309A as related to
BICKI= 32 * fs, 48 * fs, 64 * fs, where sampling rate, fs = 32, 44.1, 48, 88.2, 96, 176.4,
192 kHz.
Table 17. SAI and SAIFB serial clock
Registers STA309A
26/67 Doc ID 13855 Rev 4
7.2.3 Configuration register C (0x02) - serial output formats
The STA309A features a serial audio output interface that consists of 8 channels. The serial
audio output always acts as a slave to the serial audio input interface and, therefore, all
output clocks are synchronous with the input clocks. The output sample frequency (fs) is
also equivalent to the input sample frequency. In the case of SACD/DSD input, the serial
audio output acts as a master with an output sampling frequency of 176.4 kHz. The output
serial format can be selected independently from the input format and is done via the SAO
and SAOFB bits.
Table 18. SAO bits
Table 19. SAOFB bit
Table 20. SAO serial clock
STA309A Registers
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7.2.4 Configuration register D (0x03)
The DDX power output mode selects how the DDX output timing is configured. Different
power devices use different output modes. The STA50x recommended use is OM = 10.
Table 20. SAO serial clock (continued)
Table 21. OM bits
Table 22. Output stage mode
Table 23. CSZ bits
Registers STA309A
28/67 Doc ID 13855 Rev 4
Setting the MPC bit turns on special processing that corrects the STA50x power device at
high power. This mode should lower the THD+N of a full STA50x DDX system at maximum
power output and slightly below. This mode will only be operational in OM[1,0]= 01.
7.2.5 Configuration register E (0x04)
Each individual channel output can be set to output a binary PWM stream. In this mode
output A of a channel will be considered the positive output and output B is negative inverse.
Table 24. CSZ definition
Table 25. MPC bit
Table 26. CnBO bits
STA309A Registers
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7.2.6 Configuration register F (0x05)
The STA309A features an internal digital high-pass filter for the purpose of AC coupling. The
purpose of this filter is to prevent DC signals from passing through a DDX amplifier. DC
signals can cause speaker damage.
If HPB = 1, then the filter that the high-pass filter utilizes is made available as user-
programmable biquad#1.
Both limiters can be used in one of two ways, anti-clipping or dynamic range compression.
When used in anti-clipping mode the limiter threshold values are constant and dependent on
the limiter settings.
In dynamic range compression mode the limiter threshold values vary with the volume
settings allowing a nighttime listening mode that provides a reduction in the dynamic range
regardless of the volume level.
By setting this bit to one de-emphasis will implemented on all channels. When this is used it
takes the place of biquad #7 in each channel and any coefficients using biquad #1 will be
ignored. DSPB (DSP bypass) bit must be set to 0 for de-emphasis to function.
Table 27. HPB bit
Table 28. DRC bit
Table 29. DEMP bit
Registers STA309A
30/67 Doc ID 13855 Rev 4
The Postscale function can be used for power-supply error correction. For multi-channel
applications running off the same power-supply, the postscale values can be linked to the
value of channel 1 for ease of use and update the values faster.
For ease of use, all channels can use the biquad coefficients loaded into the channel 1
coefficient RAM space by setting bit BQL to 1. Therefore, any EQ updates only have to be
performed once.
Table 30. PSL bit
Table 31. BQL bit
Table 32. PWMS bits
Table 33. PWM output speed
STA309A Registers
Doc ID 13855 Rev 4 31/67
7.2.7 Configuration register G (0x06)
The STA309A features a DDX processing mode that minimizes the amount of noise
generated in frequency range of AM radio. This mode is intended for use when DDX is
operating in a device with an AM tuner active. The SNR of the DDX processing is reduced to
~83 dB in this mode, which is still greater than the SNR of AM radio.
The STA309A features a 2 DDX processing modes that minimize the amount of noise
generated in frequency range of AM radio. This second mode is intended for use when DDX
is operating in a device with an AM tuner active. This mode eliminates the noise-shaper.
Channels 7 and 8 can be configured to be processed and output in such a manner that
headphones can be driven using and appropriate output device. This signal is a differential
3-wire drive called DDX Headphone.
Table 34. Register G bit definitions
Table 35. AM2E bit
Table 36. HPE bit
Registers STA309A
32/67 Doc ID 13855 Rev 4
7.2.8 Configuration register H (0x07)
The ZCE bit enables zero-crossing volume adjustments. When volume is adjusted on digital
zero-crossings no clicks will be audible.
Table 37. DCCV bit
Table 38. MPCV bit
Table 39. NSBW bit
Table 40. ZCE bit
Table 41. SVE bit
Table 42. ZDE bit
STA309A Registers
Doc ID 13855 Rev 4 33/67
Setting the ZDE bit enables the zero-detect automatic mute. The zero-detect circuit looks at
the input data to each processing channel after the channel-mapping block. If any channel
receives 2048 consecutive zero value samples (regardless of fs) then that individual
channel is muted if this function is enabled.
Setting the IDE bit enables this function, which looks at the input I2 S data and will
automatically mute if the signals are perceived as invalid.
Detects loss of input MCLK in binary mode and will output 50% duty cycle.
Actively prevents double trigger of LRCLK.
When active will issue a device power down signal (EAPD) on clock loss detection
7.2.9 Configuration register I (0x08)
This feature utilizes an ADC on SDI78 that provides power supply ripple information for
correction. Registers PSC1, PSC2, PSC3 are utilized in this mode.
Table 43. IDE bit
Table 44. BCLE bit
Table 45. LDTE bit
Table 46. ECLE bit
Table 47. PSCE bit
Registers STA309A
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7.2.10 Master mute register (0x09)
7.2.11 Master volume register (0x0A)
Note: Value of volume derived from MVOL is dependent on AMV Automode volume settings.
7.2.12 Channel 1 volume (0x0B)
7.2.13 Channel 2 volume (0x0C)
7.2.14 Channel 3 volume (0x0D)
7.2.15 Channel 4 volume (0x0E)
Table 48. EAPD bit
