STA308 Fast Delivery |IC PHOENIX CO.,LIMITED

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STA308
MULTICHANNEL DIGITAL AUDIO PROCESSOR WITH DDX
STA308 8 DDXTM Channels Capability (24 bit) From 32kHz to 192kHz Input Sample Rates
Supported Volume Control from 0 to -100dB (0.5 dB steps) Variable Digital Gain from 0 to 24dB (0.5dB
steps) with Digital Limiter Functionality and
Variable Attack and Release Time I2S Inputs and Outputs Individual Channel and Master Gain/
Attenuation Individual Channel Mute and Zero Input Detect
Auto-Mute Selectable Serial Audio Data Interface Bass/Treble Controls Channel Mapping of any Input to any
Processing/DDXTM Channel Active Crossover Capability DC Blocking Selectable High-Pass Filter Selectable Bass Management on Channel 6 Selectable Adjacent Channel Mixing Capability Selectable DDXTM Headphone Output on
Channels 7 & 8 Selectable Clock Input Ratio Selectable De-emphasis Selectable DDXTM Ternary, or Binary PWM
output AM Interference Reduction Mode I2C Control
DESCRIPTION
The STA308 is a single chip solution for digital audio
processing and control in multi-channel applications.
It provides output capabilities for DDXTM (Direct Digi-
tal Amplification). In conjunction with a DDXTM power
device, it provides high-quality, high-efficiency, all
digital amplification. The device is extremely versatile
allowing for input of most digital formats including 6.1
channel and 192kHz, 24-bit DVD-Audio.
The internal 24-bit DSP allows for high resolution
processing at all standard input sample frequencies.
Processing includes volume control, filtering, bass
management, gain compression/limiting and PCM
and DDXTM outputs. Filtering includes five user-pro-
grammable 28-bit biquads for EQ per channel, as
well as bass, treble and DC blocking. External clock-
ing can be provided at 4 different ratios of the input
sample frequency. All sample frequencies are up-
sampled for processing. Each internal processing
channel can receive any input channel, allowing flex-
ibility and the ability to perform active digital cross-
over for powered loudspeaker systems.
The serial audio data interface accepts many differ-
ent formats, including the popular I2S format. Eight
channels of DDX processing are performed.
PRODUCT PREVIEW
MULTICHANNEL DIGITAL AUDIO PROCESSOR WITH DDX™
STA308
BLOCK DIAGRAM
Figure 1. Signal Flow Diagram
STA308
IN CONNECTION (Top view)
PIN FUNCTION
STA308
PIN FUNCTION (continued)
STA308
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
RECOMMENDED DC OPERATING CONDITIONS
STA308
ELECTRICAL CHARACTERISTCS (VDD3 = 3.3V ± 0.3V; VDD = 2.5V ± 0.2V; Tamb = 0 to 70 °C; unless other-
wise specified)
GENERAL INTERFACE ELECTRICAL CHARACTERISTICS
Note 1: The leakage currents are generally very small, < 1na. The values given here are maximum after an electrostatic stress on the pin.
Note 2: Human Body Model
DC ELECTRICAL CHARACTERISTICS: 3.3V BUFFERS
DC ELECTRICAL CHARACTERISTICS: 2.5V BUFFERS
Notes:1. Source/Sink current under worst-case conditions.
STA308
1.0 PIN DESCRIPRTION
1.1 MVO: Master Volume Override
This pin enables the user to bypass the Volume Control on all channels. When MVO is pulled High, the Master
Volume Register is set to 00h, which corresponds to its Full Scale setting. The Master Volume Register Setting
offsets the individual Channel Volume Settings, which default to 0dB.
1.2 SDI_12 through 78: Serial Data In
Audio information enters the device here. Six format choices are available including I2S, left- or right-justified,
LSB or MSB first, with word widths of 16, 18, 20 and 24 bits.
1.3 RESET
Driving this pin (low) turns off the outputs and returns all settings to their defaults.
1.4 I2C
The SA, SDA and SCL pins operate per the Philips I2C specification. See Section 2.
1.5 PLL: Phase Locked Loop
The phase locked loop section provides the System Timing Signals and CKOUT.
1.6 CKOUT: Clock Out
System synchronization and master clocks are provided by the CKOUT.
1.7 OUT1 through OUT8: PWM Outputs
The PWM outputs provide the input signal for the power devices.
1.8 EAPD: External Amplifier Power-Down
This signal can be used to control the power-down of DDX power devices.
1.9 SDO_12 through 78: Serial Data Out
Audio information exits the device here. Six different format choices are available including I2S, left- or right-
justified, LSB or MSB first, with word widths of 16, 18, 20 and 24 bits.
1.10 PWDN: Device Power-Down
This puts the STA308 into a low-power state via appropriate power-down sequence. Pulling PWDN low begins
power-down sequence, and EAPD goes low ~30ms later.
2.0 II2C BUS SPECIFICATION
The STA308 supports the I2C protocol. This protocol defines any device that sends data on to the bus as a
transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known
as the master and the other as the slave. The master always starts the transfer and provides the serial clock
for synchronization. The STA308 is always a slave device in all of its communications.
STA308
2.1 COMMUNICATION PROTOCOL
2.1.1 Data Transition or change
Data changes on the SDA line must only occur when the SCL clock is low. SDA transition while the clock is
high is used to identify a START or STOP condition.
2.1.2 Start Condition
START is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is stable
in the high state. A START condition must precede any command for data transfer.
2.1.3 Stop Condition
STOP is identified by low to high transition of the data bus SDA signal while the clock signal SCL is stable in the
high state. A STOP condition terminates communication between STA308 and the bus master.
2.1.4 Data Input
During the data input the STA308 samples the SDA signal on the rising edge of clock SCL. For correct device
operation the SDA signal must be stable during the rising edge of the clock and the data can change only when
the SCL line is low.
2.2 DEVICE ADDRESSING
To start communication between the master and the STA308, the master must initiate with a start condition.
Following this, the master sends onto the SDA line 8-bits (MSB first) corresponding to the device select address
and read or write mode.
The 7 most significant bits are the device address identifiers, corresponding to the I2C bus definition. In the
STA308 the I2C interface has two device addresses depending on the SA pin configuration, 0x30 or 0011000x
when SA = 0, and 0x32 or 0011001x when SA = 1.
The 8th bit (LSB) identifies read or write operation RW, this bit is set to 1 in read mode and 0 for write mode.
After a START condition the STA308 identifies on the bus the device address and if a match is found, it acknowl-
edges the identification on SDA bus during the 9th bit time. The byte following the device identification byte is
the internal space address.
2.3 WRITE OPERATION
Following the START condition the master sends a device select code with the RW bit set to 0. The STA308
acknowledges this and the writes for the byte of internal address. After receiving the internal byte address the
STA308 again responds with an acknowledgement.
2.3.1 Byte Write
In the byte write mode the master sends one data byte, this is acknowledged by the STA308. The master then
terminates the transfer by generating a STOP condition.
2.3.2 Multi-byte Write
The multi-byte write modes can start from any internal address. The master generating a STOP condition ter-
minates the transfer.
STA308
Read Mode Sequence
Table 1. Register summary
STA308
STA308
3.0 CONFIGURATION REGISTER A (ADDRESS 00H)
3.0.1 Master Clock Select
The STA308 will support sample rates of 32kHz, 44.1kHz, 48Khz, 88.2kHz, 96kHz, 176.4kHz, and 192kHz.
Therefore the internal clock will be: 65.536Mhz for 32kHz 90.3168Mhz for 44.1khz, 88.2kHz, and 176.4kHz 98.304Mhz for 48kHz, 96kHz, and 192kHz
The external clock frequency provided to the XTI pin must be a multiple of the input sample frequency(fs). The
relationship between the input clock and the input sample rate is determined by both the MCSx and the IRx (In-
put Rate) register bits. The MCSx bits determine the PLL factor generating the internal clock and the IRx bits
determine the oversampling ratio used internally.
3.0.2 Interpolation Ratio Select
The STA308 has variable interpolation (oversampling) settings such that internal processing and DDX output
rates remain consistent. The first processing block interpolates by either 4 times, 2 times, or 1 time (pass-
through). The IR bits determine the oversampling ratio of this interpolation.
Table 2. IR bit settings as a function of Input Sample Rate.
STA308
3.0.3 Bass Management Enable
Channel 6 of the STA308 features a bass management mode that enables redirection of information in all other
channels to this channel and which can then be filtered appropriately using the EQ(Biquad) section. Setting the
BME bit selects the output of the scale and mix block for channel 6 instead of the output of the channel mapping
block. The settings for the scale and mix block are provided by the CxBMS registers
3.0.4 DDX Headphone Output Enable
Channels 7 and 8 of the STA308 have the option to be processed for headphones. The headphone output can
then be driven using an appropriate output device. This signal is a fully differential 3-wire drive called DDX
Headphone
3.0.5 Max Power Correction
Setting the MPC bit turns on special processing that corrects the DDX power device at high power. This mode
should lower the THD+N of a full DDX system at maximum power output and slightly below. This mode will only
be operational in OM= 00 or 10.
3.1 Configuration Register B (address 01h)
3.1.1 DSP Bypass
Setting the DSPB bit bypasses the biquad and bass/treble functionality of the STA308.
3.1.2 Zero-Detect Mute Enable
Setting the ZDE bit enables the zero-detect automatic mute.
The zero-detect circuit looks at the input data to each processing channel after the channel mapping block. If
any channel receives 2048 consecutive zero value samples (regardless of fs) then that individual channel is
muted if this function is enabled.
STA308
Serial Audio Input Interface Format
The STA308 features a configurable digital serial audio interface. The settings of the SAIx bits determine how
the input to this interface is interpreted. Six formats are accepted.
Table 3. Interface format as a function of SAI bits.
Figure 2. Serial Audio Signals
STA308
3.1.3 Serial Audio Input Interface First Bit
3.1.4 Zero-Crossing Volume Enable
The ZCE bit enables zero-crossing volume adjustments. When volume is adjusted on digital zero-crossings,
"zipper noise" is eliminated
3.1.5 Dynamic Range Compression/Anti-Clipping Bit
Both limiters can be used in one of two ways, anti-clipping or dynamic range compression. When used in anti-
clipping mode the limiter threshold values are constant and dependent on the gain/attenuation settings applied
to the input signal. In dynamic range compression mode the limiter threshold values vary with the volume set-
tings allowing for limiting to occur independently of the gain/attenuation but dependent on the input signal
3.2 Configuration Register C (address 02h)
3.2.1 DDX Power Output Mode
The DDX Power Output Mode selects how the DDX output timing is configured. Different power devices use
different output modes. The DDX recommended use is OM = 00. The variable mode uses the OMVx bits for
adjustment
STA308
3.2.2 DDX Compensating Pulse Size Register
3.2.3 High-Pass Filter Bypass
The STA308 features an internal digital high-pass filter for the purpose of AC coupling. The purpose of this filter
is to prevent DC signals from passing through a DDX amplifier. DC signals can cause speaker damage
3.3 Configuration Register D (address 03h)
3.3.1 Binary Output Enable Registers
Each two-channel pair of outputs can be set to output a binary PWM stream. In this mode, output A
of a channel will be considered the positive output and output B is negative inverse. For example, setting C34BO
= 1 sets channels 3&4 to Binary Output (PWM) Mode.
3.3.2 Clock Output Select
STA308
The Clock Output Select register selects the frequency of the clock output pin relative to the PLL clock output.
The PLL clock runs at 2048fs for 32, 44.1, and 48kHz, at 1024fs for 88.2kHz and 96 kHz, and at 512fs for
176.4kHz and 192kHz.
3.3.3 Post-Scale Link
For multi-channel applications, the post-scale values can be linked to the value of channel 1 for ease of use and
update the values faster.
3.3.4 Biquad Coefficient Link
For ease of use, all channels can use the biquad coefficients loaded into the Channel 1 Coefficient RAM space
by setting the BQL bit to 1. Then any EQ updates would only have to be performed once.
3.4 Configuration Register E (address 04h)
The scale and mix functionality can be used to mix adjacent channels instead of for bass management. By set-
ting this bit(BME must be set to 0) odd channels will be mixed with their adjacent even channel and output in
the place of the even channel. The odd channel wills pass-through unscaled. The values used for this function
are the same as for bass management. Since this function occurs post channel mapping a large number of
possibilities are present for two channel mixing. Up to four mixed channels can be obtained.
When VOLEN set to 1, volume operation is normal. When set to 0, volume operation is bypassed and the vol-
ume stages are all set to pass-through. This also eliminates the digital volume offset of ~-0.6dB that is used to
STA308
map full-scale digital input to full DDX modulation output.
By setting this bit to one deemphasis will implemented on all channels. When this is used it takes the place of
biquad #1 in each channel and any coefficients using biquad #1 will be ignored. DSPB(DSP Bypass) bit must
be set to 0 for Deemphasis to function.
The STA308 features a configurable digital serial audio interface. The settings of the SAIx bits determine how
the output to this interface is interpreted. Six formats are accepted.
Table 4. Interface format as a function of SAO bits.
3.5 Configuration Register F (address 05h)

Partno	Mfg	Dc	Qty	Available	Descript
STA308	ST	N/a	40000	avai	MULTICHANNEL DIGITAL AUDIO PROCESSOR WITH DDX