STA2500DTR ,Bluetooth蛺2;2; V2.1 + EDR ("Lisbon") for automotive applicationsfeatures . 195.5 Bluetooth controller V2.1 + EDR (“Lisbon”) . . . . . . . 195.6 Processor and ..
STA301A , NPN Darlington With built-in avalanche diode
STA302 , PNP Darlington General purpose/3-phase motor drive
STA303 , NPN Darlington General purpose/3-phase motor drive
STA304 ,DIGITAL AUDIO PROCESSOR WITH MULTICHANNEL DDX(TM)STA304DIGITAL AUDIO PROCESSOR WITH MULTICHANNEL DDX™PRODUCT PREVIEW■ END TO END DIGITAL AUDIO INTEG ..
STA304A ,3-phase Motor Driver ArraySTA304ADIGITAL AUDIO PROCESSOR WITH MULTICHANNEL DDX™PRODUCT PREVIEW■ STA304AEND TO END DIGITAL AUD ..
STS25NH3LL ,N-CHANNEL 30VSTS25NH3LLN-CHANNEL 30V - 0.0027Ω -25A SO-8STripFET™ III MOSFET FOR DC-DC CONVERSIONPRELIMINARY DAT ..
STS2DNE60 ,NABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V = 0)60 VDS GSV Drain-g ..
STS2DNE60 ,NELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED)OFFSymbol Parameter Test Condi ..
STS2DNF30L ,N-CHANNEL 30VSTS2DNF30LN-CHANNEL 30V - 0.09 Ω - 3A SO-8STripFET™ POWER MOSFETTYPE V R IDSS DS(on) DSTS2DNF30L 30 ..
STS2DNFS30L ,N-CHANNEL 30V 0.09 OHM 3A SO-8 STRIPFET II MOSFET PLUS SCHOTTKY RECTIFIERELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED)OFFSymbol Parameter Test Condi ..
STS2DPF20V ,DUAL P-CHANNEL 20V 0.014 OHM 2A SO-8 2.7V-DRIVE STRIPFET II POWER MOSFETABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V = 0) 20 VDS GSV Drain- ..
STA2500DTR
Bluetooth蛺2;2; V2.1 + EDR ("Lisbon") for automotive applications
A2500DBluetooth™ V2.1 + EDR ("Lisbon") for automotive applications
Features Based on Ericsson technology licensing
baseband core (EBC) Bluetooth™ specification compliance:
V2.1 + EDR (“Lisbon”) Point-to-point, point-to-multipoint (up to 7
slaves) and scatternet capability Support ACL and SCO links Extended SCO (eSCO) links Faster connection HW support for packet types ACL: DM1, DM3, DM5, DH1, DH3, DH5, 2-
DH1, 2-DH3, 2-DH5, 3-DH1, 3-DH3, 3-DH5 SCO: HV1, HV3 and DV eSCO: EV3, EV4, EV5, 2-EV3, 2-EV5, 3-
EV3, 3-EV5 Adaptive frequency hopping (AFH) Channel quality driven data rate (CQDDR) “Lisbon” features Encryption pause/resume (EPR) Extended inquiry response (EIR) Link supervision time out (LSTO) Secure simple pairing Sniff subrating Quality of service (QoS)
Packet boundary flag
Erroneous data delivery Transmit power Power class 2 and power class 1.5 (above
4 dBm) Programmable output power Power class 1 compatible HCI HCI H4 and enhanced H4 transport layer HCI proprietary commands (e.g.
peripherals control) Single HCI command for patch/upgrade
download eSCO over HCI supported Supports pitch-period error concealment (PPEC) Efficient and flexible support for WLAN
coexistence scenarios Low power consumption Ultra low power architecture with 3 different
low-power levels Deep sleep modes, including host-power
saving feature Dual wake-up mechanism: initiated by the
host or by the Bluetooth device Communication interfaces Fast UART up to 4 MHz Flexible SPI interface up to 13 MHz PCM interface Up to 10 additional flexibly programmable
GPIOs External interrupts possible through the
GPIOs
–Fast I2 C interface as master Clock support System clock input (digital or sine wave) at
9.6, 10, 13, 16, 16.8, 19.2, 26, 33.6 or 38.4 MHz Low power clock input at 3.2 kHz, 32 kHz
and 32.768 kHz ARM7TDMI CPU Memory organization On chip RAM, including provision for
patches On chip ROM, preloaded with SW up to
HCI Ciphering support up to 128-bit key Single power supply with internal regulators for
core voltage generation Supports 1.65 V to 2.85 V I/O systems Auto calibration (VCO, filters)
Contents STA2500D
Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Quick reference data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 I/O specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Clock specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Block diagram and electrical schematic . . . . . . . . . . . . . . . . . . . . . . . . 12 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134.1 Pin description and assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 HW configuration of the STA2500D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3 I/O Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185.1 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.3 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.4 Bluetooth controller V1.2 and V2.0 + EDR features . . . . . . . . . . . . . . . . . 19
5.5 Bluetooth controller V2.1 + EDR (“Lisbon”) . . . . . . . . . . . . . . . . . . . . . . . 19
5.6 Processor and memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.7 TX output power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
General specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216.1 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.3 Class 1 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.4 Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.5 System clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.6 Low power clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.7 Clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
STA2500D Contents6.8 Clock request signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.9 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.10 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.10.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.10.2 Some examples for the usage of the low power modes . . . . . . . . . . . . 30
6.10.3 Deep sleep mode entry and wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.11 Patch RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.12 Download of SW parameter file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.13 Bluetooth - WLAN coexistence in collocated scenario . . . . . . . . . . . . . . . 38
6.13.1 Algorithm 1: PTA (packet traffic arbitration) . . . . . . . . . . . . . . . . . . . . . . 38
6.13.2 Algorithm 2: WLAN master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.13.3 Algorithm 3: Bluetooth master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.13.4 Algorithm 4: two-wire mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.13.5 Algorithm 5: Alternating wireless medium access (AWMA) . . . . . . . . . . 40
Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417.1 The UART interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.2 The SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.3 The PCM interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.4 The JT AG interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.5 Alternate I/O functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.6 The I2 C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
HCI transport layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488.1 H4 UART transport layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8.2 Enhanced H4 SPI transport layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8.3 H4 SPI transport layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8.4 eSCO over HCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Acronyms and abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
List of tables STA2500D
List of tables
Table 1. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. DC input specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. DC output specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5. System clock supported frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. System clock overall specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 7. System clock, sine wave specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 8. System clock, digital clock DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 9. System clock, digital clock AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 10. Low power clock specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 11. Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 12. The STA2500D pin list (functional and supply). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 13. Configuration programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 14. I/O supply split diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 15. Mbps receiver parameters - GFSK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 16. Mbps receiver parameters - /4-DQPSK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 17. Mbps receiver parameters - 8-DPSK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 18. Transmitter parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 19. Output power: class 1 control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 20. Output power: class 1 device pin configuration (depending on SW parameter download). 26
Table 21. Output power: class 1 device pin configuration (depending on SW parameter download). 26
Table 22. Use of the BT_CLK_REQ_IN and BT_CLK_REQ_OUT signals in different modes. . . . . . 28
Table 23. Low power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 24. WLAN HW signal assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 25. SPI timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 26. PCM interface parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 27. PCM interface timing (at PCM_CLK = 2048 kHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 28. Examples of BT_GPIO pin programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 29. Package markings legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 30. References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 31. Acronyms and abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 32. Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 33. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
STA2500D List of figures
List of figures
Figure 1. Block diagram and electrical schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 2. Pinout (bottom view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 3. Active high clock request input and output combined with UART or SPI . . . . . . . . . . . . . . 28
Figure 4. Active low clock request input and output combined with UART . . . . . . . . . . . . . . . . . . . . 28
Figure 5. Active low clock request input and output combined with SPI . . . . . . . . . . . . . . . . . . . . . . 28
Figure 6. Deep sleep mode entry and wake-up through H4 UART . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 7. Entering deep sleep mode through enhanced H4 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 8. Wake-up by the host through enhanced H4 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 9. Wake-up by the Bluetooth controller with data transmission to the host, through enhanced H4
SPI 34
Figure 10. Deep sleep mode entry and wake-up through H4 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 11. Entering deep sleep mode, pending data on UART interface, through UART with handshake
Figure 12. Wakeup by host through UART with handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 13. PTA diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 14. WLAN master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 15. Bluetooth master. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 16. SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 17. SPI data transfer timing for data length of 8 bits and lsb first, full duplex . . . . . . . . . . . . . . 42
Figure 18. SPI setup and hold timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 19. PCM (A-law, µ-law) standard mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 20. Linear mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 21. Multislot operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 22. PCM interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 23. UART transport layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 24. LFBGA48 (6x6x1.4mm) mechanical data and package dimensions . . . . . . . . . . . . . . . . . 50
Figure 25. Package markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Description STA2500D
1 Description
The ST A2500D is a single chip Bluetooth solution that is fully optimized for automotive
applications such as telematics, navigation and portable navigation. Power consumption
levels are targeted at battery powered devices and single chip solution brings cost
advantages. Manufacturers can easily and quickly integrate the STA2500D on their product
to enable a rapid time to market. A2500D supports the Bluetooth specification V2.1 + EDR (“Lisbon“) and is optimized in
terms of RF performance and cost.
The ST A2500D is a ROM-based solution targeted at applications requiring integration up to
HCI level. Patch RAM is available, enabling multiple patches/upgrades and fast time to
volume. The ST A2500D’s main interfaces are UART or SPI for HCI transport, PCM for voice
and GPIOs for control purposes.
The radio has been designed specifically for single chip requirements, for low power
consumption and minimum BOM count.
STA2500D Quick reference data
2 Quick reference data
BT_VIO_x means BT_VIO_A, BT_VIO_B.
BT_HVx means BT_HVA, BT_HVD.
(See also Table 12.)
2.1 Absolute maximum ratings
The absolute maximum rating (AMR) corresponds to the maximum value that can be
applied without leading to instantaneous or very short-term unrecoverable hard failure
(destructive breakdown).
2.2 Operating ranges
Operating ranges define the limits for functional operation and parametric characteristics of
the device. Functionality outside these limits is not implied.
Table 1. Absolute maximum ratings
Table 2. Operating ranges
Quick reference data STA2500D
2.3 I/O specifications
The I/Os comply with the EIA/JEDEC standard JESD8-B.
2.4 Clock specifications
The ST A2500D supports, on the BT_REF_CLK_IN pin, the system clock both as a sine
wave clock and as a digital clock. For configuration, see Table 12: pin BT_VDD_CLD (E6).
Table 3. DC input specification Except for the system clock.
Table 4. DC output specification X is the source/sink current under worst-case conditions according to the drive capabilities (see Section3)
Table 5. System clock supported frequencies
Table 6. System clock overall specifications
STA2500D Quick reference data
Table 7. System clock, sine wave specifications Equivalent to max 10 ps time jitter (rms).
Table 8. System clock, digital clock DC specifications
Table 9. System clock, digital clock AC specifications Equivalent to max 15 ps time jitter (rms).
Table 10. Low power clock specifications
The low power clock pin is powered by connecting BT_VIO_B to the wanted supply.
Quick reference data STA2500D
2.5 Current consumption
Tamb = 25°C, 13 MHz digital clock, 7 dBm output power for BR packets, 3 dBm output power
for EDR packets.
The rise and fall time are not the most important parameters for the low power clock input due to the Schmitt trigger logic. It
is more important that the noise on the Low power clock line remains substantially below the hysteresis in amplitude. The total jitter is defined as the error that can appear on the actual frequency between two clock edges compared to the
perfect frequency. Due to this, the total jitter value must contain the jitter itself and the error due to the accuracy on the
clock frequency. The lower the accuracy, the smaller the jitter is allowed to be.
Table 10. Low power clock specifications (continued)
The low power clock pin is powered by connecting BT_VIO_B to the wanted supply.
Table 11. Current consumption(1)
STA2500D Quick reference data The power consumption (except for power safe modes i.e. complete power down and deep sleep mode)
will rise (with approx. 200 µA) if an analog system clock is used instead of a digital clock. In functional sleep mode, the baseband clock is still running.
Table 11. Current consumption(1) (continued)
Block diagram and electrical schematic STA2500D Block diagram and electrical schematic
STA2500D Pinout
4 Pinout
4.1 Pin description and assignment
Table 12 shows the pin list of the STA2500D.
In columns “Reset” and “Default after reset”, the “PD/PU” shows the pads implementing an
internal pull-down/up.
The column “Reset” shows the state of the pins during hardware reset; the column “Default
after reset” shows the state of the pins after the hardware reset state is left, but before any
software parameter download.
The column “Type” describes the pin directions: I for Input (All inputs have a Schmitt trigger function.) O for Output I/O for Input/Output O/t for tri-state output
Pinout STA2500D
For the output pin the default drive capability is 2 mA, except for pin K3 (BT_GPIO_11) and
pin L3 (BT_GPIO_8) where it is 8 mA such that when used for Class 1, these 2 pins can be
used for a switch control in a cheaper way.
Table 12. The STA2500D pin list (functional and supply)
STA2500D Pinout
Table 12. The STA2500D pin list (functional and supply) (continued)
Pinout STA2500D
4.2 HW configuration of the STA2500D
By means of the three configuration pins, one can select the Host interface (UART or SPI)
and clock request signal polarity to be used at startup.
The available combinations of Host interface and protocol are illustrated in Table 13 (where
‘1’ = BT_VIO_A and ‘0’ = BT_VSSDIG). Additionally, the polarity of the BT_CLK_REQ
signals can be programmed through the same pins. The polarity of the BT_CLK_REQ_IN
and BT_CLK_REQ_OUT signals is further described in Section 6.8. Pin behaviour during HW reset (BT_RESETN low). Pin behaviour immediately after HW reset and internal chip initialization, but before SW parameter download. See also pin BT_VDD_CLD in Table12. Reconfigurable I/O pin.The functionality of these I/Os can be configured through software parameter download (see
Section 7.5). Should be strapped to BT_VSSDIG if not used. JTAG mode. Described in Section 4.3. To be strapped to BT_VSSANA. Pin is ST - reserved for test function and it must be soldered to an isolated pad (not connected to anything, just floating).
Table 12. The STA2500D pin list (functional and supply) (continued)
STA2500D Pinout
4.3 I/O Supply
The device STA2500D has two different I/O supplies: BT_VIO_A and BT_VIO_B.
The two different pins may be potentially connected to separate dedicated voltage supplies
in order to harmonize the digital levels to the platform.
They are linked to different interfaces as described in Table 14.
Table 13. Configuration programming In order to get other SPI modes, the Host must send a specific configuration at start-up in addition of these configuration
pins.
Table 14. I/O supply split diagram
Functional description STA2500D
5 Functional description
5.1 Transmitter
The transmitter uses the serial transmit data from the Bluetooth Controller. The transmitter
modulator converts this data into GFSK, /4-DQPSK or 8-DPSK modulated I and Q digital
signals for respectively 1, 2 and 3 Mbps transmission speed. These signals are then
converted to analog signals that are low pass filtered before up-conversion. The carrier
frequency drift is limited by a closed loop PLL.
5.2 Receiver
The ST A2500D implements a low-IF receiver for Bluetooth modulated input signals. The
radio signal is taken from a balanced RF input and amplified by an LNA. The mixers are
driven by two quadrature LO signals, which are locally generated from a VCO signal running
at twice the frequency. The I and Q mixer output signals are band pass filtered by a poly-
phase filter for channel filtering and image rejection. The output of the band pass filter is
amplified by a VGA to the optimal input range for the A/D converter. Further channel filtering
is done in the digital part. The digital part demodulates the GFSK, /4-DQPSK or 8-DPSK
coded bit stream by evaluating the phase information. RSSI data is extracted. Overall
automatic gain amplification in the receive path is controlled digitally. The RC time constants
for the analog filters are automatically calibrated on chip.
5.3 PLL
The on chip VCO is part of a PLL. The tank resonator circuitry for the VCO is completely
integrated without need of external components. Variations in the VCO centre frequency are
calibrated out automatically.
STA2500D Functional description
5.4 Bluetooth controller V1.2 and V2.0 + EDR features
The Bluetooth controller is backward compatible with the Bluetooth specification V1.2 [] and
V2.0 + EDR []. Here below is a list with the main features of those specifications: Adaptive Frequency Hopping (AFH): hopping kernel, channel assessment as Master
and as Slave Fast Connection: Interlaced scan for Page and Inquiry scan, answer FHS at first
reception, RSSI used to limit range Extended SCO (eSCO) links: supports EV3, EV4 and EV5 packets Channel Quality Driven Data Rate change (CQDDR) QoS Flush Synchronization: BT clocks are available at HCI level for synchronization of parallel
applications on different Slaves L2CAP Flow & Error control LMP SCO handling 2 Mbps packet types ACL: 2-DH1, 2-DH3, 2-DH5 eSCO: 2-EV3, 2-EV5 3 Mbps packet types ACL: 3-DH1, 3-DH3, 3-DH5 eSCO: 3-EV3, 3-EV5
5.5 Bluetooth controller V2.1 + EDR (“Lisbon”) Encryption Pause/Resume (EPR) Extended Inquiry Response (EIR) Link Supervision Time Out (LSTO) Secure Simple Pairing Sniff Subrating Quality of Service (Qos) Packet Boundary Flag Erroneous Data Delivery
5.6 Processor and memory ARM7TDMI On chip RAM, including provision for patches On chip ROM, preloaded with SW up to HCI
Functional description STA2500D
5.7 TX output power control
The ST A2500D supports output power control with advanced features: Basic feature: With the standard TX power control algorithm enabled, the STA2500D will adapt
its output power when a remote BT device supports the RSSI feature; this allows
the remote device to measure the link strength and to request the ST A2500D to
decrease/increase its output power. In case the remote device does not support
the RSSI feature, the STA2500D will use its ‘default’ output power level. Advanced features, available via specific HCI commands: Enhanced power control feature: allows the STA2500D to decrease autonomously
its output power until the remote BT device, supporting the RSSI feature, requests
to increase the output power.
STA2500D General specification
6 General specification
All the values are provided according to the Bluetooth specification V2.1 + EDR (“Lisbon”)
unless otherwise specified. The below values are preliminary and will be updated in the next
version of this datasheet.
6.1 Receiver
All specifications below are given at device pin level and with the conditions as specified.
Parameters are given for each of the 3 modulation types supported.
Typical is defined at Tamb = 25 °C, BT_HV = 2.75 V. Minimum and Maximum are worst cases
over corner lots and temperature. Parameters are given at device pin, except for receiver
interferers measured at antenna with a filter having a typical attenuation of 2.3 dB.
Table 15. Mbps receiver parameters - GFSK
General specification STA2500D
Typical is defined at Tamb = 25 °C, BT_HV = 2.75 V. Minimum and Maximum are worst cases
over corner lots and temperature. Parameters are given at device pin, except for receiver
interferers measured at antenna with a filter having a typical attenuation of 2.3 dB.
Table 15. Mbps receiver parameters - GFSK (continued)
Table 16. Mbps receiver parameters - /4-DQPSK
STA2500D General specification
Typical is defined at Tamb = 25 °C, BT_HV = 2.75 V. Minimum and Maximum are worst cases
over corner lots and temperature. Parameters are given at device pin, except for receiver
interferers measured at antenna with a filter having a typical attenuation of 2.3 dB.
Table 16. Mbps receiver parameters - /4-DQPSK (continued)
Table 17. Mbps receiver parameters - 8-DPSK
General specification STA2500D
6.2 Transmitter
Unless otherwise stated, typical is defined at Tamb = 25 °C, BT_HV = 2.75 V. Minimum and
Maximum are worst cases over corner lots and temperature. Parameters are given at device
pin, except for in-band spurious measured at antenna.
Table 18. Transmitter parameters
STA2500D General specification Lower transmit power (i.e. Class 2) can be obtained by programming the radio init power table via software parameter
download or an HCI command. Power of GFSK part. Relative power of EDR part compared to the GFSK part. At antenna with maximum output power, filter attenuation of 2.3 dB. Phase noise will add maximum [-10 kHz;10 kHz] for worst case clock 270 mVpp at 13 MHz. Worst case clock 270 mVpp at 13 MHz. Measurement according to EDR RF test spec V2.0.E.3 []. With maximum output power (BR or EDR). Measured on reference design STLC2555_rev1.1 following eBOM and layout recommendations. Measurement bandwidth.
10. Transmitting DH5 packets.
Table 18. Transmitter parameters (continued)
General specification STA2500D
6.3 Class 1 operation
The ST A2500D supports operation at Class 1 output power levels with the use of an
external PA. The operation of the external PA and antenna switch are controlled by the
following signals:
If Class 1 functionality is enabled through SW parameter download, then these 6 control
signals are available on the pins as indicated in Table 20 and Table 21.
Configuration 2 allows to deploy the STA2500D in Class 1 mode, still maintaining the
necessary control signals to coexist and cooperate with a WLAN transceiver. The
handshake between the STA2500D and a WLAN device happens in this case through other
BT_GPIO pins.
6.4 Power-up
The BT_RESETN pin should be active while powering up BT_VDD_HV and should stay
active at least two cycles of the low power clock (BT_LP_CLK) after power-up is completed.
The time between the STA2500D making BT_CLK_REQ_OUT_x active and the platform
providing a stable clock should maximally be 15 ms.
Table 19. Output power: class 1 control signals
Table 20. Output power: class 1 device pin configuration (depending on SW
parameter download)
Table 21. Output power: class 1 device pin configuration (depending on SW
parameter download)
STA2500D General specification
6.5 System clock
The ST A2500D works with a sine wave or digital clock provided on the BT_REF_CLK_IN
pin. Detailed specifications are found in Section 2.4.
6.6 Low power clock
The low power clock is used by the Bluetooth Controller as reference clock during the low
power modes. It requires an accuracy of +250 ppm. The STA2500D requires a digital clock
to be provided on the BT_LP_CLK pin, with frequencies of 3.2 kHz, 32 kHz and 32.768 kHz.
After power-up, the low power clock must be available before the reset is released. It must
remain active all the time until the STA2500D is powered off.
6.7 Clock detection
An integrated automatic detection algorithm detects the system and low power clock
frequencies after a hardware reset. The steps in the clock detection routine are: Identification of the system clock frequency (9.6 MHz, 10 MHz, 13 MHz, 16 MHz,
16.8MHz, 19.2 MHz, 26 MHz, 33.6 MHz or 38.4 MHz) Identification of the low power clock (3.2 kHz, 32.768 kHz or 32 kHz).
6.8 Clock request signals
To allow minimum power consumption, a clock request feature is available so that the
system clock (BT_REF_CLK_IN) can be stopped when not needed by the Bluetooth
system. The clock request signal can be active high or active low, and the ST A2500D
supports internal propagation of clock request signal coming from another device in the
system.
Different configurations as described below are supported immediately after reset and in all
Bluetooth operation modes, provided that BT_VIO_A is available.
The clock request functionality is based on four different signals: BT_CLK_REQ_OUT_1,
BT_CLK_REQ_OUT_2, BT_CLK_REQ_IN_1, BT_CLK_REQ_IN_2, with the following
function: BT_CLK_REQ_OUT_1: active low or high clock request, depending on HW
configuration pins (T able ). Support for either push-pull or open drain output. BT_CLK_REQ_OUT_2: active low clock request, only used in combination with SPI
mode. Support for either push-pull or open drain output. BT_CLK_REQ_IN_1: active high clock request input from an other device, depending
on HW configuration pin. BT_CLK_REQ_IN_2: active low clock request input from an other device.
The following modes are supported: Active high clock request input and output combined with UART or SPI:
General specification STA2500D
The pins which are “not used” are available for alternate functions as described in
Section 7.5.
Table 22. Use of the BT_CLK_REQ_IN and BT_CLK_REQ_OUT signals in different modes BT_CLK_REQ_IN_1 and BT_CLK_REQ_IN_2 are used in the configuration logic, UNLESS one or both I/Os re-
programmed as alternate function(s) via the Parameter File.
STA2500D General specification
6.9 Interrupts
The user can program the BT_GPIOs as external interrupt sources.
6.10 Low power modes
6.10.1 Overview
To save power, three low power modes are supported as described in Table 23.
Depending of the Bluetooth and of the Host's activity, the STA2500D decides to use Sleep
mode or Deep Sleep mode. Note however that the Deep Sleep mode must first be activated
via SW parameter download or an HCI command prior to any possibility to use it as the
default configuration is only Sleep mode. Complete Power Down is entered only after an
explicit command from the Host.
Table 23. Low power modes
