STA120D13TR ,DIGITAL AUDIO INTERFACE RECEIVERABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV , V Power Supply Voltage 4 VD+ A+V Input Volta ..
STA120DJ ,Digital audio interface receiverABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV , V Power Supply Voltage 4 VD+ A+V Input Volta ..
STA203A , 1.2A 3 circuits Triac Array
STA203A , 1.2A 3 circuits Triac Array
STA2051 ,32-BIT SINGLE CHIP BASEBAND CONTROLLER FOR GPS AND TELEMATIC APPLICATIONSFEATURESFigure 1. Packages■ ARM7TDMI 16/32 bit RISC CPU based host microcontroller.■ Complete Embed ..
STA2500DTR ,Bluetooth蛺2;2; V2.1 + EDR ("Lisbon") for automotive applicationsfeatures . 195.5 Bluetooth controller V2.1 + EDR (“Lisbon”) . . . . . . . 195.6 Processor and ..
STS1DNC45 ,DUAL N-CHANNEL 450VABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V = 0) 450 VDS GSV Drain ..
STS1HNK60 ,N-CHANNEL 600VSTS1HNK60N-CHANNEL 600V - 8Ω -0.3A SO-8SuperMESH™Power MOSFETTYPE V R I PwDSS DS(on) DSTS1HNK60 600 ..
STS1NC60 ,N-CHANNEL 600V 12 OHM 0.3A SO-8 POWERMESH II MOSFETABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V = 0)DS GS 600 VV Drain ..
STS1NK60Z ,N-CHANNEL 600V 13 OHM 0.25A SO-8 ZENER-PROTECTED SUPERMESH POWER MOSFETABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V =0)600 VDS GSV Drain-g ..
STS2300 , N-Channel E nhancement Mode Field EffectTransistor
STS2300 , N-Channel E nhancement Mode Field EffectTransistor
STA120D13TR
DIGITAL AUDIO INTERFACE RECEIVER
1/15
STA120December 2002 MONOLITHIC CMOS RECEIVER 3.3V SUPPLY VOLTAGE LOW-JITTER, ON-CHIP CLOCK RECOVERY
256xFs OUTPUT CLOCK PROVIDED SUPPORTS: AES/EBU, IEC 958, S/PDIF, &
EIAJ CP-340/1201 PROFESSIONAL AND
CONSUMER FORMATS EXTENSIVE ERROR REPORTING REPEAT
LAST SAMPLE ON ERROR OPTION
DESCRIPTIONThe STA120 is a monolithic CMOS device that re-
ceives and decodes audio data according to the
AES/EBU, IEC 958, S/PDIF, & EIAJ CP-340/1201
interface standards.
The STA120 recovers the clock and synchroniza-
tion signals and de-multiplexes the audio and dig-
ital data. Differential or single ended inputs can be
decoded.
The STA120 de-multiplexes the channel, user and
validity data directly to serial output pins with ded-
icated output pins for the most important channel
status bits.
DIGITAL AUDIO INTERFACE RECEIVER
BLOCK DIAGRAM
STA120 2/15
ABSOLUTE MAXIMUM RATINGS
PIN CONNECTIONS (Top view)
PINS DESCRIPTION
3/15
STA120
PINS DESCRIPTION (continued)
STA120 4/15
DIGITAL CHARACTERISTICS (Tamb = 25°C; VD+, VA+ = 3.3V ±10%)Note 1: FS is defined as the incoming audio sample frequency per channel.
SWITCHING CHARACTERISTICS - SERIAL PORTS (Tamb = 25°C; VD+, VA+ = 3.3V ±10%)Note 2: The output word rate, OWR, refers to the frequency at which an audio sample is output from the part. (A stereo pair is two audio
samples). Therefore, in Master mode, there are always 32 SCK periods in one audio sample. In Slave mode 32 SCK periods must
be provided in most serial port formats.
PINS DESCRIPTION (continued)
5/15
STA120
Figure 1. Circuit Diagram
GENERAL DESCRIPTIONThe STA120 is a monolithic CMOS circuit that receives and decodes audio and digital data according to
the AES/EBU, IEC 958, S/PDIF, and EIAJ CP-340/1201 interface standards.
It contains a RS422 line receiver and Phase-Locked Loops (PLL) that recovers the clock and synchroni-
zation signals and de-multiplexes the audio and digital data. The STA120 de-multiplexes the channel sta-
tus, user and validity information directly to serial output pins with dedicated pins for the most important
channel status bits.
Line ReceiverThe line receiver can decode differential as well as single ended inputs. The receiver consits of a differ-
ential input Schmitt trigger with 50mV of hysteresis. The hysteresis prevents noisy signals from corrupting
the phase detector. Appendix A contains more information on how to configure the line receivers for dif-
ferential and single ended signals.
Clocks and Jitter AttenuationThe primary function of this chip is to recover audio data and low jitter clocks from a digital audio trans-
mission line. The clocks that can be generated are MCK (256xFS), SCK (64xFS), and FSYNC (FS or
2xFS). MCK is the output of the voltage controlled oscillator which is a component of the PLL. The PLL
consists of phase and frequency detectors, a second-order loop filter, and a voltage controlled oscillator.
All components of the PLL are on chip with the exception of a resistor and capacitors used in the loop filter.
This filter is connected between the FILT pin and AGND. The closed-loop transfer function, which speci-
fies the PLL's jitter attenuation characteristics, is shown in Figure 2.
The loop will begin to attenuate jitter at approximately 25kHz with another pole at 80kHz and will have
50dB of attenuation by 1MHz. Since most data jitter introduced by the transmission line is high in frequen-
cy, it will be strongly attenuated.
Multiple frequency detectors are used to minimize the time it takes the PLL to lock to the incoming data
stream and to prevent false lock conditions. When the PLL is not locked to the incoming data stream, the
STA120 6/15
frequency detectors pull the VCO frequency within
the lock range of the PLL. When no digital audio
data is present, the VCO frequency is pulled to its
minimum value.
Figure 2. Jitter Attenuator Characteristics.As a master, SCK is always MCK divided by four,
producing a frequency of 64 x FS. In the STA120,
FSYNC is always generated from the incoming
data stream. When FSYNC is generated from the
data its edges are extracted at times when in-
tersymbol interference is at a minimum. This pro-
vides a sample frequency clock that is as
spectrally pure as the digital audio source clock for
moderate length transmission lines.
STA120 DESCRIPTIONThe STA120 does not need a microprocessor to
handle the non-audio data (although a micro may
be used with the C and U serial ports). Instead,
dedicated pins are available for the most important
channel status bits. The STA120 is a monolithic
CMOS circuits that receives and decodes digital
audio data which was encoded according to the
digital audio interface standards. It contains a
clock and data recovery utilizing an on-chip phase-
locked loop. The output data is output through a
configurable serial port that supports 14 formats.
The channel status and user data have their own
serial pins and the validity flag is OR'ed with the
ERF flag to provide a single pin, VERF, indicating
that the audio output may not be valid. This pin
may be used by interpolation filters that provide er-
ror correction.
Audio Serial PortThe audio serial port is used primarily to output au-
dio data and consists of three pins: SCK, FSYNC
and SDATA. These pins are configured via four
control pins: M0, M1,M2,and M3.M3 selects be-
tween eight normal serial formats (M3 = 0), and six
special formats (M3 = 1).
Normal Modes (M3 = 0)When M3 is low, the normal serial port formats
shown in Figure 3 are selected using M2, M1 and
M0. These formats are also listed in Table 1
wherein the first word part the format number (Out-
In) indicates whether FSYNC and SCK are outputs
from the STA120 or are inputs.
The next word (L/R-WSYNC) indicates whether
FSYNC indicates the particular channel or just de-
lineates each word. If an error occurs (ERF=1)
while using one of these formats, the previous val-
id audio data for that channel will be output.
If the STA120 is not locked, the last sample is re-
peated at the output. In some modes FSYNC and
SCK are outputs and in others they are inputs. In
Table 3, LSBJ is short for LSB justified where the
LSB is justified to the end of the audio frame and
the MSB varies with word length. As outputs the
STA120 generates 32 SCK periods per audio
sample (64 per stereo sample) and, as inputs, 32
SCK periods must be provided per audio sample.
When FSYNC and SCK are inputs, one stereo
sample is double buffered. For those modes which
output 24 bits of audio data, the auxiliary bits will
be included. If the auxiliary bits are not used for
audio data, they must be masked off.
7/15
STA120
Table 1. Normal Audio Port Modes (M3 = 0)
Special Modes (M3 = 1)When M3 is high, the special audio modes described in Table 2 are selected via M2, M1, and M0. In for-
mats 8, 9, and 10, SCK, FSYNC, and SDATA are the same as in formats 0, 1, and 2 respectively; however,
the recovered data is output as is even if ERF is high, indicating an error. (In modes 0-2 the previous valid
sample is output).
When out of lock invalid data are sent to the output and the ERF pin goes high.
Format 11 is similar to format 0 except that SCK is an input and FSYNC is an output.
In this mode FSYNC and SDATA are synchronized to the incoming SCK, This mode may be useful when
writing data to storage.
Table 2. Special Audio Port Modes (M3 = 1)Format 12 is similar to format 7 except that SDATA is the entire data word received from the transmission
line including the C, U, V, and P bits, with zeros in place of the preamble. In format 13 SDATA contains
the entire biphase encoded data from the transmission line including the preamble, and SCK is twice the
normal frequency.
The normal two frame delay of data from input to output is reduced to only a few bit periods in formats 12
and 13. However, the C, U, V bits and error codes follow their normal pathways and therefore follow the
output data by nearly two frames. Figure 4.... illustrates formats 12 and 13. Format 14 is reserved and not
presently used, and format 15 causes the STA120 to go into a reset state. While in reset all outputs will
be inactive except MCK. The STA120 incorporates a Power-on Reset to avoid a Reset at power-up.
C, U, VERF, ERF, and CBL Serial OutputsThe C and U bits and CBL are output one SCK period prior to the active edge of FSYNC in all serial port
formats except 2, 3 and 10 (I2 S modes). The active edge of FSYNC may be used to latch C, U, and CBL
externally. In formats 2, 3 and 10, the C and U bits and CBL are updated with the active edge of FSYNC.
The validity + error flag (VERF) and the error flag (ERF) are always updated at the active edge of FSYNC.
STA120 8/15
This timing is illustrated in Figure 5.
The C output contains the channel status bits with CBL rising indicating the start of a new channel status
block. CBL is high for the first four bytes of channel status (32 frames or 64 samples) and low for the last
20 bytes of channel status (160 frames or 320 samples).
The U output contains the User Channel data. The V bit is OR'ed with the ERF flag and output on the
VERF pin. This indicates that the audio sample may be in error and can be used by interpolation filters to
interpolate through the error.
ERF being high indicates a serious error occurred on the transmission line. There are three errors that
cause ERF to go high: a parity error or biphase coding violation during that sample, or an out of lock PLL
receiver. Timing for the above pins is illustrated in Figure 5.
Multifunction PinsThere are seven multifunction pins which contain either error and received frequency information, or chan-
nel status information, selectable by SEL.
Figure 3. Audio Serial Port Formats
