STA015T ,MPEG 2.5 LAYER III AUDIO DECODER WITH ADPCM CAPABILITYAPPLICATIONSEASY PROGRAMMABLE GPSO INTERFACEFOR ENCODED DATA UP TO 5Mbit/sPC SOUND CARDS(TQFP44 & L ..
STA016A ,MPEG 2.5 LAYER III AUDIO DECODER SUPPORTING CD-ROM CAPABILITYfeatures of the device and allowing the use of only one D/A converter with no external analog switc ..
STA016A13TR ,MPEG 2.5 LAYER III AUDIO DECODER SUPPORTING CD-ROM CAPABILITYfeatures specified for Layer III in ISO/IEC13818-3.2 (MPEG 2 Audio) Table 1. Order Codes– Lower sam ..
STA016T ,MPEG 2.5 LAYER III AUDIO DECODER SUPPORTING CD-ROM CAPABILITY & ADPCMfeatures of the device and allowing the use of only one D/A converter with no external analog switc ..
STA016T13TR ,MPEG 2.5 LAYER III AUDIO DECODER SUPPORTING CD-ROM CAPABILITY & ADPCMfeatures of the device and allowing the use of only one D/A converter with no external analog switc ..
STA020D ,96KHZ DIGITAL AUDIO INTERFACE TRANSMITTERABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV DC Power Supply 4 VD+V Digital Input Voltage - ..
STS100 , Multifunction Telecommunications Switch
STS10DN3LH5 ,Dual N-channel 30 V, 0.019 Ohm;, 10 A, SO-8 STripFET (TM); V Power MOSFETElectrical characteristics(T = 25 °C unless otherwise specified)CASE Table 4. Static Symbol Paramet ..
STS10N3LH5 ,N-channel 30 V, 0.019 Ohm;, 10 A, SO-8 STripFET(TM); V Power MOSFETElectrical characteristics(T = 25 °C unless otherwise specified)CASE Table 4. Static Symbol Paramet ..
STS10NF30L ,N-CHANNEL 30VSTS10NF30L®N - CHANNEL 30V - 0.011Ω - 10A SO-8STripFET™ POWER MOSFETPRELIMINARY DATATYPE V R IDSS ..
STS10PF30L ,P-CHANNEL 30VABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V = 0) 30 VDS GSV Drain- ..
STS11N3LLH5 , N-channel 30 V, 0.0117 Ω, 11 A, SO-8 STripFET™ V Power MOSFET
STA015-STA015T
MPEG 2.5 LAYER III AUDIO DECODER WITH ADPCM CAPABILITY
SINGLE CHIP MPEG LAYER 3 DECODER
SUPPORTING:
- All features specified for Layer III in ISO/IEC
11172-3 (MPEG 1 Audio)
- All features specified for Layer III in ISO/IEC
13818-3.2 (MPEG 2 Audio)
- Lower sampling frequencies syntax extension,
(not specified by ISO) called MPEG 2.5
DECODES LAYER III STEREO CHANNELS,
DUAL CHANNEL, SINGLE CHANNEL (MONO)
SUPPORTING ALL THE MPEG 1 & 2 SAM-
PLING FREQUENCIES AND THE EXTEN-
SION TO MPEG 2.5:
48, 44.1, 32, 24, 22.05, 16, 12, 11. 025, 8 KHz
ACCEPTS MPEG 2.5 LAYER III ELEMEN-
TARY COMPRESSED BITSTREAM WITH
DATA RATE FROM 8 Kbit/s UP TO 320 Kbit/s
ADPCM CODEC CAPABILITIES:
- sample frequency from 8 kHz to 32 kHz
- sample size from 8 bits to 32 bits
- encoding algorithm: DVI,
ITU-G726 pack (G723-24, G721,G723-40)
- Tone control and fast-forward capability
EASY PROGRAMMABLE GPSO INTERFACE
FOR ENCODED DATA UP TO 5Mbit/s
(TQFP44 & LFBGA 64)
DIGITAL VOLUME
BASS & TREBLE CONTROL
BYPASS MODE FOR EXTERNAL AUDIO
SOURCE
SERIAL BITSTREAM INPUT INTERFACE
EASY PROGRAMMABLE ADC INPUT INTER-
FACE
ANCILLARY DATA EXTRACTION VIA I2C IN-
TERFACE.
SERIAL PCM OUTPUT INTERFACE (I2S
AND OTHER FORMATS)
PLL FOR INTERNAL CLOCK AND FOR OUT-
PUT PCM CLOCK GENERATION
CRC CHECK AND SYNCHRONISATION ER-
ROR DETECTION WITH SOFTWARE INDI-
CATORS2 C CONTROL BUS
LOW POWER 2.4V CMOS TECHNOLOGY
WIDE RANGE OF EXTERNAL CRYSTALS
FREQUENCIES SUPPORTED
APPLICATIONSPC SOUND CARDS
MULTIMEDIA PLAYERS
VOICE RECORDERS
DESCRIPTIONThe STA015 is a fully integrated high flexibility
MPEG Layer III Audio Decoder, capable of de-
coding Layer III compressed elementary streams,
as specified in MPEG 1 and MPEG 2 ISO stand-
ards. The device decodes also elementary streams
compressed by using low sampling rates, as speci-
fied by MPEG 2.5.
STA015 receives the input data through a Serial
Input Interface. The decoded signal is a stereo,
mono, or dual channel digital output that can be
sent directly to a D/A converter, by the PCM Out-
put Interface. This interface is software program-
mable to adapt the STA015 digital output to the
most common DACs architectures used on the
market.
The functional STA015 chip partitioning is de-
scribed in Fig.1a and Fig.1b.
STA015 STA015B STA015TMPEG 2.5 LAYER III AUDIO DECODER
WITH ADPCM CAPABILITY
PRODUCT PREVIEWFigure 1b. BLOCK DIAGRAM for SO28 package
Figure 1a. BLOCK DIAGRAM for TQFP44 and LFBGA64 package
STA015-STA015B-STA015T
Figure 2. PIN CONNECTIONS
STA015-STA015B-STA015T
THERMAL DATA
1. OVERVIEW
1.1 - MP3 decoder engineThe MP3 decoder engine is able to decode any
Layer III compliant bitstream: MPEG1, MPEG2
and MPEG2.5 streams are supported. Besides
audio data decoding the MP3 engine also per-
forms ANCILLARY data extraction: these data
can be retrieved via I2C bus by the application
microcontroller in order to implement specific
functions.
Decoded audio data goes through a software vol-
ume control and a two-band equalizer blocks be-
fore feeding the output I2S interface. This results
in no need for an external audio processor.
MP3 bitstream is sent to the decoder using a sim-
ple serial input interface (see pins SDI, SCKR,
BIT_EN and DATA_REQ), supporting input rate
up to 20 Mbit/s. Received data are stored in a
256 bytes long input buffer which provides a
feedback line (see DATA_REQ pin) to the bit-
stream source (tipically an MCU).
1.2 - ADPCM encoder/decoder engineThis device also embeds a multistandard ADPCM
encoder/decoder supporting different sample
rates (from 8 KHz up to 32 KHz) and different
sample sizes (from 8 bit to 32 bits).
During encoding process two different interfaces
can be used to feed data: the serial input inter-
face (same interface used also to feed MP3 bit-
stream) or the ADC input interface, which pro-
vides a seamless connection with an external A/D
converter.
The currently used interface is selected via I2C
bus.
Also to retrieve encoded data two different inter-
faces are available: the I2C bus or the faster
GPSO output interface. GPSO interface is able to
output data with a bitrate up to 5 Mbit/s and its
control pins (GPSO_SCKR, GPSO_DATA and
GPSO_REQ) can be configured in order to easily
fit the target application.
1.3 - BYPASS functional modeIn order to allow using the device to post-process
auxiliary audio sources a special BYPASS mode
is available.
When the device is configured in BYPASS mode
the embedded DSP will process digital audio data
coming through the ADC input interface and will
output the resulting data to the external DAC.
Available processings include volume and a tone
controls.
ABSOLUTE MAXIMUM RATINGS
STA015-STA015B-STA015T
PIN DESCRIPTIONNote: In functional mode TESTEN must be connected to VDD.
STA015-STA015B-STA015T
1. ELECTRICAL CHARACTERISTICS: VDD = 3.3V ±0.3V; Tamb = 0 to 70°C; Rg = 50Ω unless otherwisespecified
DC OPERATING CONDITIONS
GENERAL INTERFACE ELECTRICAL CHARACTERISTICS
Note 1: The leakage currents are generally very small, < 1nA. The value given here is a maximum that can occur after an electrostatic stresson the pin.
Note 2: Human Body Model.
DC ELECTRICAL CHARACTERISTICS
Note 1: Takes into account 200mV voltage drop in both supply lines.
Note 2: X is the source/sink current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability.
Note 1: Min. condition: VDD = 2.7V, 125°C Min process Max. condition: VDD = 3.6V, -20°C Max.
POWER DISSIPATION
STA015-STA015B-STA015T
Figure 3. Test Circuit (refer to SO28 package)
Figure 4. Test Load Circuit
Test Load
2. FUNCTIONAL DESCRIPTION
2.1 - Clock SignalThe STA015 input clock is derivated from an ex-
ternal source or from a industry standard crystal
oscillator, generating input frequencies of 10,
14.31818 or 14.7456 MHz.
Other frequencies may be supported upon re-
quest to STMicroelectronics. Each frequency is
supported by downloading a specific configura-
tion file, provided by STM
XTI is an input Pad with specific levels.
CMOS compatibility
The XTI pad low and high levels are CMOS compatible; XTI pad noise margin is better than typical
CMOS pads.
TTL compatibility
The XTI pad low level is compatible with TTL while the high level is not compatible (for example if VDD =
3V TTL min high level = 2.0V while XTI min high level = 2.2V)
STA015-STA015B-STA015T
Figure 5. PLL and Clocks Generation System
2.2 - PLL & Clock Generator SystemWhen STA015 receives the input clock, as de-
scribed in Section 2.1, and a valid layer III input
bitstream, the internal PLL locks, providing to the
DSP Core the master clock (DCLK), and to the
Audio Output Interface the nominal frequencies of
the incoming compressed bit stream. The STA015
PLL block diagram is described in Figure 5.
The audio sample rates are obtained dividing the
oversampling clock (OCLK) by software programma-
ble factors. The operation is done by STA015 em-
bedded software and it is transparent to the user.
The STA015 PLL can drive directly most of the com-
mercial DACs families, providing an over sampling
clock, OCLK, obtained dividing the VCO frequency
with a software programmable dividers.
2.3 - STA015 Operational ModesThe device can be configured in 4 different op-
erational modes. To select one specific mode a
dedicated CHIP_MODE registers is available. For
proper operation the following steps must be is-
sued to switch between different modes:
- issue a software reset (SOFT_RESET register)
- select the desired mode (CHIP_MODE register)
- run the device (RUN register)
Hereby is a short description of each available
mode
ADPCM EncoderThis mode can be used to encode the incom-
ing bitstream with 4 different compression al-
gorithms. Moreover different sample frequen-
cies and word size are supported. For a
detailed description of this features refer to the
related registers.
ADPCM DecoderThis mode can be used when an ADPCM
compressed bitstream must be decoded.
The input interface handling and control flow is
the same as in the MP3 Mode.
BYPASS modeUsing this mode it’s possible to use the em-
bedded post-processing controls (volume and
tone controls) to process an incoming uncom-
pressed stereo audio stream. In this configura-
tion ADC input is the only supported interface.
This could be useful, for instance, to process
audio data coming from an external tuner or
some other auxiliary source.
MP3 modeIn MP3 Mode (default mode) STA015 decodes
the incoming bitstream, acting as a master of
the data communication from the source to it-
self.
This control is done by a specific buffer man-
agement, controlled by STA015 embedded
software. The data coming from the serial in-
terface are stored in the input buffer, a 256
bytes long FIFO.
The feedback line DATA_REQ actually is the
result of the h/w comparison between the writ-
ing address of the FIFO and the constant
value 252. This means that if the buffer is filled
up with more than 252 bytes the DATA_REQ
line goes low, requesting MCU to stop trans-
mission: the maximum time to stop transmit-
ting is given by the time required to transmit 4
bytes (this time, in turn, depends on the bit-
stream speed used to send MP3 data).
The input interface can receive data with a
speed up to 20Mbit/s. The speed at which the
FIFO is emptied is equal to the MP3 nominal
bitrate. Provided the FIFO is filled up with 252
bytes the time required to empty it (in worst
condition, which is 320kbit/s mpeg stream) is
about 6ms. So if no more data is received in
this time the buffer will be emptied and this will
badly affect the output audio.
STA015-STA015B-STA015T
In this mode the fractional part of the PLL is dis-
abled and the audio clocks are generated at
nominal rates. Fig. 6 describes the default
DATA_REQ signal behaviour. Programming
STA015 it is possible to invert the polarity of the
DATA_REQ line (register REQ_POL).
In order to allow proper operation of the device in
broadcast applications a special BRAODCAST
MP3 decoding mode is available. When config-
ured in BROADCAST mode the device will oper-
ate as a slave decoder and no more feedback will
be generated to the data source. The output PCM
clock will be automatically adjusted by the em-
bedded DSP in order to follow the incoming bit-
stream rate and to avoid input buffer under-
run/overrun. A special configuration file must be
used to enable this operational mode: the file
must be downloaded via I2C link after device
power-on. Please contact your local ST branch to
have more information about.
2.4 - STA015 Decoding StatesThere are three different decoder states: Idle,
Init, and Decode. Commands to change the de-coding states are described in the STA015 I2C
registers description.
Idle ModeIn this mode (entered after a S/W or H/W reset)
the decoder is waiting for the RUN command.
This mode should be used to initialize the con-
figuration registers of the device. The DAC con-
nected to STA015 can be initialized during this
mode (set MUTE to 1).
Init Mode"PLAY" and "MUTE" changes are ignored in this
mode. The internal state of the decoder will be
updated only when the decoder changes from the
state "init" to the state "decode". The "init" phase
ends when the first decoded samples are at the
output stage of the device.
Decode ModeThis mode is completely described by the follow-
ing table:
Figure 6. DATA_REQ control line
Figure 7. MPEG Decoder Interfaces.
STA015-STA015B-STA015T
Figure 8. Serial Input Interface Clocks
3. INTERFACE DESCRIPTION
3.1 - Serial Input InterfaceSTA015 receives the input data (MSB first)
through the Serial Input Interface (Fig.7). It is a
serial communication interface connected to the
SDI (Serial Data Input) and SCKR (Receiver Se-
rial Clock).
The interface can be configured to receive data
sampled on both rising and falling edge of the
SCKR clock. The BIT_EN pin, when set to low,
forces the bitstream input interface to ignore the
incoming data. For proper operation BIT_EN line
should be toggled only when SCKR is stable low
(for both SCLK_POL configuration). The possible
configurations are described in Fig. 8.
3.2 - GPSO Output InterfaceIn order to retrieve ADPCM encoded data a Gen-
eral Purpose Serial Output interface is available
(in TQFP44 and LFBGA64 packages only). The
maximum frequency for GPSO_SCKR clock is
the DSP system clock frequency divided by 3
(i.e. 8.192 MHz @ 24.58MHz). The interface is
based on a simple and configurable 3-lines proto-
col, as described by figure 10.
3.3 - PCM Output InterfaceThe decoded audio data are output in serial PCM
format. The interface consists of the following sig-
nals:
SDO PCM Serial Data Output
SCKT PCM Serial Clock Output
LRCLK Left/Right Channel Selection Clock
The output samples precision is selectable from
16 to 24 bits/word, by setting the output precision
with PCMCONF (16, 18, 20 and 24 bits mode)
register. Data can be output either with the most
significant bit first (MS) or least significant bit first
(LS), selected by writing into a flag of the
PCMCONF register.
Figure 9 gives a description of the several
STA015 PCM Output Formats. The sample rates
set decoded by STA015 is described in Table 1.
Figure 9. PCM Output Formats
Table 1: MPEG Sampling Rates (KHz)
STA015-STA015B-STA015T
Figure 10.To enable the GPSO interface bit GEN of
GPSO_ENABLE register must be set. Using the
GPSO_CONF register the protocol can be config-
ured in order to provide outcoming data on ris-
ing/falling edge of GPSO_SCKR input clock; the
GPSO_REQ request signal polarity (usually con-
nected to an MCU interrupt line) can be config-
ured as well.
3.4 ADC IntefaceBeside the serial input interface based on SDI
and SCKR lines a 3 wire flexible and user config-
urable input interface is also available, suitable to
interface with most A/D converters. To configure
this interface 4 specific I2 C registers are available
(ADC_ENABLE, ADC_CONF, ADC_WLEN and
ADC_WPOS). Refer to registers description for
more details.
3.5 General Purpose I/O Interface new general purpose I/O interface has been
added to this device (TQFP44 and LFBGA64
only). Actually only the strobe line is used in
ADPCM encoding mode to provide an interrupt;
other pins are reserved for future use. The re-
lated configuration register is GPIO_CONF. See
the following summary for related pin usage:
4 ADPCM ENCODING: OverviewAccording to the previously described interfaces
there are 4 ways to manage ADPCM data stream
while encoding. Input interface can be either the
serial receiver block (SDI + SCKR + DATA_REQ
lines) or the ADC specific interface.
Output interfaces can be either the I2 C bus (with
or without interrupt line) or the GPSO high-speed
serial interface (GPSO_REQ + GPSO_ DATA +
GPSO_SCKR lines). This result in the following 4
methods to handle encoding flow:
(*) STA013 Compatible mode
Figure. 11
STA015-STA015B-STA015T
5 - I2 C BUS SPECIFICATIONThe STA015 supports the I2 C protocol. This pro-
tocol defines any device that sends data on to the
bus as a transmitter and any device that reads
the data as a receiver. The device that controls
the data transfer is known as the master and the
others as the slave. The master always starts the
transfer and provides the serial clock for synchro-
nisation. The STA015 is always a slave device in
all its communications.
5. 1 - COMMUNICATION PROTOCOL
5.1.0 - Data transition or changeData changes on the SDA line must only occur
when the SCL clock is low. SDA transition while
the clock is high are used to identify START or
STOP condition.
5.1.1 - Start conditionSTART is identified by a high to low transition of
the data bus SDA signal while the clock signal
SCL is stable in the high state. START condition must precede any command
for data transfer.
The following 4 figures (fig. 12, 13, 14, 15) show
the available connection diagrams as far as
ADPCM encoding function. As shown in the fig-
ures some configuration is not available in SO28
package.
Figure 14. Input from BITSTREAM, Output fromGPSO
Figure 13. Input from ADC, Output from I2C +IRQ
Figure 15. Input from ADC, Output from GPSO
Figure 12. Input from BITSTREAM, Output fromI2C
STA015-STA015B-STA015T
5.1.2 - Stop conditionSTOP is identified by low to high transition of the
data bus SDA signal while the clock signal SCL is
stable in the high state. A STOP condition termi-
nates communications between STA015 and the
bus master.
5.1.3 - Acknowledge bitAn acknowledge bit is used to indicate a success-
ful data transfer. The bus transmitter, either mas-
ter or slave, releases the SDA bus after sending
8 bit of data.
During the 9th clock pulse the receiver pulls the
SDA bus low to acknowledge the receipt of 8 bits
of data.
5.1.4 - Data inputDuring the data input the STA015 samples the
SDA signal on the rising edge of the clock SCL.
For correct device operation the SDA signal has
to be stable during the rising edge of the clock
and the data can change only when the SCL line
is low.
5.2 - DEVICE ADDRESSINGTo start communication between the master and
the STA015, the master must initiate with a start
condition. Following this, the master sends onto
the SDA line 8 bits (MSB first) corresponding to
the device select address and read or write
mode.
The 7 most significant bits are the device address
identifier, corresponding to the I2 C bus definition.
For the STA015 these are fixed as 1000011.
The 8th bit (LSB) is the read or write operation
RW, this bit is set to 1 in read mode and 0 for
write mode. After a START condition the STA015
identifies on the bus the device address and, if a
match is found, it acknowledges the identification
on SDA bus during the 9th bit time. The following
byte after the device identification byte is the in-
ternal space address.
5.3 - WRITE OPERATION (see fig. 16)Following a START condition the master sends a
device select code with the RW bit set to 0.
The STA015 acknowledges this and waits for the
byte of internal address.
After receiving the internal bytes address the
STA015 again responds with an acknowledge.
5.3.1 - Byte writeIn the byte write mode the master sends one data
byte, this is acknowledged by STA015. The mas-
ter then terminates the transfer by generating a
STOP condition.
5.3.2 - Multibyte writeThe multibyte write mode can start from any inter-
nal address. The transfer is terminated by the
master generating a STOP condition.
Figure 17. Read Mode Sequence
Figure 16. Write Mode Sequence
STA015-STA015B-STA015T
5.4 - READ OPERATION (see Fig. 17)
5.4.1 - Current byte address readThe STA015 has an internal byte address
counter. Each time a byte is written or read, this
counter is incremented.
For the current byte address read mode, follow-
ing a START condition the master sends the de-
vice address with the RW bit set to 1.
The STA015 acknowledges this and outputs the
byte addressed by the internal byte address
counter. The master does not acknowledge the
received byte, but terminates the transfer with a
STOP condition.
5.4.2 - Sequential address readThis mode can be initiated with either a current
address read or a random address read. How-
ever in this case the master does acknowledge
the data byte output and the STA015 continues to
output the next byte in sequence.
To terminate the streams of bytes the master
does not acknowledge the last received byte, but
terminates the transfer with a STOP condition.
The output data stream is from consecutive byte
addresses, with the internal byte address counter
automatically incremented after one byte output.
6 - I2 C REGISTERS The following table gives a description of the
MPEG Source Decoder (STA015) register list.
The first column (HEX_COD) is the hexadecimal
code for the sub-address.
The second column (DEC_COD) is the decimal
code.
The third column (DESCRIPTION) is the descrip-
tion of the information contained in the register.
The fourth column (RESET) inidicate the reset
value if any. When no reset value is specifyed,
the default is "undefined".
The fifth column (R/W) is the flag to distinguish
register "read only" and "read and write", and the
useful size of the register itself.
Each register is 8 bit wide. The master shall oper-
ate reading or writing on 8 bits only.
2 C REGISTERS
STA015-STA015B-STA015T
2 C REGISTERS (continued)Note:
1) The HEX_COD is the hexadecimal adress that the microcontroller has to generate to access the information.
2) RESERVED: register used for production test only, or for future use.
STA015-STA015B-STA015T
6.1 - STA015 REGISTERS DESCRIPTIONThe STA015 device includes 256 I2 C registers. In
this document, only the user-oriented registers
are described. The undocumented registers are
reserved. These registers must never be ac-
cessed (in Read or in Write mode). The Read-
Only registers must never be written.
The following table describes the meaning of the
abbreviations used in the I2 C registers descrip-
tion:
VERSION
Address: 0x00 (00)Type: RO
MSB LSB
The VERSION register is read-only and it is used
to identify the IC on the application board.
IDENT
Address: 0x01 (01)Type: RO
Software Reset: 0xAC
Hardware Reset: 0xAC
MSB LSB
IDENT is a read-only register and is used to iden-
tify the IC on an application board. IDENT always
has the value "0xAC"
PLLCTL
Address: 0x05 (05)Type: R/W
Software Reset: 0xA1
Hardware Reset: 0xA1
MSB LSB
UPD_FRAC: when is set to 1, update FRAC in
the switching circuit. It is set to 1 after autoboot.
XTI2OCLK: when is set to 1, use the XTI as input
of the divider X instead of VCO output. It is set to
0 on HW reset.
XTI2DSPCLK: when is to 1, set use the XTI as in-
put of the divider S instead of VCO output. It is
set to 0 on HW reset.
PLLDIS: when set to 1, the VCO output is dis-
abled. It is set to 0 on HW reset.
SYS2OCLK: when is set to 1, the OCLK fre-
quency is equal to the system frequency. It is
useful for testing. It is set to 0 on HW reset.
OCLKEN: when is set to 1, the OCLK pad is en-
able as output pad. It is set to 1 on HW reset.
XTODIS: when is set to 1, the XTO pad is dis-
able. It is set to 0 on HW reset.
XTO_BUF: when this bit is set, the pin nr. 28
(OUT_CLOCK/DATA_REQ) is enabled. It is set
to 0 after autoboot.
PLLCTL (M)
Address: 0x06 (06)Type: R/W
Software Reset: 0x0C
Hardware Reset: 0x0C
PLLCTL (N)
Address: 0x07 (07)Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
The M and N registers are used to configure the
STA015 PLL by DSP embedded software.
M and N registers are R/W type but they are
completely controlled, on STA015, by DSP soft-
ware.
STA015-STA015B-STA015T
REQ_POL
Address: 0x0C (12)Type: R/W
Software Reset: 0x01
Hardware Reset: 0x00
The REQ_POL registers is used to program the
polarity of the DATA_REQ line.
MSB LSB
Default polarity (the source sends data when the
DATA_REQ line is high)
MSB LSB
Inverted polarity (the source sends data when the
DATA_REQ line is low)
SCLK_POL
Address: 0x0D (13)Type: R/W
Software Reset: 0x04
Hardware Reset: 0x04
MSB LSB (1) (2)
X = don’t care
SCLK_POL is used to select the working polarity
of the Input Serial Clock (SCKR).
(1) If SCLK_POL is set to 0x00, the data (SDI)
are sent with the falling edge of SCKR
and sampled on the rising edge.
(2) If SCLK_POL is set to 0x04, the data (SDI)
are sent with the rising edge of SCKR and
sampled on the falling edge.
ERROR_CODE
Address: 0x0F (15)Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
MSB LSB
X = don’t care
ERROR_CODE register contains the last error
occourred if any. The codes can be as follows:
SOFT_RESET
Address: 0x10 (16)Type: WO
Software Reset: 0x00
Hardware Reset: 0x00
MSB LSB
X = don’t care; 0 = normal operation; 1 = reset
When this register is written, a soft reset occours.
The STA015 core command register and the in-
terrupt register are cleared. The decoder goes in
to idle mode.
PLAY
Address: 0x13 (19)Type: R/W
Software Reset: 0x01
Hardware Reset: 0x01
MSB LSB
X = don’t care; 0 = normal operation; 1 = play
The PLAY command is handled according to the
state of the decoder, as described in section 2.5.
PLAY only becomes active when the decoder is
in DECODE mode.
STA015-STA015B-STA015T
DATA_REQ_ENABLE
Address: 0x18 (24)Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB LSB
MUTE
Address: 0x14 (20)Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB LSB
X = don’t care; 0 = normal operation; 1 = mute
The MUTE command is handled according to the
state of the decoder, as described in section 2.5.
MUTE sets the clock running.
CMD_INTERRUPT
Address: 0x16 (22)Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB LSB
X = don’t care;
0 = normal operation;
1 = write into I2 C/Ancillary Data
The INTERRUPT is used to give STA015 the
command to write into the I2C/Ancillary Data
Buffer (Registers: 0x7E ... 0xB5). Every time the
Master has to extract the new buffer content it
writes into this register, setting it to a non-zero
value.
The DATA_REQ_ENABLE register is used to
configure Pin n. 28 working as buffered output
clock or data request signal, used for multimedia
mode.
The buffered Output Clock has the same fre-
quency than the input clock (XTI)
SYNCSTATUS
Address: 0x40 (64)Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
MSB LSB
STA015-STA015B-STA015T
ADPCM_DATA BUFFER
Address: 0x40 - 0x51 (64 - 81)Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB LSB
ANCCOUNT_L
Address: 0x41 (65)Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
MSB LSB
ANCCOUNT_H
Address: 0x42 (66)Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
ANCCOUNT_H
MSB LSB
ANCCOUNT registers are logically concatenated
and indicate the number of Ancillary Data bits
available at every correctly decoded MPEG
frame.
HEAD_H[23:16]MSB LSB
x = don’t care
HEAD_M[15:8]MSB LSB
HEAD_L[7:0]MSB LSB
Address: 0x43, 0x44, 0x45 (67, 68, 69)Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
Head[1:0] emphasis
Head[2] original/copy
Head[3] copyrightHead
[5:4] mode extension
Head[7:6] mode
Head[8] private bit
Head[9] padding bit
Head[11:10] sampling frequency index
Head[15:12] bitrate index
Head[16] protection bit
Head[18:17] layer
Head[19] ID
Head[20] ID_ex
The HEAD registers can be viewed as logically
concatenated to store the MPEG Layer III Header
content. The set of three registers is updated
every time the synchronisation to the new MPEG
frame is achieved
The meaning of the flags are shown in the follow-
ing tables:
MPEG IDs
Layer
in Layer III these two flags must be set always to
"01".
Protection_bit
It equals "1" if no redundancy has been added
and "0" if redundancy has been added.
STA015-STA015B-STA015T
Bitrate_index
indicates the bitrate (Kbit/sec) depending on the
MPEG ID.
Sampling Frequencyindicates the sampling frequency of the encoded
audio signal (KHz) depending on the MPEG ID
Padding bit
if this bit equals ’1’, the frame contains an addi-
tional slot to adjust the mean bitrate to the sam-
pling frequency, otherwise this bit is set to ’0’.
Private bit
Bit for private use. This bit will not be used in the
future by ISO/IEC.
Mode
Indicates the mode according to the following ta-
ble. The joint stereo mode is intensity_stereo
and/or ms_stereo.
Mode extension
These bits are used in joint stereo mode. They in-
dicates which type of joint stereo coding method
is applied. The frequency ranges, over which the
intensity_stereo and ms_stereo modes are ap-
plied, are implicit in the algorithm.
Copyright
If this bit is equal to ’0’, there is no copyright on
the bitstream, ’1’ means copyright protected.
Original/Copy
This bit equals ’0’ if the bitstream is a copy, ’1’ if it
is original.
Emphasis
Indicates the type of de-emphasis that shall be
used.
DLA
Address: 0x46 (70)Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB LSB
STA015-STA015B-STA015T
DLA register is used to attenuate the level of
audio output at the Left Channel using the butter-
fly shown in Fig. 18. When the register is set to
255 (0xFF), the maximum attenuation is
achieved.
A decimal unit correspond to an attenuation step
of 1 dB.
DLB
Address: 0x47 (71)Type: R/W
Software Reset: 0xFF
Hardware Reset: 0xFF
MSB LSB
DLB register is used to re-direct the Left Channel
on the Right, or to mix both the Channels.
Default value is 0x00, corresponding at the maxi-
mum attenuation in the re-direction channel.
Figure 18. Volume Control and Output Setup
DRA
Address: 0x48 (72)Type: R/W
Software Reset: 0X00
Hardware Reset: 0X00
MSB LSB
DRA register is used to attenuate the level of
audio output at the Right Channel using the but-
terfly shown in Fig. 11. When the register is set to
255 (0xFF), the maximum attenuation is
achieved.
A decimal unit correspond to an attenuation step
of 1 dB.
STA015-STA015B-STA015T
DRB
Address: 0x49 (73)Type: R/W
Software Reset: 0xFF
Hardware Reset: 0xFF
MSB LSB
DRB register is used to re-direct the Right Chan-
nel on the Left, or to mix both the Channels. De-
fault value is 0x00, corresponding at the maxi-
mum attenuation in the re-direction channel.
CHIP_MODE
Address: 0x4D (77)Type: R/W
Hardware Reset: 0x00
Using this register it’s possible to select which op-
eration will be performed by the DSP.
Possible values are:
0x00 - MP3 decoding
0x01 - Reserved
0x02 - ADPCM Encoder
0x03 - ADPCM Decoder
0x04 - BYPASS mode
The DSP will check for the value of this register
right after the RUN command has been issued
(refer to RUN register). After that no more checks
will be performed: therefore a SOFT_RESET
must be generated in order to change the device
mode.
CRCR
Address: 0x4E (78)Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB LSB
The CRC register is used to enable/disable the
CRC check. If CRC_EN bit is cleared, the CRC
value encoded in the bitstream is checked
against the hardware one. If a discrepance oc-
curs, the current frame is skipped and the de-
coder is muted. The ERROR_CODE register is
affected with the value 0x01.
If CRC_EN bit is set, the result of the CRC check
is ignored, but the ERROR_CODE register is
nevertheless affected with the value 0x01 if a dis-
crepance has occurred.
MFSDF_441
Address: 0x50 (80)Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB LSB
This register contains the value for the PLL X
driver for the 44.1KHz reference frequency.
The VCO output frequency, when decoding
44.1KHz bitstream, is divided by (MFSDF_441 +1)
PLLFRAC_441_L
Address: 0x51 (81)Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB LSB
STA015-STA015B-STA015T
