STA001 ,RF FRONT-END FOR DIGITAL RADIOBLOCK DIAGRAMAGC1, AGC2SOP, SONCEPADJ1, PADJ2 SIP, SINGADJ1, GADJ2 V VDD1 DD4SUPPLY4 :IF1, SUPPLY1 ..
STA003T ,MPEG 2.5 LAYER III AUDIO DECODERBLOCK DIAGRAM: MPEG 2.5 Layer III Decoder Hardware Partitioning.RESET SDA SCL26 3 42I C CONTROL5 9S ..
STA011 , L-band RF front-end for digital radio
STA013 ,MPEG 2.5 LAYER III AUDIO DECODERELECTRICAL CHARACTERISTICS: specifiedDC OPERATING CONDITIONSSymbol Parameter ValueV Power Supply Vo ..
STA013$ ,MPEG 2.5 LAYER III (MP3) AUDIO DECODERABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Power Supply -0.3 to 4 VDDV Voltage on Input p ..
STA013$ ,MPEG 2.5 LAYER III (MP3) AUDIO DECODERELECTRICAL CHARACTERISTICS Symbol Parameter Test Condition Min. Typ. Max. Unit NoteI Low Level Inpu ..
STS100 , Multifunction Telecommunications Switch
STS10DN3LH5 ,Dual N-channel 30 V, 0.019 Ohm;, 10 A, SO-8 STripFET (TM); V Power MOSFETElectrical characteristics(T = 25 °C unless otherwise specified)CASE Table 4. Static Symbol Paramet ..
STS10N3LH5 ,N-channel 30 V, 0.019 Ohm;, 10 A, SO-8 STripFET(TM); V Power MOSFETElectrical characteristics(T = 25 °C unless otherwise specified)CASE Table 4. Static Symbol Paramet ..
STS10NF30L ,N-CHANNEL 30VSTS10NF30L®N - CHANNEL 30V - 0.011Ω - 10A SO-8STripFET™ POWER MOSFETPRELIMINARY DATATYPE V R IDSS ..
STS10PF30L ,P-CHANNEL 30VABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V = 0) 30 VDS GSV Drain- ..
STS11N3LLH5 , N-channel 30 V, 0.0117 Ω, 11 A, SO-8 STripFET™ V Power MOSFET
STA001
RF FRONT-END FOR DIGITAL RADIO
1/20
STA001November 2002 SINGLE CHIP RECEIVER FOR SATELLITE
DIGITAL TRANSMISSION SUPERHETERODYNE RECEIVER WITH IF
OUTPUT HIGH INPUT INTERCEPT POINT, LOW
MIXER NOISE 54dB IF VGA GAIN RANGE ADJUSTABLE RF GAIN ADJUSTABLE IF GAIN INTEGRATED RF VCO INTEGRATED IF VCO INTEGRATED SYNTHESIZERI2 CBUS COMPATIBLE PROGRAMMING
INTERFACE UNREGULATED 2.7 V TO 3.3V VOLTAGE
SUPPLY LOW COST EXTERNAL COMPONENTS
DESCRIPTIONThe STA001 is an RF IC using STMicroelectronics
HSB2 High Speed Bipolar Technology for one chip so-
lution for the Starman digital satellite radio receiver.
The STA001 is assembled in a TQFP44 package.
The frontend architecture is a double conversion re-
ceiver (see block diagram) .
The chip includes all the RF functions up to low IF
and manages the signals to and from the baseband.
PRODUCT PREVIEWRF FRONT-END FOR DIGITAL RADIO
BLOCK DIAGRAM
STA001 2/20
PIN CONNECTION (Top view)
PIN FUNCTION
3/20
STA001
ABSOLUTE MAXIMUM RATINGS
OPERATING CONDITIONS
PIN FUNCTION (continued)
STA001 4/20
THERMAL DATA(1) According to JEDEC specification on a 4 layers board
ELECTRICAL CHARACTERISTCS
SUPPLY CURRENTS (Tamb = 25°, VDD = 3V)
LNA, RF MIXER AND IF1 BUFFER (T = 25°, VDD-VSS = 3V)
5/20
STA001
IF VGA AMPLIFIER, IF MIXER AND OUTPUT BUFFER (T = 25°, VDD-VSS = 3V)
ELECTRICAL CHARACTERISTCS (continued)
STA001 6/20
Figure 1. Typical IF Overall Gain vs Control Voltage
ELECTRICAL CHARACTERISTCS (continued)
7/20
STA001
ELECTRICAL CHARACTERISTCS (continued)
CRYSTAL OSCILLATOR (T = 25°, VDD-VSS = 3V)
PLLs, SYNTHESIZERS (T = 25°, VDD-VSS = 3V)*** Using loop filter as suggested in application board schematics
RF VCO (T = 25°, VDD-VSS = 3V)
STA001 8/20
IF VCO (T = 25°, VDD-VSS = 3V)
DIGITAL INTERFACE TO MP (SCL, SDA, TLCK) AND XOSEL INTERFACE (T = 25°, VDD-VSS = 3V)
DIFFERENTIAL DIGITAL INTERFACE (M_CLK1, M_CLK2) (T = 25°, VDD-VSS = 3V)
ELECTRICAL CHARACTERISTCS (continued)
9/20
STA001
XOSEL, CE, TLCK, ENRFOSC TRUTH TABLE (LOW = GND, HIGH = VDD)
ADDITIONAL DIGITAL INTERFACE (CE) (T = 25°, VDD-VSS = 3V)
(LOW=GND, HIGH=VDD)
ADDITIONAL OPTIONAL INTERFACE INFORMATION (REF)
ELECTRICAL CHARACTERISTCS (continued)
STA001 10/20
FUNCTIONAL DESCRIPTION
Receiver chain The receiver chain transforms the RF frequency signals to an IF signal at 1.84 MHz Carrier directly usable by
the Channel decoder.
In front of the STA001 IC it can be placed an external LNA and a bandpass filter; the bandpass filter limitates
the input bandwidth and guarantees a suitable rejection to the image frequency.
The STA001 input stage is a LNA working in the 1452-1492 MHz band. The RF signal is downconverted, using
an active mixer, to a first IF of 115.244 MHz. The first LO is tunable with a frequency step of 460 KHz.
The RF can be reduced 5dB by an external trimmer/resistor connected between PADJ1 and PADJ2 pins.
An IF variable gain amplifier guarantees 54 dB typical of gain range.
Using pins GADJ1, GADJ2, the output RX signal level can be decreased to the desired value by an external
trimmer/resistor.
Moreover, the IF chain can be configured to have a fixed gain by fixing statically control voltages on AGC1 and
AGC2 pins (i.e. V(AGC1)=VCC and V(AGC2)=GND), and by trimming the gain through connecting an external
resistor between GADJ1 and GADJ2.
By using an 800 Ohm resistor connected between GADJ1 and GADJ2, for example, a typical 56 dBs IF static
gain is obtained.
The first IF signal, having a bandwidth of 2.5 MHz, shaped by an external SAW filter, is downconverted to a
second IF of 1.84 MHz.
A differential clock output at 14.72 MHz is available to be used from the baseband.
Synthesizers, PLL, charge pump and VCOsThe first Voltage controlled Oscillator is controlled by an integrated PLL and it's able to cover a frequency range
of 37MHz with a step size of 460 KHz.
The second Voltage controlled oscillator produces a fixed 117.08MHz frequency controlled by a second inte-
grated PLL. Moreover, the 2nd PLL is able to select 2 other fixed frequencies, i.e. 111.76MHz and 122.4MHz,
suitable for application test.
The other components of the first PLL synthesizer are a low frequency programmable divider and a dual mod-
ulus prescaler; a fixed dividers is instead used to synthesize the second VCO frequency. Other fixed internal
dividers are used to get the comparation frequencies of both loops.
Channel selection is made through the I2 CBUS interface , directly from the μP.
POWER SUPPLIESThe chip operates from an unregulated power supply of 2.7 to 3.3 Volts. All interface circuits to the baseband
chips are operating between these supplies unless otherwise specified.
INTERFACE SPECIFICATIONAll the interface voltage levels to the micro controller are referenced to the supply voltage of the interface power
supply (GND) . The interface voltage levels are therefore fully compatible with the base band circuits.
The digital levels are all CMOS threshold compatible with the exception of M_CLK1, M_CLK2 pins (ECL type).
For completeness all other interface signals are also included.
2 C BUS INTERFACEData transmission from microprocessor to the STA001 takes place through the 2 wires I2 C BUS interface, consisting
of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected to SDA and SCL).
