ST92T163E-ST92T163L Fast Delivery |IC PHOENIX CO.,LIMITED

ST92T163L ,8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I2C, SCI, & MFTST921638/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES2WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I C, S ..
ST92T163N4B1 ,8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I 2 C, SCI, & MFTGENERAL DESCRIPTION . . . . . . 61.1 INTRODUCTION . 61.1.1 Core Architecture ..
ST92T163R4T1 ,8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I 2 C, SCI, & MFTTable of Contents3.4 PRIORITY LEVEL ARBITRATION . . . 483.4.1 Priority Level 7 (Lowest) . ..
ST92T163R4T1E ,8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I 2 C, SCI, & MFTFunctional Description . . . . . . 643.12.4 Programming Considerations . 663.12.5 Regist ..
ST92T163R4T1L ,8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I 2 C, SCI, & MFTTable of Contents6.1 INTRODUCTION 906.2 EXTERNAL MEMORY SIGNALS . . . . 916.2.1 AS: Ad ..
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ST92T163E-ST92T163L
8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I2C, SCI, & MFT
January 2000 1/224
ST92163
8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES
WITH 16 ENDPOINTS, 20K ROM, 2K RAM,I2 C, SCI, & MFT
PRELIMINARY DATA Internal Memories: 20 Kbytes ROM/EPROM/OTP,2 Kbytes RAM Register oriented 8/16bit core 224 general purpose registers available as
RAM, accumulatorsor index pointers Minimum instruction cycle time: 167ns (@24
MHz CPU frequency) Low power modes: WFI, SLOW, HALT and
STOP DMA controllerfor reduced processor overhead Full speed USB interface with DMA, compliant
with USB specifications version 1.1 (in normal
voltage mode) USB Embedded Functions with 16 fully
configurable endpoints (buffer size
programmable), supporting all USB data
transfer types (Isochronous included) On-chip USB transceiver and 3.3 voltage
regulator MultimasterI2 C-bus serial interface up to
400KHz. with DMA capability Serial Communications Interface (SCI) with
DMA capability: Asynchronous modeupto 315 Kb/s Synchronous mode upto3 MHz External memory interface (8-bit data/16-bit
address) with DMA capability from the USB 16-bit Multi-Function Timer (12 operating
modes) with DMA capability 16-bit Timer with 8-bit prescaler and Watchdog 6-channel, 8-bit A/D Converter (ADC) 15 interrupt pinson8 interrupt channels 14 pins programmableas wake-upor additional
external interrupts 42 (DIP56)or44 (QFP64) fully programmable
I/Os with6or8 high sink pads (10 mA@1V) Programmable PLL clock generator (RCCU)
usinga low frequency external quartz(8 MHz) On-chip RC oscillatorfor low power operation Low Voltage Detector Reseton some devices1 Rich instruction set with14 addressing modes Several operating voltage modes available on
some devices1: Normal Voltage Mode 8-MHz Low Voltage Mode 16-MHz Low Voltage Mode 0-24 MHz CPU clock operation@ 4.0-5.5V (all
devices) 0-8 MHz CPU clock operation@ 3.0-4.0V (8-
MHz and 16-MHz Low Voltage devices) 0- 16 MHz CPU clock operation@ 3.0-4.0V
(16-MHz Low Voltage devices only) Division-by-zero trap generation 0o Cto70oC temperature range Low EMI design supporting single sided PCB Complete development tools, including
assembler, linker, C-compiler, archiver, source
level debugger and hardware emulators, and
Real Time Operating System
Note1: Referto “Device Summary” on page6
TQFP64
PSDIP56
Rev. 1.9
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Table of Contents
ST92163 ..... .......... .... ..... ........ ......... ...1 GENERAL DESCRIPTION...... ..... ......... .... ....... ............ ...........6
1.1 INTRODUCTION............. ...... ..... .............. ....... ...... ......6
1.1.1 Core Architecture................. ....... ................ ... ........9
1.1.2 Instruction Set.................... ....... ................ ... ........9
1.1.3 External MEMORY INTERFACE........................... ...... ......9
1.1.4 OPERATING MODES...............................................9
1.1.5 On-chip Peripherals............................ .... ................ 10
1.2 PIN DESCRIPTION.. ..... ....... ...... ..... ......... ....... ............. 11
1.3 I/O PORT PINS.................... ............ ....... ............. ..... 13
1.4 MEMORY MAP.......... ..... ... ...... .... ................... ...... .... 19
1.5 ST92163 REGISTER MAP .............. ..... .......... .... ............... 20 DEVICE ARCHITECTURE.......... ...... ..... .............. ....... ...... ..... 27
2.1 CORE ARCHITECTURE.................. .... ....................... ..... 27
2.2 MEMORY SPACES.............. ..... ..................... ...... ..... ... 27
2.2.1 Register File........................... .... .... ........... ........ 27
2.2.2 Register Addressing..... ...... ..... .... ....................... ..... 29
2.3 SYSTEM REGISTERS......................... .... .... ........... ........ 30
2.3.1 Central Interrupt Control Register........... ........ .... ....... ........ 30
2.3.2 Flag Register...... ..... ....... ... .... ....... ....... .... ....... ... 31
2.3.3 Register Pointing Techniques.... ..... ....... ....... ....... ...... ..... 32
2.3.4 Paged Registers................................................... 35
2.3.5 Mode Register..... ..... ......... .... ....... ............ .......... 35
2.3.6 Stack Pointers..................... .... ....................... ..... 36
2.4 MEMORY ORGANIZATION............... ....... ................ ... ....... 38
2.5 MEMORY MANAGEMENT UNIT.......... ..... ......... .................... 39
2.6 ADDRESS SPACE EXTENSION............................................ 40
2.6.1 Addressing 16-Kbyte Pages......... ....................... ...... .... 40
2.6.2 Addressing 64-Kbyte Segments..... ..... ......... ....... ............. 41
2.7 MMU REGISTERS. ....... ..... ....... ... .... ....... ...... ..... ....... ... 41
2.7.1 DPR[3:0]: Data Page Registers............................ ...... ..... 41
2.7.2 CSR: Code Segment Register... ............ ....... ...... ....... ..... 43
2.7.3 ISR: Interrupt Segment Register............ .... .... .... ....... ........ 43
2.7.4 DMASR: DMA Segment Register........... .... .... .... ....... ........ 43
2.8 MMU USAGE.......................... ....... ................ ... ....... 45
2.8.1 Normal Program Execution............................ ..... ....... ... 45
2.8.2 Interrupts.............................. .... .... .... ....... ........ 45
2.8.3 DMA................................. ........ .... ....... ........ 45 INTERRUPTS.. .............. ..... ......... .... ....... ............ .......... 46
3.1 INTRODUCTION............. ...... ..... .............. ....... ...... ..... 46
3.2 INTERRUPT VECTORING ....... ....... ..... ......... ....... ............. 47
3.2.1 Divideby Zero trap................ ....... ................ .......... 47
3.2.2 Segment Paging During Interrupt Routines. ................... ...... .... 48
3.3 INTERRUPT PRIORITY LEVELS........................................... 48
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Table of Contents
3.4 PRIORITY LEVEL ARBITRATION...... ..... ....... ....... ....... ...... ..... 48
3.4.1 Priority level7 (Lowest)............................................. 48
3.4.2 Maximum depthof nesting...... ..... ..................... ...... ..... 48
3.4.3 Simultaneous Interrupts............ ....... ................ ... ....... 48
3.4.4 Dynamic Priority Level Modification.................................... 49
3.5 ARBITRATION MODES................. ..... ......... ....... ............. 49
3.5.1 Concurrent Mode.................................................. 49
3.5.2 Nested Mode...... ..... ....... ... .... ....... ....... .... ....... ... 52
3.6 EXTERNAL INTERRUPTS..................... .... .... ........... ........ 54
3.7 MANAGEMENT OF WAKE-UP LINES AND EXTERNAL INTERRUPT LINES. ..... ... 56
3.8 TOP LEVEL INTERRUPT................. .... ....................... ..... 57
3.9 ON-CHIP PERIPHERAL INTERRUPTS........................... ...... ..... 57
3.10 INTERRUPT RESPONSE TIME. ...... ..... .... ....................... ..... 58
3.11 INTERRUPT REGISTERS.. ..... ......... .... ................... ...... .... 59
3.12 WAKE-UP/ INTERRUPT LINES MANAGEMENT UNIT (WUIMU).................. 63
3.12.1 Introduction.................. ....... ..... ....... ...... ....... ..... 63
3.12.2 Main Features............................................. ..... ... 63
3.12.3 Functional Description.............................................. 64
3.12.4 Programming Considerations.......................... ..... ....... ... 66
3.12.5 Register Description. ............ ... ........... ....... ...... ..... ... 67 ON-CHIP DIRECT MEMORY ACCESS (DMA)....... ............ .... ............... 70
4.1 INTRODUCTION............. ...... ..... .............. ....... ...... ..... 70
4.2 DMA PRIORITY LEVELS... ..... ......... .... ....... ............ ...... .... 70
4.3 DMA TRANSACTIONS.............. ..... ....... ....... ....... ...... ..... 71
4.4 DMA CYCLE TIME............... ..... ..................... ...... ..... ... 73
4.5 SWAP MODE............ ..... ......... .... ....... ............ ...... .... 73
4.6 DMA REGISTERS............ ...... ..... .... ....................... ..... 74 RESET AND CLOCK CONTROL UNIT (RCCU)... .... ................... ...... .... 75
5.1 INTRODUCTION............. ...... ..... .............. ....... ...... ..... 75
5.2 CLOCK CONTROL UNIT....... ...... ..... .... ....................... ..... 75
5.2.1 Clock Control Unit Overview..... ..... .............. ....... ...... ..... 75
5.3 CLOCK MANAGEMENT............. ....... ..... ....... ...... ....... ..... 77
5.3.1 PLL Clock Multiplier Programming.... .... ................... ...... .... 78
5.3.2 CPU Clock Prescaling.............................................. 78
5.3.3 Peripheral Clock................................................... 78
5.3.4 Low Power Modes......................................... ..... ... 79
5.3.5 Interrupt Generation............................ .... ................ 79
5.4 CLOCK CONTROL REGISTERS................. .... .... ........... ........ 81
5.5 OSCILLATOR CHARACTERISTICS........... ...... ....... ..... ....... ..... 85
5.6 RESET/STOP MANAGER...... ...... ..... .... ....................... ..... 86
5.6.1 Reset Pin Timing... ..... ......... ..... ....... ........... ....... ... 87
5.7 STOP MODE...................... ............ ....... ...... ....... ..... 87
5.8 LOW VOLTAGE DETECTOR (LVD) RESET.. ....... ................ ... ....... 88
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Table of Contents EXTERNAL MEMORY INTERFACE (EXTMI)...................................... 89
6.1 INTRODUCTION............. ...... ..... .............. ....... ...... ..... 89
6.2 EXTERNAL MEMORY SIGNALS................. ....... .... ....... ......... 90
6.2.1 AS: Address Strobe..................... ........ .... ....... ........ 90
6.2.2 DS: Data Strobe.... ..... ......... .... ....... ............ ...... .... 90
6.2.3 DS2: Data Strobe2................................................. 90
6.2.4 RW: Read/Write.... ..... .......... .... ....... ...... ..... ....... ... 93
6.2.5 BREQ, BACK: Bus Request, Bus Acknowledge................... ..... ... 93
6.2.6 PORT0...... ....................... ... ............. ............. 94
6.2.7 PORT1...... ....................... ... ............. ............. 94
6.2.8 WAIT: External Memory Wait.......................... ..... ....... ... 94
6.3 REGISTER DESCRIPTION. ..... ....... ... .... ....... ...... ..... ....... ... 95 I/O PORTS............................. ....... ..... ....... ...... ....... ..... 98
7.1 INTRODUCTION............. ...... ..... .............. ....... ...... ..... 98
7.2 SPECIFIC PORT CONFIGURATIONS............................... ..... ... 98
7.3 PORT CONTROL REGISTERS.................. ....... .... ....... ......... 98
7.4 INPUT/OUTPUT BIT CONFIGURATION...................................... 99
7.5 ALTERNATE FUNCTION ARCHITECTURE........................ ...... .... 103
7.5.1 Pin Declaredas I/O.. ..... ......... ..... ....... ........... ......... 103
7.5.2 Pin Declaredasan Alternate Input.................................... 103
7.5.3 Pin Declaredasan Alternate Function Output........................... 103
7.6 I/O STATUS AFTER WFI, HALT AND RESET...................... ...... .... 103 ON-CHIP PERIPHERALS........... ...... ..... .... ....................... .... 104
8.1 TIMER/WATCHDOG (WDT)............. ..... ......... ................... 104
8.1.1 Introduction............ ...... ..... .... ....................... .... 104
8.1.2 Functional Description......... ..... .............. ....... ...... .... 105
8.1.3 Watchdog Timer Operation.......... .... ................... ......... 106
8.1.4 WDT Interrupts .... ....... ....... ..... ......... ....... ............ 108
8.1.5 Register Description..... ...... ..... .... ....................... .... 109
8.2 MULTIFUNCTION TIMER (MFT)........................ .... ............... 111
8.2.1 Introduction............ ...... ..... .... ....................... .... 111
8.2.2 Functional Description......... ..... .............. ....... ...... .... 113
8.2.3 Input Pin Assignment............. ..... ......... ....... ............ 116
8.2.4 Output Pin Assignment............................................. 120
8.2.5 Interrupt and DMA................ ....... ................ ... ...... 122
8.2.6 Register Description..... ...... ..... .... ....................... .... 124
8.3 USB PERIPHERAL (USB).. ..... ... ...... ....................... ......... 135
8.3.1 Introduction............ ...... ..... .... ....................... .... 135
8.3.2 Main Features.......... ...... ..... .... ....................... .... 135
8.3.3 Functional Description......... ..... .............. ....... ...... .... 135
8.3.4 Register Description..... ...... ..... .... ....................... .... 138
8.3.5 Register pages summary........... ....... ................ ... ...... 148
8.4 SERIAL COMMUNICATIONS INTERFACE (SCI).............................. 150
8.4.1 Introduction............ ...... ..... .... ....................... .... 150
8.4.2 Functional Description......... ..... .............. ....... ...... .... 151
8.4.3 SCI Operating Modes.............................................. 152
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Table of Contents
8.4.4 Serial Frame Format............................................... 155
8.4.5 Clocks And Serial Transmission Rates. ..... ....... ....... .... ......... 158
8.4.6 SCI Initialization Procedure............... .... .... ........... ....... 158
8.4.7 Input Signals................. ..... ....... ....... ....... ...... .... 160
8.4.8 Output Signals............................................ ....... 160
8.4.9 Interrupts and DMA............ ..... ....... ....... ....... ...... .... 161
8.4.10 Register Description.... ....... ....... ..... ............. ....... .... 164
8.5 I2C BUS INTERFACE......................... .... .... .... ....... ....... 175
8.5.1 Introduction............ ...... ..... .... ....................... .... 175
8.5.2 Main Features.......... ...... ..... .... ....................... .... 175
8.5.3 Functional Description......... ..... .............. ....... ...... .... 176
8.5.4 I2C State Machine.. ..... ......... .... ....... ............ ......... 178
8.5.5 Interrupt Features............. ....... ..... ....... ...... ....... .... 183
8.5.6 DMA Features...... ..... ....... ... .... ....... ....... .... ......... 184
8.5.7 Register Description..... ...... ..... .... ....................... .... 186
8.6 A/D CONVERTER (A/D)................. ....... ................ ... ...... 197
8.6.1 Introduction............ ...... ..... .... ....................... .... 197
8.6.2 Main Features.......... ...... ..... .... ....................... .... 197
8.6.3 General Description..................... .... .... ........... ....... 197
8.6.4 Register Description..... ...... ..... .... ....................... .... 199 ELECTRICAL CHARACTERISTICS................... .... .... ........... ....... 201 GENERAL INFORMATION ..... ....... ...... ..... ......... ....... ............ 218
10.1 EPROM/OTP PROGRAMMING......................... .... ............... 218
10.2 PACKAGE DESCRIPTION............................................... 219
10.3 ORDERING INFORMATION............. ..... ......... ................... 221
10.4 TRANSFER OF CUSTOMER CODE.... ....... ..... ....... ...... ....... .... 221

Partno	Mfg	Dc	Qty	Available	Descript
ST92T163E	ST	N/a	216	avai	8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I2C, SCI, & MFT
ST92T163L	ST	N/a	453	avai	8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I2C, SCI, & MFT