ST90T158M9LVQ1 Fast Delivery |IC PHOENIX CO.,LIMITED

ST90T158M9LVQ1 ,8/16-BIT MICROCONTROLLER (MCU) WITH 16 TO 64K ROM, OTP OR EPROM, 512 TO 2K RAMTable of Contents4.2.1 Divide by Zero trap .... .. . ... . .. .. .. . .. .. . ... .. .. .. . 484. ..
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ST90T158M9LVQ1
8/16-BIT MCU FAMILY WITH UP TO 64K ROM/OTP/EPROM AND UP TO 2K RAM
January 2000 1/190
Rev.3.0
ST90158- ST90135
8/16-BIT MCU FAMILY WITH TO 64K ROM/OTP/EPROM AND UP TO 2K RAM Register File based 8/16bit Core Architecture
with RUN, WFI, SLOW and HALT modes0-16 MHz Operation@ 5V±10%, -40°Cto
+85°C and 0°C to +70°C Operating
Temperature Ranges0-14 MHz Operation@ 3V±10% and 0°Cto
+70°C Operating Temperature Range Fully Programmable PLL Clock Generator, with
Frequency Multiplication and low frequency,
low cost external crystal Minimum 8-bit Instruction Cycle time: 83ns-(@ MHz internal clock frequency) Minimum 16-bit Instruction Cycle time: 250ns-24 MHz internal clock frequency) Internal Memory: EPROM/OTP/ROM 16/24/32/48/64K bytes ROMless version available RAM 512/768/1K/1.5K/2K bytes Maximum External Memory: 64K bytes 224 general purpose registers availableas
RAM, accumulatorsor index pointers (register
file) 80-pin Plastic Quad Flat Package and 80-pin
Thin Quad Flat Package 67 fully programmableI/Obits8 external and1 Non-Maskable Interrupts DMA Controller and Programmable Interrupt
Handler Single Master Serial Peripheral Interface Two 16-bit Timers with 8-bit Prescaler, one
usableasa Watchdog Timer (software and
hardware) Three (ST90158)or two (ST90135) 16-bit
Multifunction Timers, each with an8 bit
prescaler, 12 operating modes and DMA
capabilities8 channel 8-bit Analogto Digital Converter, with
Automatic voltage monitoring capabilities and
external reference inputs Two (ST90158)or one (ST90135) Serial
Communication Interfaces with asynchronous,
synchronous and DMA capabilities Rich InstructionSet with14 Addressing modes Division-by-Zero trap generation Versatile Development Tools, including
Assembler, Linker, C-compiler, Archiver,
Source Level Debugger and Hardware
Emulators with Real-Time Operating System
available from Third Parties
DEVICE SUMMARY
DEVICE
Program
Memory
(Bytes)
RAM
(Bytes) MFT SCI PACKAGE
ST90135
16K ROM 512 2 1
PQFP80
24K ROM 768 2 1
32K ROM 1K 2 1
ST90158
48K ROM 1.5K 3 2
64k ROM 2K 3 2 PQFP80/
TQFP80
ST90E158 64K
EPROM 2K 3 2 CQFP80
ST90E158LV 64K
EPROM 2K 3 2 CQFP80
ST90T158 64K OTP 2K 3 2 PQFP80
ST90T158LV 64K OTP 2K 3 2 PQFP80/
TQFP80/
ST90R158 ROMless 2K 3 2 PQFP80/
TQFP80
PQFP80
TQFP80
2/190
Table of Contents
190 GENERAL DESCRIPTION...... .............. .... ....... .......................6
1.1 INTRODUCTION............. ................................ ............6
1.1.1 ST9+ Core... .... ....... ....... .............. .....................6
1.1.2 Power Saving Modes............. .............. .....................6
1.1.3 system Clock......................................................6
1.1.4 I/O Ports.............. ................................ ............6
1.1.5 Multifunction Timers (MFT)............................................7
1.1.6 Standard Timer (STIM)...............................................7
1.1.7 Watchdog Timer (WDT)............ .... ......................... .....7
1.1.8 Serial Peripheral Interface (SPI).................... ....................7
1.1.9 Serial Communications Controllers (SCI)............ .....................7
1.1.10 Analog/Digital Converter (ADC)............................ ............7
1.2 PIN DESCRIPTION.. .................. .............. ....................10
1.3 I/O PORT PINS.........................................................13 DEVICE ARCHITECTURE.......... ................................ ...........18
2.1 CORE ARCHITECTURE.................. ................................18
2.2 MEMORY SPACES.............. ................................ ........18
2.2.1 Register File........................... .... .......................18
2.2.2 Register Addressing..... ........... ................................20
2.3 SYSTEM REGISTERS......................... .... .......................21
2.3.1 Central Interrupt Control Register........... ...........................21
2.3.2 Flag Register...... ...............................................22
2.3.3 Register Pointing Techniques.............................. ...........23
2.3.4 Paged Registers...................................................26
2.3.5 Mode Register..... .............. .... ....... ......................26
2.3.6 Stack Pointers..................... ................................27
2.4 MEMORY ORGANIZATION............... .................................29
2.5 MEMORY MANAGEMENT UNIT.......... .............. ....................30
2.6 ADDRESS SPACE EXTENSION............................................31
2.6.1 Addressing 16-Kbyte Pages......... ............................. ....31
2.6.2 Addressing 64-Kbyte Segments..... .............. ....................32
2.7 MMU REGISTERS. ....... ................................ ...............32
2.7.1 DPR[3:0]: Data Page Registers............................ ...........32
2.7.2 CSR: Code Segment Register........................................34
2.7.3 ISR: Interrupt Segment Register............ .... .......................34
2.7.4 DMASR: DMA Segment Register........... .... .......................34
2.8 MMU USAGE.......................... .................................36
2.8.1 Normal Program Execution............................ ...............36
2.8.2 Interrupts.............................. .... .......................36
2.8.3 DMA................................. ...........................36 REGISTER AND MEMORY MAP .............. ............... ...................37
3.1 MEMORY CONFIGURATION............. ............................. ....37
3.2 EPROM PROGRAMMING.................................................37
3.3 MEMORY MAP.......... .............. .... ......................... ....39
3.4 ST90158/135 REGISTER MAP.............................................40 INTERRUPTS.. .............. .............. .... ....... ......................48
4.1 INTRODUCTION............. ................................ ...........48
4.2 INTERRUPT VECTORING ....... ....... .............. ....................48
3/190
Table of Contents
4.2.1 Divideby Zero trap................ .................................48
4.2.2 Segment Paging During Interrupt Routines. ......................... ....49
4.3 INTERRUPT PRIORITY LEVELS...........................................49
4.4 PRIORITY LEVEL ARBITRATION................................ ...........49
4.4.1 Priority level7 (Lowest).............................................49
4.4.2 Maximum depthof nesting................................ ...........49
4.4.3 Simultaneous Interrupts............ .................................49
4.4.4 Dynamic Priority Level Modification....................................50
4.5 ARBITRATION MODES................. .............. ....................50
4.5.1 Concurrent Mode..................................................50
4.5.2 Nested Mode...... ...............................................53
4.6 EXTERNAL INTERRUPTS..................... .... .......................55
4.7 TOP LEVEL INTERRUPT................. ................................57
4.8 ON-CHIP PERIPHERAL INTERRUPTS........................... ...........57
4.9 INTERRUPT RESPONSE TIME. ........... ................................58
4.10 INTERRUPT REGISTERS.. .............. .... ......................... ....59 ON-CHIP DIRECT MEMORY ACCESS (DMA)................... ...................63
5.1 INTRODUCTION............. ................................ ...........63
5.2 DMA PRIORITY LEVELS... .............. .... ....... .................. ....63
5.3 DMA TRANSACTIONS........................................ ...........64
5.4 DMA CYCLE TIME............... ................................ ........66
5.5 SWAP MODE............ .............. .... ....... .................. ....66
5.6 DMA REGISTERS............ ........... ................................67 RESET AND CLOCK CONTROL UNIT (RCCU)... .... ......................... ....68
6.1 INTRODUCTION............. ................................ ...........68
6.2 CLOCK CONTROL UNIT....... ........... ................................68
6.2.1 Clock Control Unit Overview............................... ...........68
6.3 CLOCK MANAGEMENT..................................................69
6.3.1 PLL Clock Multiplier Programming.... .... ......................... ....70
6.3.2 CPU Clock Prescaling..............................................70
6.3.3 Peripheral Clock...................................................70
6.3.4 Low Power Modes......................................... ........71
6.3.5 Interrupt Generation............................ .... ................71
6.4 CLOCK CONTROL REGISTERS................. .... .......................74
6.5 OSCILLATOR CHARACTERISTICS........... ..............................77
6.6 RESET/STOP MANAGER...... ........... ................................79
6.6.1 RESETPin Timing................ .................................80
6.7 EXTERNAL STOP MODE.. .............. .... ....... .................. ....80 EXTERNAL MEMORY INTERFACE (EXTMI)......................................81
7.1 INTRODUCTION............. ................................ ...........81
7.2 EXTERNAL MEMORY SIGNALS................. ....... .... ....... .........82
7.2.1 AS: Address Strobe..................... ...........................82
7.2.2 DS: Data Strobe.... .............. .... ....... .................. ....82
7.2.3 DS2: Data Strobe2.................................................82
7.2.4 RW: Read/Write.... ................................ ...............85
7.2.5 BREQ, BACK: Bus Request, Bus Acknowledge................... ........85
7.2.6 PORT0...... ....................................................86
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Table of Contents
7.2.7 PORT1...... ....................................................86
7.2.8 WAIT: External Memory Wait.......................... ...............86
7.3 REGISTER DESCRIPTION. ................................ ...............87I/O PORTS..................................................................90
8.1 INTRODUCTION............. ................................ ...........90
8.2 SPECIFIC PORT CONFIGURATIONS............................... ........90
8.3 PORT CONTROL REGISTERS.................. ....... .... ....... .........90
8.4 INPUT/OUTPUTBIT CONFIGURATION......................................91
8.5 ALTERNATE FUNCTION ARCHITECTURE........................ ...........95
8.5.1 Pin DeclaredasI/O.. .............. .................................95
8.5.2 Pin Declaredasan Alternate Input.....................................95
8.5.3 Pin Declaredasan Alternate Function Output............................95
8.6 I/O STATUS AFTER WFI, HALT AND RESET...................... ...........95 ON-CHIP PERIPHERALS........... ........... ................................96
9.1 TIMER/WATCHDOG (WDT)............. .............. ....................96
9.1.1 Introduction............ ........... ................................96
9.1.2 Functional Description................................... ...........97
9.1.3 Watchdog Timer Operation.......... .... ......................... ....98
9.1.4 WDT Interrupts .... ....... ....... .............. ................... 100
9.1.5 Register Description..... ........... ............................... 101
9.2 MULTIFUNCTION TIMER (MFT)........................ .... ............... 103
9.2.1 Introduction............ ........... ............................... 103
9.2.2 Functional Description................................... .......... 105
9.2.3 InputPin Assignment............. .............. ................... 108
9.2.4 OutputPin Assignment............................................. 112
9.2.5 Interrupt and DMA................ ................................ 114
9.2.6 Register Description..... ........... ............................... 116
9.3 STANDARD TIMER (STIM)............................................... 127
9.3.1 Introduction............ ........... ............................... 127
9.3.2 Functional Description................................... .......... 128
9.3.3 Interrupt Selection... ................................ .............. 129
9.3.4 Register Mapping....... ................................ .......... 129
9.3.5 Register Description..... ........... ............................... 130
9.4 SERIAL PERIPHERAL INTERFACE (SPI)......................... .......... 131
9.4.1 Introduction............ ........... ............................... 131
9.4.2 Device-Specific Options............................................ 131
9.4.3 Functional Description................................... .......... 132
9.4.4 Interrupt Structure... .............................................. 133
9.4.5 Working With Other Protocols....... .... ....... ..................... 134
9.4.6 I2C-bus Interface... .............................................. 134
9.4.7 S-Bus Interface................................ .... ............... 137
9.4.8 IM-bus Interface........................................ .......... 138
9.4.9 Register Description..... ........... ............................... 139
9.5 SERIAL COMMUNICATIONS INTERFACE (SCI).............................. 141
9.5.1 Introduction............ ........... ............................... 141
9.5.2 Functional Description................................... .......... 142
9.5.3 SCI Operating Modes.............................................. 143
9.5.4 Serial Frame Format............................................... 146
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Table of Contents
9.5.5 Clocks And Serial Transmission Rates. ................................ 149
9.5.6 SCI Initialization Procedure............... .... ...................... 149
9.5.7 Input Signals........................................... .......... 151
9.5.8 Output Signals............................................ ....... 151
9.5.9 Interrupts and DMA...................................... .......... 152
9.5.10 Register Description............................................... 155
9.6 EIGHT-CHANNEL ANALOGTO DIGITAL CONVERTER (A/D)................... 166
9.6.1 Introduction............ ........... ............................... 166
9.6.2 Functional Description................................... .......... 167
9.6.3 Interrupts.............................. .... ...................... 169
9.6.4 Register Description..... ........... ............................... 170 ELECTRICAL CHARACTERISTICS.... ....... .............. ................... 174 GENERAL INFORMATION .................. .............. ................... 188
11.1 PACKAGE MECHANICAL DATA................. .......................... 188
11.2 80-PIN PLASTIC QUAD FLAT PACKAGE.... ................................ 188
11.3 ORDERING INFORMATION............. .............. ................... 189

Partno	Mfg	Dc	Qty	Available	Descript
ST90T158M9LVQ1	ST	N/a	1480	avai	8/16-BIT MICROCONTROLLER (MCU) WITH 16 TO 64K ROM, OTP OR EPROM, 512 TO 2K RAM
ST90T158M9LVQ1		N/a	396	avai	8/16-BIT MICROCONTROLLER (MCU) WITH 16 TO 64K ROM, OTP OR EPROM, 512 TO 2K RAM