ST90R158Q6 ,8/16-BIT MICROCONTROLLER (MCU) WITH 16 TO 64K ROM, OTP OR EPROM, 512 TO 2K RAMTable of Contents4.2.1 Divide by Zero trap . 484.2.2 Segment Paging During Interrupt Routines ..
ST90T158M9LVQ1 ,8/16-BIT MICROCONTROLLER (MCU) WITH 16 TO 64K ROM, OTP OR EPROM, 512 TO 2K RAMGENERAL DESCRIPTION . . . . . . .... . ... .. .. . . .... .... .. . .... .. . .. .. . ... .. .. . . ..
ST90T158M9LVQ1 ,8/16-BIT MICROCONTROLLER (MCU) WITH 16 TO 64K ROM, OTP OR EPROM, 512 TO 2K RAMTable of Contents4.2.1 Divide by Zero trap .... .. . ... . .. .. .. . .. .. . ... .. .. .. . 484. ..
ST90T158M9Q6 ,8/16-BIT MICROCONTROLLER (MCU) WITH 16 TO 64K ROM, OTP OR EPROM, 512 TO 2K RAMST90158 - ST901358/16-BIT MCU FAMILY WITHUP TO 64K ROM/OTP/EPROM AND UP TO 2K RAM■ Register File ba ..
ST9150 ,Low-cost advanced HD decoding IC for TVapplications CPU (450 MHz)DSL/IP) worldwide. The ST-9150 is targeted at ■ 32-bit DDR1/DDR2 compatib ..
ST-9150-BUC ,Low-cost advanced HD decoding IC for TVapplications CPU, 32KI, 32KD caches:Target speed > 450 MHz delivering > 800DMIPs● Single 32-bit DDR ..
STRM6529 , OFF-LINE SWITCHING REGULATOR . WITH POWER MOSFET OUTPUT
STRM6529 , OFF-LINE SWITCHING REGULATOR . WITH POWER MOSFET OUTPUT
STRS5706 , STRS5706
STRS5706 , STRS5706
STRS5707 , OFF-LINE SWITCHING REGULATORS - WITH BIPOLAR SWITCHING TRANSISTOR
STRS5707 , OFF-LINE SWITCHING REGULATORS - WITH BIPOLAR SWITCHING TRANSISTOR
ST90R158Q6-ST90T158M9Q6
8/16-BIT MICROCONTROLLER (MCU) WITH 16 TO 64K ROM, OTP OR EPROM, 512 TO 2K RAM
/eiTir,'
ST90158 - ST90135
8/16-BIT MCU FAMILY WITH
UP TO 64K ROM/OTP/EPROM AND UP TO 2K RAM
Register File based 8/16 bit Core Architecture
with RUN, WFI, SLOW and HALT modes
Internal Memory:
- EPROM/OTP/ROM 24/32/48/64K bytes
- ROMIess version available
- RAM 768/1K/1.5K/2K bytes
Maximum External Memory: 64K bytes
224 general purpose registers available as
'gy accumulators or index pointers (register
67 fully programmable l/O bits
Fully Programmable PLL Clock Generator, with
Frequency Multiplication and low frequency,
low cost external crystal
Minimum 8-bit Instruction Cycle time: 83ns - (@
24 MHz internal clock frequency)
Minimum 16-bit Instruction Cycle time: 250ns -
(@ 24 MHz internal clock frequency)
8 external and 1 Non-Maskable Interrupts
DMA Controller and Programmable Interrupt
Handler
§ingle Master Serial Peripheral Interface with
I C capability
Two 16-bit Timers with 8-bit Prescaler, one
usable as a Watchdog Timer (software and
hardware)
Three (ST90158) or two (ST90135) 16-bit
Multifunction Timers, each with an 8 bit
prescaler, 12 operating modes and DMA
capabilities
8 channel 8-bit Analog to Digital Converter, with
Automatic voltage monitoring capabilities and
external reference inputs
PQFP80
Two (ST90158) or one (ST90135) Serial
Communication Interfaces with asynchronous,
synchronous and DMA capabilities
a Rich Instruction Set with 14 Addressing modes
I: Division-by-Zero trap generation
a Versatile IDE
(Integrated development
Environment) including Assembler, Linker, C-
compiler, Archiver, Source Level Debugger
Hardware tools; Real Time Emulator, EPROM
Programming Board
Gang Programmer and Real Time Operating
System available from Third parties
DEVICE SUMMARY
Features ST90135M5 ST90135M6 ST90158M7 ST90158M9 ST90R158 ST90T158
Program Memory 24K ROM 32K ROM 48K ROM 64K ROM ROMIess 64K OTP
RAM 768 1K 1.5K 2K 2K
Operating Supply 2.7V to 3.3V or 4.5V to 5.5V
CPU Frequency Up to 16MHz (for 2.7V to 3.3V) or Up to 24MHz (for 4.5V to 5.5V)
Watchdog Timer, Two Multifunc- Watchdog Timer, Three Multifunction Timers, Two SCI, One SPI,
Peripherals tion Timers, One SCI, One SPI, . .
ADC, 16-bit Timer ADC, 16-bit timer
Operating - o o
Temperature 40 C to 85 C
Packages TQFP8O (4.5V to 5.51/ and 2.7V to 3.3V) / PQFP80 (4.5V to 5.5V)
Rev. 3.3
January 2001 1/199
Table of Contents
1 GENERAL DESCRIPTION M..................................................... 6
1.1 INTRODUCTION _........................................................ 6
1.1.1 ST9 Core ......................................................... 6
1.1.2 Power Saving Modes ................................................ 6
1.1.3 System Clock _..................................................... 6
1.1.4 IIO Ports W......................................................... 6
1.1.5 Multifunction Timers (MFT) ............................................ 7
1.1.6 Standard Timer (STIM) ............................................... 7
1.1.7 Watchdog Timer (WDT) .............................................. 7
1.1.8 Serial Peripheral Interface (SPI) ........................................ 7
1.1.9 Serial Communications Controllers (SCI) ................................. 7
1.1.10 Analog/Digital Converter (ADC) ........................................ 7
1.2 PIN DESCRIPTION P..................................................... 10
1.3 IIO PORT PINS ......................................................... 13
2 DEVICE ARCHITECTURE ..................................................... 18
2.1 CORE ARCHITECTURE w................................................. 18
2.2 MEMORY SPACES ...................................................... 18
2.2.1 Register File _..................................................... 18
2.2.2 Register Addressing ................................................ 20
2.3 SYSTEM REGISTERS w................................................... 21
2.3.1 Central Interrupt Control Register ...................................... 21
2.3.2 Flag Register _.................................................... 22
2.3.3 Register Pointing Techniques ......................................... 23
2.3.4 Paged Registers ................................................... 26
2.3.5 Mode Register _................................................... 26
2.3.6 Stack Pointers _.................................................... 27
2.4 MEMORY ORGANIZATION ................................................ 29
2.5 MEMORY MANAGEMENT UNIT ............................................ 30
2.6 ADDRESS SPACE EXTENSION ............................................ 31
2.6.1 Addressing 16-Kbyte Pages .......................................... 31
2.6.2 Addressing 64-Kbyte Segments ....................................... 32
2.7 MMU REGISTERS w...................................................... 32
2.7.1 DPR[3:0]: Data Page Registers ....................................... 32
2.7.2 CSR: Code Segment Register ........................................ 34
2.7.3 ISR: Interrupt Segment Register ....................................... 34
2.7.4 DMASR: DMA Segment Register ...................................... 34
2.8 MMU USAGE w.......................................................... 36
2.8.1 Normal Program Execution ........................................... 36
2.8.2 Interrupts _........................................................ 36
2.8.3 DMA _........................................................... 36
3 REGISTER AND MEMORY MAP ................................................ 37
3.1 MEMORY CONFIGURATION .............................................. 37
3.2 EPROM PROGRAMMING ................................................. 37
3.3 MEMORY MAP ........................................................ . 39
3.4 ST90158/135 REGISTER MAP ............................................. 40
4 INTERRUPTS _.............................................................. 48
4.1 INTRODUCTION ........................................................ 48
4.2 INTERRUPT VECTORING w............................................... 48
2/199 dry
