ST7536CFN Fast Delivery |IC PHOENIX CO.,LIMITED

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ST7536CFN
POWER LINE MODEM
ST7536
POWER LINE MODEM
November 1998 HALF DUPLEX SYNCHRONOUS FSK MODEM TWO PROGRAMMABLE CHANNELS FOR
600BPS DATA RATE TWO PROGRAMMABLE CHANNELS FOR
1200BPSDATARATE. AUTOMATICALLYTUNEDRxANDTxFILTERS.TX CARRIER FREQUENCIES SYNTHESIZED
FROMEXTERNAL CRYSTAL. LOW DISTORTIONTx SIGNAL (S/H2≥ 50dB). AUTOMATIC LEVELCONTROLON TxSIGNAL.Rx SENSITIVITY: 2mVRMS (600bps)
3mVRMS (1200bps).Rx CLOCK RECOVERY. POWER-DOWN MODE. SUITABLETOAPPLICATIONIN ACCORDANCE
WITH DH028/29 ENEL, EN50065-1 CENELEC
ANDFCC SPECIFICA TIONS
DESCRIPTION
The ST7536isa half duplex synchronous FSK
MODEM designedfor power line communication
network applications. operatesfroma dualpowersupply +5V and -5V,
and requiresan external interfaceforthe couplingthe power line.It offerstwo programmable data
rate withtwo programmablechannels each.
PLCC28
(Plastic Leaded Chip Carrier Package)
ORDER CODE: ST7536CFN
Rx/Tx234 1927281314151617
VDDAV
DVDD
ATO
ALCI
TxFI
RxFO
RAI
AGND
DEMI
IFO
AFCF
BRSCHS
RESETTEST
TEST
TEST2
TEST1
CLR/T
RxD
RxDEM
DGND
TxD
XTAL
XTAL
PIN CONNECTIONS
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PIN DESCRIPTION
Pin
Number Name Type Description Rx/Tx Digital RxorTx mode selection input RESET Digital Logic resetand power-down mode input. Active whenlow. TEST4 Digital Test input which selectstheTx band-pass filter input (TxFI) when high. TEST3 Digital Test input which givesan accesstothe clock recovery input stage.This inputis selected
when TEST1is high. RxD Digital Synchronous receive data output CLR/T Digital RxorTx clock accordingtothe functional mode RxDEM Digital Demodulated data output DGND Supply Digital ground
9DVDD Supply Digital positive supply voltage:5V±5% TEST1 Digital Test input which cancelstheTxtoRx mode automatic switchingand validates TEST3
input. Active when high. TEST2 Digital Test input which reducestheTxtoRx mode automaticswitching time. Active when high. TxD Digital Transmit data input XTAL2 Digital Crystal oscillator output XTAL1 Digital Crystal oscillator input CHS Digital Channel selection input BRS Digital Baudrate selection input AFCF Analog Automatic frequency control outputfor connecting compensation network. DVSS Supply Digital negative supply voltage:-5V±5% IFO Analog Intermediate frequency filter output DEMI Analog FSK demodulator input AVSS Supply Analognegative supply voltage:-5V±5% AGND Supply Analogground:0V AVDD Supply Analogpositive supply voltage:5V ± 5% RAI Analog Receive analog input RxFO Analog Receive filter output TxFI Analog Transmitfilter input (selected when TEST4 ishigh) ALCI Analog Automatic level control input ATO Analog Analogtransmit output
ST7536
2/9
POST-DEMOS.C. FILTER CORRELATOR8 2327
TEST
LOGIC
REFERENCEVOLTAGE
CLOCKRECOVERY
FSK
MODULATOR
20dB
GAIN
AFC
ALC
TIME BASEANDCONTROLLOGIC 2
FSK DEMODULATOR
IFO
XTAL2
XTAL1
Rx/Tx
RESET
BRS
CHS
TxD
TxFI
DEMI
RAI
AFCF
ATO
ALCI
RxDEM
RxD
CLR/T
TEST1TEST2 TEST3TEST4
RxFO DGND AGNDDVDD AVSSDVSS BAND-PASS
S.C. FILTER
SMT.
FILTER
A.A.
FILTER I.F. BAND-PASS
S.C. FILTER
SMT.
FILTER
A.A.
FILTER
AVDD BAND-PASS
S.C. FILTER
A.A.
FILTER
A.A.
FILTER
MUX
MUX ST7536
BLOCK DIAGRAM
ST7536
3/9
FUNCTIONAL DESCRIPTION- Transmit Section
The transmit modeisset whenRx/Tx=0,if Rx/Tx heldat0 longerthan3s, thenthedevice switches
automaticallyintheRx mode.A new activationof
theTx mode requires Rx/Txtobe returnedto1for minimum2μs period before beingsetto0.
The Transmit Data (TxD)is sampledona positive
edgeof CLR/Twhich deliversthe transmitbit clock
whenthe transmit modeis selected. This data
entersa FSK modulatorwhosetwo basic frequen-
ciesare selectedbythe Baud Rate Selectionpin
(BRS) andthe Channel Selectionpin (CHS)ac-
cordingtothe Table1.
CLR/T
TxD DATA VALID
Figure1:Tx Data Input Timing
Table1
BRS CHS Baud Rate
(Baud) Frequencies (kHz)
TxD=1- TxD=0 0 600 81.75- 82.35 1 600 67.2-67.8 0 1200 71.4-72.6 1 1200 85.95- 87.15
These frequencies are synthesized froma
11.0592MHzcrystal oscillator; theirprecisionisthe
sameasthe crystal one’s (100 ppm).
Themodulatedsignal comingout oftheFSKmodu-
latoris filteredbya switched-capacitorband-pass
filter (Tx band-pass)in orderto limitthe output
spectrumandto reducethe levelof harmonic com-
ponents.
The output stageof theTx path consistsofan
AutomaticLevelControl(ALC)systemwhich keeps
the output signal (ATO) amplitude independantof
thelineimpedancevariations.ThisALCisa variable
gain system (with32 discrete values) controlledby
ananalogfeed-backsignal ALCI (see Figure2).
The ALC gain rangeis 0dBto -26dB and gain
changeis clockedat 7200Hz. Gain stepsareof
magnitude 0.84dBtypically. periodof this clockis decomposedintoa 34.7μs
gain settling latency anda 104.2μs peakdetecting
time. The gain changeis relatedtothe resultofa
peak detection obtainedby makinga direct com-
parisonof ALCI maximum value (during detecting
time)withtwo threshold voltagesVT1 andVT2 (see
Figure2). max (VALCI)< VT1- The next gainis increased 0.84dB,
-VT1≤ max(VALCI)≤VT2-No gain change,
-VT2< max(VALCI)- The next gainis decreased 0.84dB.
Amplitude
modification
duetoan
external cause
High Gain
Low Gain Correct Gain
Correct
Gain
latency
Gain
setting
Peak
detecting
time
VT2
VT1
ALCI SIGNAL ENVELOP
ALCCLOCK
4.E
Figure2: AutomaticLevel Control Timing Chart
ST7536
4/9
- Receive SectionThe receive sectionis active when Rx/Tx=1.
The baud rate and channel selectionis also made
accordingto Table1.
TheRx signalis appliedon RAI witha common
mode voltageof0V and filteredbya band-pass
switched capacitor filter (Rx band-pass) centered
onthereceivedcarrierfrequencyand whose band-
widthis around 6kHz. The input voltage rangeon
RAIis 2mVRMS -2VRMS.
TheRx filteroutputisamplifiedbya20dBgainstage
whichprovidessymmetricallimitationsforlarge volt-
age. The resulting signalis down-convertedbya
mixer which receivesa local oscillator synthesized theFSK modulatorblock.Finallyanintermediate
frequency band-pass filter(IF band-pass) whose
central frequencyis 2.7kHz when BRS=0 and
5.4kHzwhen BRS=1 improvesthe signalto noise
ratio before enteringthe FSK demodulator. The
couplingofthe intermediate frequencyfilter output
(IFO)tothe FSKdemodulatorinput(DEMI)ismade
byanexternalcapacitorC5 (1μF±10%,10V) which
cancelstheRx path offset voltage. clock recovery circuit extractsthe receive clock
(CLR/T) from the demodulated output (RxDEM)
and delivers synchronous data (RxD)onthe posi-
tive edgeof CLR/T.
FUNCTIONAL DESCRIPTION (continued)- Additional Digital and Analog Functions reset intput (RESET) initializesthe device.
When RESET=0, the deviceisin power-down
mode andall the internal logicis reset. When
RESET=1,the deviceis active. time base section deliversallthe internalclocks
froma crystal oscillator (11.0592MHz). The crystal connected betweenXTAL1 and XTAL2 pins and
needstwo external capacitorsC3 andC4 depend-
ing on the crystalchara cteristic typically
22pF ±10%for properoperation.Itis also possible provide directlythe clockonpin XTAL1;in this
caseC3 andC4 shouldbe removed. Automatic Frequency Control (AFC) Section
adjuststhe central frequencyofRx andTx band-
pass filterto the carrier central frequency. The
stabilityofthe AFC loopis ensuredbyan external
compensationnetworkC1 (470nF ±10%, 10V),C2
CLR/T
RxD DATA VALID
Figure3:Rx Data Output Timing
(47nF±10%, 10V) andR1 (1.5kΩ ±5%) connectedpin AFCF. C1
AFCF AGND
Figure4: Automatic Frequency Loop Filter- Testing FeaturesAn additionnalamplifierallowsthe observationof
theRx band-pass filter outputonpin RxFO.A direct inputtotheTx band-passfilter (TxFI)is
availableand selected when TEST4=1. The3 second normal durationoftheTxtoRx
mode automaticswitchingis reducedto 1.48ms
when TEST2=1. When TEST1=1theTxtoRx mode automatic
switchingis desactivatedandthe functionalmode thecircuitiscontrolledby Rx/Tx asfollow :when
Rx/Tx=0the circuitis transmitting continuously,
whenRx/Tx= 1the clock recoveryblockis discon-
nected from theFSK demodulatorfor testing pur-
pose,in thisconfigurationTEST3 isthe data inputthe clockrecoveryblock, RxDEM follow TEST3
andRxD delivers theresynchronized data.- Power Supplies Wiring and Decoupling
Precautions
The ST7536 has two positive power supply pins,
two negative power supply pins and two ground
pinsin order toseparate internal analog and digital
supplies. The analog and digital terminalsof each
supplypair mustbe connectedtogetherexternally
and require special routing precautionsin orderto
getthe best receive sensitivity performances.
The three major routing requirementsare: The ground impedance shouldbeas lowas
possible,for this purposethe AGNDan DGND
terminalscanbe connectedviaa local plane. The positive andnegativepower supplies (AVDD,
DVDD,AVSS,DVSS) shouldbe star-connected,
avoidingcommoncurrent pathforthe digital and
analog power supplies terminals. Five decoupling capacitors locatedas closeas
possibletothe powersupply terminalsshouldbe
used. Two 2.2μF tantalum and two 100nFce-
ramic capacitors performthe main decoupling
functioninthe vicinityofthe analog power sup-
pliesanda100nFceramiccapacitorin thevicinity the positive digital power supplyis usedto
reducethe high frequency perturbations gener-
atedbythe logic partofthe circuit.
ST7536
5/9
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
AVDD/DVDD Positive Supply Voltage(1) -0.3,+7 V
AVSS/DVSS Negative Supply Voltage(1) -7, +0.3 V
VAGND/DGND Voltage between AGNDand DGND -0.3, +0.3 V Digital Input Voltage DGND-0.3, DVDD+0.3 V Digital Output Voltage DGND-0.3, DVDD+0.3 V Digital Output Current -5,+5 mA Analog Input Voltage AVSS-0.3, AVDD+0.3 V Analog Output Voltage AVSS-0.3, AVDD+0.3 V Analog Output Current -5,+5 mA Power Dissipation 500 mW
Toper Operating Temperature -25,+70 oC
Tstg Storage Temperature -65,+150 oC
Notes:1.The voltagesare referencedto AGNDand DGND. Latch-up problemscanbe overcomewith2 reverse biased schottky diodes connectedrespectively between A/DVDD& A/DGND
andA/DVSS &A/DGND. Absolute maximum ratingsare values beyondwhich damage todevicemay occur. Functionaloperation under theseconditionsis
notimplied.
GENERAL ELECTRICAL CHARACTERISTICS
Thetest conditionsare A/DVDD= +5V, A/DVSS= -5V,A/DGND=0V,
Tamb=-10to70oC unless otherwisespecified
Symbol Parameter Test Conditions Min. Typ. Max. Unit
AVDD/DVDD Positive Supply Voltage 4.75 5 5.25 V
AVSS/DVSS Negative Supply Voltage -5.25 -5 -4.75 V
AIDD +DIDD Positive Supply CurrentinTx Mode RESET=1, RX/Tx=0 30 35 mA
AIDD +DIDD Positive Supply CurrentinRx Mode RESET=1, RX/Tx=1 29 34 mA
AISS +DISS Negative Supply CurrentinTx Mode RESET=1, RX/Tx=0 -34-29 mA
AISS +DISS Negative Supply CurrentinRx Mode RESET=1, RX/Tx=1 -33-28 mA
AIDD +DIDD Positive Power-down Current RESET=0, RX/Tx=1
XTAL1=1
1.2 mA
AISS +DISS Negative Power-down Current -1.2 mA
VIH High Level Input Voltage Digital inputs except XTAL1 2.2 V
VIL Low LevelInput Voltage Digital inputs 0.8 V
VOH High Level Output Voltage Digital outputs,IOH=- 400μA 2.4 V
VOL Low LevelOutput Voltage Digital outputs,IOL= 1.6mA 0.4 V
VIH High Level Input Voltage XTAL1input 3.6 V XTAL1Clock Duty Cycle External clock 40 60 %
ST7536
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Partno	Mfg	Dc	Qty	Available	Descript
ST7536CFN		N/a	7	avai	POWER LINE MODEM