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ST72T331J4T3S-ST72T331J4T6-ST72T331N2-ST72T331N2B6-ST72T331N4
8-BIT MICROCONTROLLER (MCU) WITH 8/16K ROM/OTP/EPROM,256 EEPROM,384/512 BYTES RAM,ADC,WDG,SCI,SPI & 2 TIMERS
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ST72E331
ST72T331
8-BIT MCU WITH 8 TO 16K OTP/EPROM, 256 EEPROM,
384 TO 512 BYTES RAM, ADC, WDG, SCI, SPI AND 2 TIMERS
a User Program Memory (OTP/EPROM):
8 to 16K bytes
a User EEPROM: 256 bytes
Data RAM: 384 to 512 bytes including 256 bytes
of stack
Master Reset and Power-On Reset
Low Voltage Detector (LVD) Reset option
Run and Power Saving modes
44 or 32 multifunctional bidirectional I/O lines:
- 15 or 9 programmable interrupt inputs
- 8 or 4 high sink outputs
- 8 or 6 analog alternate inputs
- 13 alternate functions
- EMI filtering
a Software or Hardware Watchdog (WDG)
a Two 16-bit Timers, each featuring:
- 2 Input Captures 1)
- 2 Output Compares 1)
- External Clock input (on Timer A)
- PWM and Pulse Generator modes
I: Synchronous Serial Peripheral Interface (SPI)
n Asynchronous Serial Communications Interface
a 8-bit ADC with 8 channels 2)
a 8-bit Data Manipulation
n 63 basic Instructions and 17 main Addressing
n 8 x 8 Unsigned Multiply Instruction
a True Bit Manipulation
a Complete Development Support on DOS/
WINDOWSTM Real-Time Emulator
a Full Software Package on DOS/WINDOWSTM
(C-Compiler, Cross-Assembler, Debugger)
Device Summary
DATASHEET
PSDIP42 CSDIP42W
TQFP64
TQFP44
(See ordering information at the end of datashe
Notes:
1. One only on Timer A.
2. Six channels only for ST72T331J.
Features ST72T331J2 ST72T331J4 ST72T331N2 ST72T331N4
Program Memory - bytes 8K 16K 8K 16K
EEPROM - bytes 256
RAM (stack) - bytes 384 (256) l 512 (256) I 384 (256) l 512 (256)
Peripherals
Watchdog, Timers, SPI, SCI, ADC and optional Low Voltage Detector Reset
Operating Supply
3 to 5.5V
CPU Frequency
8M Hz max (16MHz oscillator) - 4MHz max over 85°C
Temperature Range
- 40°C to + 125°C
Package TQFP44 - SDIP42
l TQFP64 - SDIP56
Note: The ROM versions are supported by the ST72334 family.
May 2001
Rev. 1.8
Table of Contents
ST72E331
ST72T331 ........................................... 1
1 GENERAL DESCRIPTION ...................................................... 5
1.1 INTRODUCTION ......................................................... 5
1.2 PIN DESCRIPTION ....................................................... 6
1.3 EXTERNAL CONNECTIONS ............................................... 10
1.4 MEMORY MAP _....................................................... . 11
1.5 OPTION BYTE w......................................................... 14
2 CENTRAL PROCESSING UNIT ................................................. 15
2.1 INTRODUCTION _....................................................... 15
2.2 MAIN FEATURES _...................................................... 15
2.3 CPU REGISTERS ....................................................... 15
3 CLOCKS, RESET, INTERRUPTS & POWER SAVING MODES ........................ 18
3.1 CLOCK SYSTEM ........................................................ 18
3.1.1 General Description _................................................ 18
3.1.2 External Clock _.................................................... 18
3.2 RESET _............................................................... 19
3.2.1 Introduction ....................................................... 19
3.2.2 External Reset _.................................................... 19
3.2.3 Reset Operation _................................................... 19
3.2.4 Low Voltage Detector Reset .......................................... 20
4 INTERRUPTS M.............................................................. 21
4.1 NON MASKABLE SOFTWARE INTERRUPT .................................. 21
4.2 EXTERNAL INTERRUPTS _............................................... 21
4.3 PERIPHERAL INTERRUPTS ............................................... 21
4.4 POWER SAVING MODES ................................................. 24
4.4.1 Introduction ....................................................... 24
4.4.2 Slow Mode w....................................................... 24
4.4.3 WaitMode _....................................................... 24
4.4.4 Halt Mode ......................................................... 25
4.5 MISCELLANEOUS REGISTER ............................................. 26
5 ON-CHIP PERIPHERALS ...................................................... 27
5.1 IIO PORTS ............................................................. 27
5.1.1 Introduction _...................................................... 27
5.1.2 Functional Description w.............................................. 27
5.1.3 l/O Port Implementation .............................................. 28
5.1.4 Register Description w................................................ 31
5.2 EEPROM (EEP) M........................................................ 33
5.2.1 Introduction ....................................................... 33
5.2.2 Main Features w.................................................... 33
5.2.3 Functional description ............................................... 34
5.2.4 Low Power Modes .................................................. 36
5.2.5 Interrupts P........................................................ 36
5.2.6 Register Description M................................................ 36
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