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ST72T121J2
8-BIT MICROCONTROLLER (MCU) WITH 8 TO 16 K ROM/OTP/EPROM, 384 TO 512 BYTES RAM, WDG, SCI, SPI & 2 TIMERS
tiT/r' ST72E121
's5rgir, ST72T121
8-BIT MCU WITH 8 TO 16K OTP/EPROM,
384 TO 512 BYTES RAM, WDG, SCI, SPI AND 2 TIMERS
DATASHEET
a User Program Memory (OTP/EPROM):
8 to 16K bytes
Data RAM: 384 to 512 bytes including 256 bytes
of stack
Master Reset and Power-On Reset A
Low Voltage Detector (LVD) Reset option
Run and Power Saving modes
32 multifunctional bidirectional l/O lines: PSDIP42
- 9 programmable interrupt inputs
- 4 high sink outputs
- 13 alternate functions
- EMI filtering
a Software or Hardware Watchdog (WDG)
a Two 16-bit Timers, each featuring:
- 2 Input Captures and 2 Output Compares 1)
- External Clock input (on Timer A)
- PWM and Pulse Generator modes CSDIP42W
n Synchronous Serial Peripheral Interface (SPI)
u Asynchronous Serial Communications Interface
a 8-bit Data Manipulation ye-ass''''''''),
I: 63 basic Instructions and 17 main Addressing
n 8 x 8 Unsigned Multiply Instruction
" True Bit Manipulation
a Complete Development Support on DOS/ TQFP44
WINDOWSTM Real-Time Emulator
'1 Full Software Package on DOS/WINDOWS", (See ordering information at the end of datasheet)
(C-Compiler, Cross-Assembler, Debugger)
Note: 1. One only of each on Timer A.
Device Summary
Features ST72T121J2 ST72T121J4
Program Memory - bytes 8K 16K
RAM (stack) - bytes 384 (256) 512 (256)
Peripherals Watchdog, Timers, SPI, SCI and optional Low Voltage Detector Reset
Operating Supply 3 to 5.5 V
CPU Frequency 8MHz max (16MHz oscillator) - 4MHz max over 85°C
Temperature Range - 40°C to + 125°C
Package TQFP44 - SDIP42
OTP/EPROM Devices ST72T121J4/ST72E121J4
Note: ROM versions are supported by the ST72334/124 family. Important product differences must be taken into account.
Refer to the Preamble in the ST72334/124 Datasheet for more information.
Revision 1.9
May 2001 1/93
Table of Contents
1 GENERAL DESCRIPTION M..................................................... 4
1.1 INTRODUCTION _........................................................ 4
1.2 PIN DESCRIPTION _...................................................... 5
1.3 EXTERNAL CONNECTIONS ................................................ 7
1.4 MEMORY MAP .......................................................... 8
1.5 OPTION BYTE .......................................................... 11
2 CENTRAL PROCESSING UNIT ................................................. 12
2.1 INTRODUCTION ........................................................ 12
2.2 MAIN FEATURES P...................................................... 12
2.3 CPU REGISTERS _...................................................... 12
3 CLOCKS, RESET, INTERRUPTS & POWER SAVING MODES ........................ 15
3.1 CLOCK SYSTEM _....................................................... 15
3.1.1 General Description ................................................. 15
3.1.2 External Clock ..................................................... 15
3.2 RESET P............................................................... 16
3.2.1 Introduction w...................................................... 16
3.2.2 External Reset ..................................................... 16
3.2.3 Reset Operation P................................................... 16
3.2.4 Low Voltage Detector Reset .......................................... 17
4 INTERRUPTS M.............................................................. 18
4.1 NON MASKABLE SOFTWARE INTERRUPT .................................. 18
4.2 EXTERNAL INTERRUPTS ................................................ 18
4.3 PERIPHERAL INTERRUPTS ............................................... 18
4.4 POWER SAVING MODES ................................................. 21
4.4.1 Introduction _...................................................... 21
4.4.2 Slow Mode w....................................................... 21
4.4.3 Wait Mode ........................................................ 21
4.4.4 Halt Mode _........................................................ 22
4.5 MISCELLANEOUS REGISTER ............................................. 23
5 ON-CHIP PERIPHERALS ...................................................... 24
5.1 l/O PORTS _............................................................ 24
5.1.1 Introduction _...................................................... 24
5.1.2 Functional Description w.............................................. 24
5.1.3 l/O Port Implementation .............................................. 25
5.1.4 Register Description ................................................. 28
5.2 WATCHDOG TIMER (WDG) ............................................... 30
5.2.1 Introduction _...................................................... 30
5.2.2 Main Features ..................................................... 30
5.2.3 Functional Description ............................................... 30
5.2.4 Hardware Watchdog Option _.......................................... 31
5.2.5 Low Power Modes _................................................. 31
5.2.6 Interrupts ......................................................... 31
5.2.7 Register Description w................................................ 31
5.3 16-BIT TIMER w......................................................... 33
5.3.1 Introduction ....................................................... 33
2/93 dry
