ST72681/R21 ,USB 2.0 HIGH-SPEED 8-BIT MCU FLASH DRIVE CONTROLLERFeaturesST72681/R20 ST72681/R21USB interface USB 2.0 high speed(1)Number of NAND Flash devices supp ..
ST72681R21 ,USB 2.0 HIGH-SPEED 8-BIT MCU FLASH DRIVE CONTROLLERFeatures■ USB 2.0 interface compatible with mass storage device class– Integrated USB 2.0 PHY suppo ..
ST7271 ,8-BIT HCMOS MCUs WITH EEPROM AND TV/MONITOR DEDICATED FUNCTIONSI " SGS-THOMSON
'A, (tiMa0yhlaE(MTty2(0iilllWi) ST7271
8-BIT HCMOS MCUs WITH EEPROM
AND TV/MON ..
ST7271 ,8-BIT HCMOS MCUs WITH EEPROM AND TV/MONITOR DEDICATED FUNCTIONSapplications.
It is based around an industry standard 8-bit core
and offers an enhanced instruc ..
ST72C104G1B6 ,8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI,Table of Contents10.2.3Alternate Functions . 3010.3 I/O PORT IMPLEMENTATION . . . . 33 ..
ST72C104G1M6 ,8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI,Functional Description . . . . . . . 4212.2.4Low Power Modes . 5412.2.5Interrupts ..
STPS2L40UF ,Low Drop Power Schottky Rectifierapplications.T (max) 150 °Cj V (max) 0.34 VFSeptember 2008 Rev 4 1/10www.st.com 10Characteristics ..
STPS2L60 ,POWER SCHOTTKY RECTIFIERFEATURES AND BENEFITSn NEGLIGIBLE SWITCHING LOSSESn LOW FORWARD VOLTAGE DROPDESCRIPTIONAxial and Su ..
STPS30100ST ,Power Schottky Rectifierapplications a good efficiency at both low and high load. Table 1. Absolute Ratings (limiti ..
STPS30120CT ,Power Schottky rectifierElectrical characteristics STPS30120CTNIV "Forward"ITable 1. Device summary2 x I XOSymbol V ..
STPS30120CT. ,Power Schottky rectifierFeaturesA1K■ High junction temperature capabilityA2■ Avalanche ratedKK■ Low leakage current■ Good t ..
STPS30150CT ,HIGH VOLTAGE POWER SCHOTTKY RECTIFIERFEATURES AND BENEFITSn High junction temperature capabilityn Good trade off between leakage current ..
ST72681/R21-ST72681R21
USB 2.0 HIGH-SPEED 8-BIT MCU FLASH DRIVE CONTROLLER
Not For New DesignFebruary 2009 Rev 6 1/34
ST72681USB 2.0 high-speed Flash drive controller
Features USB 2.0 interface compatible with mass
storage device class Integrated USB 2.0 PHY supporting USB
high speed and full speed Suspend and Resume operations Mass storage controller interface (MSCI) Supports 2 KB-page NAND Flash devices
including Numonyx, Hynix, Samsung,
Toshiba, Micron, Renesas Reed-Solomon encoder/decoder on-the-fly
correction (4 bytes of a 512-byte block) Flash identification support Up to 12 MB/s for read and 8 MB/s for write
operations in single channel Up to 4 NAND Flash supported per channel Embedded ST7 8-bit MCU Supply management 3.3 V operation Integrated 3.3-1.8 V voltage regulator USB 2.0 low-power device compliant Less than 100 mA during write operation
with two NAND Flash devices Less than 500 µA in suspend mode AutoRun CDROM partition support Bootability support (HDD mode) Clock management Integrated PLL for generating core+USB
2.0 clocks from external 12 MHz crystal Data protection Write protect switch control Public/private partitions support Production tool device configurability: USB vendor ID/product ID (VID/PID), serial
number and USB strings with foreign
language support
–SCSI strings One or two LED outputs Adjustable NAND Flash bus frequency to
reach highest performance Code update in the NAND Flash memory LQFP48 7x7 ECOPACK® package Development support Complete reference design including
schematics, BOM and Gerber files Supports Windows (Vista, XP, 2000, ME),
Linux and MacOS. Drivers available for
Windows 98 SE
Table 1. Device summary Number of NAND Flash devices supported in a single channel.
Contents ST726812/34
Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 NAND Flash interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104.1 NAND Flash support table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2 NAND error correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2.1 Hardware error correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2.2 Firmware error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3 Management of bad NAND Flash blocks . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3.1 Bad block identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3.2 Bad block replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3.3 Late fail block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4 Wear levelling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4.1 LUT usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.5 NAND Flash interface configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Mass storage implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145.1 USB characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2 BOT / SCSI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2.1 BOT specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2.2 SCSI specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2.3 Bootability specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.3 Multi-LUN device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.3.1 Public drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3.2 Private drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3.3 Additional drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3.4 CD-ROM considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.4 Mass storage interface configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Human interface implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166.1 LED behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.2 Read only switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
ST72681 Contents
3/34
7.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.2.1 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.2.2 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.2.3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.4.1 RUN and SUSPEND modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.4.2 Supply and clock managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.5 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.5.1 General timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.5.2 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.6 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.6.1 Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . . 22
7.6.2 Electromagnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.6.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 23
7.7 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.7.1 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.7.2 Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.8 Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.8.1 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.9 Other communication interface characteristics . . . . . . . . . . . . . . . . . . . . 28
7.9.1 MSCI parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.9.2 Universal serial bus interface (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Introduction ST72681
4/34
1 Introduction
The ST72681 is a USB 2.0 high-speed Flash drive controller. The USB 2.0 high-speed
interface including PHY and function supports USB 2.0 mass storage device class.
The mass storage controller interface (MSCI) combined with the Reed-Solomon
encoder/decoder on-the-fly correction (4-byte on 512-byte data blocks) provides a flexible,
high transfer rate solution for interfacing a wide of range NAND Flash memory device types.
The internal 60 MHz PLL driven by the 12 MHz oscillator is used to generate the 480 MHz
frequency for the USB 2.0 PHY.
The ST7 8-bit CPU runs the application program from the internal ROM and RAM. USB data
and patch code are stored in internal RAM.
I/O ports provide functions for EEPROM connection, LEDs and write protect switch control.
The internal 3.3 to 1.8 V voltage regulator provides the 1.8 V supply voltage to the digital
part of the circuit.
Figure 1. Device block diagram
ST72681 Pin description
5/34
2 Pin description
Figure 2 shows the LQFP48 package pinout, while Table 2, Table 3, Table 4, and Table 5
give the pin description.
The legend and abbreviations used in these tables are the following: Type I = input O = output S = supply Input level: A = Dedicated analog input In/Output level
–CT = CMOS 0.3VDD/0.7VDD with input trigger
–TT= TTL 0.8V / 2 V with Schmitt trigger Output level D8 = 8mA drive D4 = 4mA drive D2 = 2mA drive
Figure 2. 48-pin LQFP package pinout Must remain NOT connected in the application.
Pin description ST72681
6/34
Table 2. Power supply
Table 3. USB 2.0 interface
Table 4. USB 2.0 and core clock system
ST72681 Pin description
7/34
Table 5. General purpose I/O ports /mass storage I/Os
Application schematics ST72681
3 Application schematics
ST72681/R20 only supports single NAND Flash Chip Enable configuration (one NAND
Flash device with one Chip Enable signal). Note that pins NAND_RnB2, NAND_CE2,
NAND_CE3 and NAND_CE4 should remain unconnected.
ST72681 Application schematics
9/34
ST72681/R21 can support up to four NAND Flash Chip Enable signals. The application can
use one of the following configurations: One NAND Flash device with four Chip Enable signals; NAND_CE1, NAND_CE2,
NAND_CE3 and NAND_CE4 are used. One NAND Flash device with two Chip Enable signals; NAND_CE1 and NAND_CE2
are used. One NAND Flash device with one Chip Enable signal; only NAND_CE1 is used. Two NAND Flash devices with two Chip Enable signals; NAND_CE1 and NAND_CE2
are used to select the first NAND Flash device and NAND_CE3 and NAND_CE4 to
select the second NAND Flash device. Two NAND Flash devices with one Chip Enable signal; NAND_CE1 and NAND_CE2
are used to select is used to select the first NAND Flash device and the 2nd NAND
Flash device, respectively. 4 NAND Flash devices with 1Chip Enable signal; NAND_CE1 selects the first NAND
Flash device, NAND_CE2 the 2nd NAND Flash device, NAND_CE3 to select the third,
and NAND_CE4 to select the fourth NAND Flash device.
NAND Flash interface ST72681
10/34 NAND Flash interface
4.1 NAND Flash support table
Table 6. Known NAND Flash compatibility guide for R20 and R21 devices (1)(2) This list is provided as a guide only as it is not possible to automatically guarantee support for all the
additions and updates across the listed ranges of manufacturers’ devices. Only NAND Flash devices with 2 Kbyte pages are supported.
ST72681 NAND Flash interface
11/34
4.2 NAND error correction
No NAND Flash memory arrays are guaranteed by manufacturers to be error-free. Error
occurrence depends on the Flash cell type (MLC or SLC).
The ST72681 embeds hardware and firmware mechanisms to correct the errors.
4.2.1 Hardware error correction
The ST72681 embeds a Reed-Solomon algorithm-based hardware cell. This cell directly
manages 512-byte data packets on the NAND Flash I/O system.
Based on a data packet contents, the cell generates an 80-bit Error Correction Code (ECC)
consisting of 8 words each containing 10 bits.
During write operations to NAND memory, the 512-bytes of data and the ECC are stored
together in the same page. The ECC is stored in the corresponding Redundant Area (RA),
using 10 bytes.
During read operations, the 512-bytes of data and the 8 ECC words are read back and are
passed through the Reed-Solomon cell for decoding. The cell allows the correction of 4
symbols in this 520-symbol packet (512 symbols from data + 8 symbols from ECC).
The hardware cell gives 3 possible results: No error detected: the data packet can be used as it is. Correctable error detected: the corrected data are available in a specific 512-byte buffer
in the Reed-Solomon cell and are ready to use. Uncorrectable error detected: data corruption is not repairable.
4.2.2 Firmware error management
The firmware defines the error correction possibilities with the corrected data packet.
When data is not repairable, the block is considered as bad and replaced by another one.
See below for further information.
4.3 Management of bad NAND Flash blocks
NAND Flash device manufacturers deliver their products with factory-marked bad blocks.
This marking depends on the manufacturer and the NAND Flash type (page size, memory
technology, etc.). The ST72681 supports all bad block markings currently available on the
market.
4.3.1 Bad block identification
During firmware initialization, the MCU scans the entire NAND Flash configuration to
identify bad blocks.
A bad block is defined as follows: 5 different Block Status bytes are considered: 4 Status bytes from page 0 and 1 from an
other page (page 127 for MLC NAND Flash memory; page 1 for SLC NAND Flash
memory). The considered block is declared bad if 1 of these 5 bytes contains 4 bits or more at 0.
NAND Flash interface ST72681
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4.3.2 Bad block replacement
The firmware works with groups of 1024 blocks, called zones. A complete NAND Flash
configuration can contain several zones.
Each zone is described in a Look Up T able (LUT) containing 1024 entries. A LUT is
composed of 3 parts: used blocks, free blocks and bad blocks. The “bad blocks” part contains as many entries as the number of bad blocks identified
in that zone. The “used blocks” part can have a size of 1000, 900 or 500 entries. This size is
configurable and also depends on the number of identified bad blocks. The “free blocks” part contains the remaining entries.
The used blocks part is used to do a correspondence between NAND Flash blocks and
logical address ranges.
This system allows all bad blocks to be masked from the Host. As a result, bad blocks are
never seen. Only a range of logical addresses are visible which correspond to the sum of
the used blocks part of all zones.
4.3.3 Late fail block
During normal application life, defects can appear in the NAND Flash memory. Under
certain conditions, these defects are not correctable and the corresponding block is
declared as “bad”.
In this case, new bad blocks are identified in the bad blocks part of the LUT and replaced by
new blocks from the “free blocks” part.
4.4 Wear levelling
During normal application life, the NAND Flash memories written and erased (by block)
many times. The NAND Flash device is guaranteed for a limited number of writes (about 100
000 cycles). As a consequence, the controller must keep write/erase operations to a
minimum for any individual block.
A method to limit these cycles is to use a “Wear Levelling” scheme between all NAND Flash
memory blocks.
4.4.1 LUT usage
The LUT is used for transfers between a logical address range and a block. It contains free
blocks which are used in the “wear levelling” scheme.
During write command treatment, the firmware calculates the zones, blocks and pages for
data write access. In a block write operation, the firmware applies the following scheme to
avoid block wearing: The least recently-used block is chosen from the free block part of the LUT. Valid data from the old block is copied to the new block. New data from the write command is written to the new block. The old block is erased. The LUT is updated after identifying the new block in the used block part and the old
block in the free block part.
ST72681 NAND Flash interface
13/34
Using this scheme, a logical address range doesn’t correspond to a constant block. A write
command repeated several times to the same logical address writes physically into different
blocks.
This method shares the wearing evenly across all blocks of the concerned zone.
4.5 NAND Flash interface configuration
Applications based on ST72681 can be configured through a dedicated PC software tool.
The NAND Flash RE and WE signals frequencies can be independently configured to 30
MHz, 20 MHz, 15 MHz, 12 MHz and 10 MHz.
The logical size reduction factor can be configured to 90% or 50% in the event of having too
many bad blocks. this option resizes the used blocks part of the LUT to 900 or 500.
Mass storage implementation ST72681
14/34 Mass storage implementation
5.1 USB characteristics
The ST72681 is compliant with USB 2.0 specification.
It is able to operate in both high speed and full speed modes using a bidirectional control
endpoint 0 and a bidirectional bulk endpoint 2.
It automatically recognizes the speed to use on the bus by a process of negotiation with
USB Host.
5.2 BOT / SCSI implementation
5.2.1 BOT specification
The USB Mass Storage Class Bulk Only Transport (BOT) specification version 1.0 is
implemented. It allows the device to be recognized by the host as a mass-storage USB
device.
5.2.2 SCSI specification
Moreover, inside BOT transfers, SCSI commands are encapsulated for mass storage
operations.
The related specifications are SBC-2 revision 10 (SCSI Block Commands 2) and SPC-4
revision 7a (SCSI Primary Commands 4).
5.2.3 Bootability specification
The USB Mass Storage Specification for Bootability revision 1.0 is implemented.
It allows the PC host to boot the operating system from the USB mass storage application.
In this case, the Host uses BOT LUN 0 (logical unit number).
A specific tool must be used to format the logical drive in order to make it bootable by
programming the correct information.
5.3 Multi-LUN device characteristics
The application can be configured with a dedicated PC software tool as a multi-LUN device.
In this case, up to 3 different drives are available: public drive, additional drive and private
drive.
Public and additional drives can be configured as removable drive, hard disk drive or CD-
ROM drive.
ST72681 Mass storage implementation
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5.3.1 Public drive
The public drive is the default configuration in a mono-LUN mode. In this default case, it is
declared as a removable drive.
The public drive is mandatory and can not be removed from the configuration. By
customization (using PC software), it can be declared as a removable drive, a CD-ROM
drive or a hard disk drive.
This drive is the LUN 0 in BOT commands.
5.3.2 Private drive
The Private drive is optional. Its type is “removable drive” and is not configurable.
This drive is protected by password and cannot be directly accessed through the PC
operating system. A PC software tool is necessary to send a command with the password to
unlock the device. The device is then open and accessible by the PC operating system until
reset or reception of a new command to lock the drive.
This drive is the LUN 1 in BOT commands.
5.3.3 Additional drive
The additional drive is optional. Its type can be “removable drive”, “hard disk drive” or “CD-
ROM drive”.
This drive is LUN 1 in BOT commands if the private drive option is not active, and is LUN 2 if
the private drive option is active.
5.3.4 CD-ROM considerations
When a drive is declared as CD-ROM, the ST72681/R21 manages this drive with a logical
block size of 2 Kbytes. To be correctly recognized by the host, it is preferable to build a
CDFS partition on this CD-ROM. See the ‘ST7268x Production Tool User Manual’ for more
information.
Note that the ST72681/R20 doesn’t consider the CD-ROM partition as a specific case. The
logical block size is 512 bytes and any file system can be used.
In both cases, the CD-ROM partition allows the use of the AutoRun operating system
feature. During device connection, the CD-ROM partition is recognized and the host tries to
run the application corresponding to the ‘autorun.inf’ file present into this CD-ROM partition.
5.4 Mass storage interface configuration
In addition to the parameters already described as configurable in the previous chapters,
additional customizable information includes: USB parameters: VID, PID, all string information SCSI parameters: strings for inquiry commands
Human interface implementation ST72681
16/34 Human interface implementation
6.1 LED behavior
The application is designed to manage 2 LEDs. This behavior is configurable through PC
dedicated software: ‘ST7268x Production Tool’.
By default, LED 1 responds to NAND Flash memory access activity and LED 2 responds to
USB activity.
Use of LED 1 is optional. When this option is not active, LED 2 reacts to both USB and
NAND Flash activity.
6.2 Read only switch
The READ ONL Y pin of the ST72681 is an input pin to be connected to VDD or GND
depending on the behavior of the device. When this pin is connected to GND, no limitations are applied on the PC command
received. When this pin is connected to VDD or unconnected, the firmware filters all accesses to
the NAND Flash which modify the NAND Flash state (write, erase, etc.) and returns an
error to the PC.
ST72681 Electrical characteristics
17/34
7 Electrical characteristics
7.1 Parameter conditions
Unless otherwise specified, all voltages are referred to VSS.
7.1.1 Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the Devices with an ambient temperature at TA = 25 °C and TA=TA max (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3Σ).
7.1.2 Typical values
Unless otherwise specified, typical data are based on TA = 25 °C and VDD33 = 3.3 V. They
are given only as design guidelines and are not tested.
7.1.3 Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
7.1.4 Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 4.
Figure 4. Pin loading conditions
