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Partno	Mfg	Dc	Qty	Available	Descript
ST62T40B	ST	N/a	437	avai	8-BIT OTP/EPROM MCU WITH LCD DRIVER, EEPROM AND A/D CONVERTER
ST62T40B	STM	N/a	6	avai	8-BIT OTP/EPROM MCU WITH LCD DRIVER, EEPROM AND A/D CONVERTER

ST62T40B ,8-BIT OTP/EPROM MCU WITH LCD DRIVER, EEPROM AND A/D CONVERTERGENERAL DESCRIPTION . . . . . . .... . ... .. .. . . .... .... .. . .... .. . .. .. . ... .. .. . . ..
ST62T40B ,8-BIT OTP/EPROM MCU WITH LCD DRIVER, EEPROM AND A/D CONVERTERTable of ContentsDocumentPage4.1.3 LCD alternate functions (combiports) . ........ .. .. .. . .. .. ..
ST62T42B ,8-BIT OTP/EPROM MCU WITH LCD DRIVER, EEPROM AND A/D CONVERTERGENERAL DESCRIPTION . . . . . . .... . ... .. .. . . .... .... .. . .... .. . .. .. . ... .. .. . . ..
ST62T42BQ6 ,8-BIT MICROCONTROLLER ( MCU ) WITH OTP, ROM, FASTROM, EPROM, LCD DRIVER, EEPROM, A/D CONVERTER AND 64 PINSGENERAL DESCRIPTION . . . . . . 51.1 INTRODUCTION . 51.2 PIN DESCRIPTIONS . . ..
ST62T46B ,8-BIT OTP/EPROM MCU WITH LCD DRIVER / EEPROM AND A/D CONVERTERGENERAL DESCRIPTION . . . . . . .... ........51.1 INTRODUCTION ....... .. . ..51.2 PIN DESCRIPTIONS ..
ST62T46BB6 ,8-BIT MICROCONTROLLER ( MCU ) WITH OTP, ROM, FASTROM, EPROM, LCD DRIVER, EEPROM, A/D CONVERTER AND 56 PINS
STP55NF03L ,N-CHANNEL 30V
STP55NF06FP ,N-CHANNEL 60V 0.017 OHM 50A TO-220/TO-220FP/I2PAK STRIPFET II POWER MOSFET
STP55NF06FP ,N-CHANNEL 60V 0.017 OHM 50A TO-220/TO-220FP/I2PAK STRIPFET II POWER MOSFET
STP5N30L ,OLD PRODUCT: NOT SUITABLE FOR NEW DESIGN-INSTP5N30LSTP5N30LFIN - CHANNEL ENHANCEMENT MODEPOWER MOS TRANSISTORTYPE V R IDSS DS(on) DSTP5N30L 30 ..
STP5N90 ,N-CHANNEL ENHANCEMENT MODE POWER MOS TRANSISTORABSOLUTE MAXIMUM RATINGS I_Symbol Parameter T Value Cunit" L., - .0 STPSNQO l STP5N90FI " '_VD ..
STP5NA50 ,Trans MOSFET N-CH 500V 5A 3-Pin(3+Tab) TO-220STP5NA50STP5NA50FIN - CHANNEL ENHANCEMENT MODEFAST POWER MOS TRANSISTORTYPE V R IDSS DS(on) DSTP5NA ..

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ST62T40B
8-BIT OTP/EPROM MCU WITH LCD DRIVER, EEPROM AND A/D CONVERTER
August 1999 1/72
Rev. 2.6
ST62T40B/E40B
8-BIT OTP/EPROM MCU WITH LCD DRIVER,
EEPROM AND A/D CONVERTER 3.0to 6.0V Supply Operating Range 8 MHz Maximum Clock Frequency -40to +85°C Operating Temperature Range Run, Wait and Stop Modes 5 Interrupt Vectors Look-up Table capabilityin Program Memory Data Storagein Program Memory:
User selectable size Data RAM: 192 bytes Data EEPROM: 128 bytes User Programmable Options 24 I/O pins, fully programmable as: Input with pull-up resistor Input without pull-up resistor Input with interrupt generation Open-drainor push-pull output Analog Input LCD segments(8 combiport lines) 4 I/O lines can sinkupto 20mAto drive LEDsor
TRIACs directly Two 8-bit Timer/Counter with 7-bit
programmable prescaler Digital Watchdog 8-bit A/D Converter with12 analog inputs 8-bit Synchronous Peripheral Interface (SPI) LCD driver with 45 segment outputs, 4
backplane outputs and selectable multiplexing
ratio. 32kHz oscillator for stand-by LCD operation Power Supply Supervisor (PSS) On-chip Clock oscillator canbe drivenby Quartz
Crystalor Ceramic resonator One external Non-Maskable Interrupt ST6240-EMU2 Emulation and Development
System (connects to an MS-DOS PC viaa
parallel port).
DEVICE SUMMARY
(See endof Datasheetfor Ordering Information)
PQFP80
CQFP80W
DEVICE OTP
(Bytes)
EPROM
(Bytes) I/O Pins
ST62T40B 7948 - 16to24
ST62E40B 7948 16to24
2/72
Table of Contents
Document
Page
ST62T40B/E40B . .......... ..... .... ....... ..... .....1 GENERAL DESCRIPTION...... ..... ......... .... ....... ............ ...........5
1.1 INTRODUCTION............. ...... ..... .............. ....... ...... ......5
1.2 PIN DESCRIPTIONS...... ..... ......... .... ................... ...... .....7
1.3 MEMORY MAP.......... ..... ... ...... .... ................... ...... .....8
1.3.1 Introduction... ....................... ... ............. ..............8
1.3.2 Program Space.................... .... .... ................... ......8
1.3.3 Data Space............................ .... .... .... ....... ........ 10
1.3.4 Stack Space............ ...... ..... .............. ....... ...... ..... 10
1.3.5 Data Window Register (DWR).... ......... .... ................... ..... 11
1.3.6 Data RAM/EEPROM Bank Register (DRBR).............................. 12
1.3.7 EEPROM Description.................... ....... .... ................ 13
1.4 PROGRAMMING MODES................................................. 15
1.4.1 Option Byte... ....................... ... ............... ........... 15
1.4.2 Program Memory... ....... ....... ..... ......... ....... ............. 15
1.4.3 EEPROM Data Memory................... ....... ..... ....... ........ 15
1.4.4 EPROM Erasing ....................... ... ............... ........... 15 CENTRAL PROCESSING UNIT.. ..... ......... .... ....... ............ .......... 16
2.1 INTRODUCTION............. ...... ..... .............. ....... ...... ..... 16
2.2 CPU REGISTERS... ....................... ... ............. ............. 16 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES.. .... ............... 18
3.1 CLOCK SYSTEM............. ...... ..... .............. ....... ...... ..... 18
3.1.1 Main Oscillator.................... ....... ................ ... ....... 18
3.1.2 32 KHz STAND-BY OSCILLATOR..................................... 19
3.2 RESETS............................................................... 20
3.2.1 RESET Input.. .................. ..... ... ............. ............. 20
3.2.2 Power-on Reset .... .............. ..... ................ ............. 20
3.2.3 Watchdog Reset.................. ....... ................ ... ....... 21
3.2.4 Application Notes... .............. ..... .......... .... .... ........... 21
3.2.5 MCU Initialization Sequence........... ............ .... ...... ......... 21
3.3 DIGITAL WATCHDOG.................. ..... ......... ....... ............. 23
3.3.1 Digital Watchdog Register (DWDR)..................................... 25
3.3.2 Application Notes... .............. ..... .......... .... .... ........... 25
3.4 INTERRUPTS.......................................................... 27
3.4.1 Interrupt request. ........................... ............ ....... ..... 27
3.4.2 Interrupt Procedure................ ....... ................ ... ....... 28
3.4.3 Interrupt Option Register (IOR)......................... ..... ....... ... 29
3.4.4 Interrupt sources.............. ............ ....... ............. ..... 29
3.5 POWER SAVING MODES......................................... ..... ... 31
3.5.1 WAIT Mode .... .... ....... ...... ..... ......... .................... 31
3.5.2 STOP Mode........ ..... ......... .... ....... ............ ...... .... 31
3.5.3 Exit from WAIT and STOP Modes....... ............ .... .... ........... 32 ON-CHIP PERIPHERALS........... ...... ..... .... ....................... ..... 33
4.1 I/O PORTS.................. ...... ..... .............. ....... ...... ..... 33
4.1.1 Operating Modes........................ ....... .... ....... ......... 34
4.1.2 Safe I/O State Switching Sequence..................................... 35
3/72
Table of Contents Document
Page
4.1.3 LCD alternate functions (combiports).... ............ .... ............... 37
4.1.4 SPI alternate functions....................................... ..... ... 37
4.1.5 I/O Port Option Registers........... ..... ................ ......... .... 38
4.1.6 I/O Port Data Direction Registers....................................... 38
4.1.7 I/O Port Data Registers......... ............ ....... ............. ..... 38
4.2 TIMER1&2........................... ....... ................ ... ....... 39
4.2.1 TIMER1 Operating Modes...... ............ ....... ...... ....... ..... 41
4.2.2 TIMER2 Operating Mode........... .... ................... ...... .... 41
4.2.3 Timer Interrupt..................... .... ....................... ..... 41
4.2.4 Application Notes... .............. ..... .......... .... .... ........... 41
4.2.5 TIMER1 Registers............. ..... ....... ....... ....... ...... ..... 42
4.2.6 TIMER2 Registers............. ..... ....... ....... ....... ...... ..... 43
4.3 A/D CONVERTER (ADC).. ..... ......... .... ....... ............ .......... 44
4.3.1 Application Notes... .............. ..... .......... .... .... ........... 44
4.4 SERIAL PERIPHERAL INTERFACE (SPI)......................... ...... ..... 46
4.5 LCD CONTROLLER-DRIVER......... ..... ....... ....... ....... ...... ..... 48
4.5.1 Multiplexing ratio and frame frequency setting......... .... ...... ......... 49
4.5.2 Segment and commonplates driving.................................... 49
4.5.3 LCD RAM..... .................. ..... ................ ......... .... 50
4.5.4 Standbyor STOP operation mode...................... ..... ....... ... 51
4.5.5 LCD Mode Control Register (LCDCR) ....... ................ ... ....... 51
4.6 POWERSUPPLY SUPERVISOR DEVICE (PSS)............................... 52
4.6.1 PSS Operating Mode Description................................. ..... 53
4.6.2 PSS Register....... ..... ......... .... ................... ...... .... 54 SOFTWARE................. ..... ....... ... .... ....... ....... .... ....... ... 55
5.1 ST6 ARCHITECTURE. ........................... ............ ....... ..... 55
5.2 ADDRESSING MODES.................... ............ .... ............... 55
5.3 INSTRUCTION SET....... ..... ......... ..... ....... ........... ....... ... 56 ELECTRICAL CHARACTERISTICS................... .... .... ........... ........ 61
6.1 ABSOLUTE MAXIMUM RATINGS...... ..... .............. ....... ...... ..... 61
6.2 RECOMMENDED OPERATING CONDITIONS...... .... .... ........... ........ 62
6.3 DC ELECTRICAL CHARACTERISTICS........................... ...... ..... 63
6.4 AC ELECTRICAL CHARACTERISTICS...................................... 64
6.5 A/D CONVERTER CHARACTERISTICS...................................... 64
6.6 TIMER CHARACTERISTICS.... ...... ..... .... ....................... ..... 65
6.7 SPI CHARACTERISTICS.. ..... ... ...... ....................... ...... .... 65
6.8 LCD ELECTRICAL CHARACTERISTICS...................... ..... ....... ... 65
6.9 PSS ELECTRICAL CHARACTERISTICS (WHEN AVAILABLE). .... ............... 65 GENERAL INFORMATION.......... ...... ..... .............. ....... ...... ..... 66
7.1 PACKAGE MECHANICAL DATA................. ........ .... ....... ........ 66
7.2 PACKAGE THERMAL CHARACTERISTIC......................... ...... ..... 67
7.3 .ORDERING INFORMATION.... ...... ..... .... ....................... ..... 67
4/72
Table of Contents
Document
Page
ST6240B ..... ........ ............ ...... ....... ..... 69 GENERAL DESCRIPTION...... ..... ......... .... ....... ............ .......... 70
1.1 INTRODUCTION............. ...... ..... .............. ....... ...... ..... 70
1.2 ROM READOUT PROTECTION............ .... ....................... ..... 70
1.3 ORDERING INFORMATION............. ..... ......... .................... 72
1.3.1 Transferof Customer Code.......... ....... ................ ... ....... 72
1.3.2 Listing Generation and Verification.... ....... ................ ... ....... 72
5/72
ST62T40B/E40B GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST62T40B and ST62E40B devices are low
cost membersof the ST62xx 8-bit HCMOS family microcontrollers, which are targetedat lowto
medium complexity applications. All ST62xx de-
vices are based ona building block approach:a
common coreis surroundedbya numberof on-
chip peripherals.
The ST62E40Bis the erasable EPROM versionof
the ST62T40B device, which maybe usedto em-ulate the ST62T40B device,as wellas the respec-
tive ST6240B ROM devices.
Figure1. Block Diagram
TEST
NMI INTERRUPT
PROGRAM
STACK LEVEL1
STACK LEVEL2
STACK LEVEL3
STACK LEVEL4
STACK LEVEL5
STACK LEVEL6
POWER
SUPPLY OSCILLATOR RESET
DATA ROM
USER
SELECTABLE
DATA RAM
PORTA
PORTB
TIMER1
DIGITALBIT CORE
TEST/VPP
8-BIT
A/D CONVERTER
PA0..PA7/Ain
VDDVSS OSCin OSCout RESET
WATCHDOG
Memory
PORTC
SPI (SERIAL
PERIPHERAL
INTERFACE)
192 Bytes7948 bytes
DATA EEPROM
128Bytes
PB0..PB3/Ain
PC0..PC7/S33..S40
S4..S32, S41..S48
COM1..COM4
(VPPon EPROM/OTP versions only)
TIMER
PB4/20mA Sink
PB5/Scl/20mA Sink
PB6/Sin/20mA Sink
PB7/Sout/20mA Sink
VLCD
VLCD1/3
VLCD2/3
OSC 32kHz
TIMER2
OSC32in
OSC32out
PSS
LCD DRIVER
POWER SUPPLY
SUPERVISOR
WDON
VA0479
6/72
ST62T40B/E40B
INTRODUCTION (Cont’d)
OTP and EPROM devices are functionally identi-
cal. The ROM based versions offer the same func-
tionality selectingas ROM options the options de-finedin the programmable option byte of the
OTP/EPROM versions.OTP devices offerall the
advantagesof user programmabilityat low cost,
which make them the ideal choiceina wide range applications where frequent code changes, mul-
tiple code versionsor last minute programmability
are required.
These compact low-cost devices feature two Tim-
ers comprisingan 8-bit counter anda 7-bit pro-
grammable prescaler, EEPROM data capability,a
serial synchronous port interface (SPI), an 8-bit
A/D Converter with 12 analog inputs,a Digital
Watchdog timer, anda complete LCD controller
driver, making them well suitedfora wide rangeof
automotive, appliance and industrial applications.
Figure2. 80 Pin QFP Package
Table1. ST6240 Pin Description
*Note: 20mA Sink80 VR01649A
Pin
number
Pin
name
Pin
number
Pin
name
Pin
number
Pin
name
Pin
number
Pin
name S43 25 RESET 41 PSS 65 S27 S44 26 OSCout 42 S4 66 S28 S45 27 OSCin 43 S5 67 S29 S46 28 WDON 44 S6 68 S30 S47 29 NMI 45 S7 69 S31 S48 30 TIMER 46 S8 70 S32 COM4 31 PB7/ Sout* 47 S9 71 PC0/S33 COM3 32 PB6/ Sin* 48 S10 72 PC1/S34 COM2 33 PB5/ SCL* 49 S11 73 PC2/S35 COM1 34 PB4* 50 S12 74 PC3/S36 VLCD1/3 35 PB3/ Ain 51 S13 75 PC4/S37 VLCD2/3 36 PB2/ Ain 52 S14 76 PC5/S38 VLCD 37 PB1/ Ain 53 S15 77 PC6/S39 PA7/Ain 38 PB0/ Ain 54 S16 78 PC7/S40 PA6/Ain 39 OSC32out 55 S17 79 S41 PA5/Ain 40 OSC32in 56 S18 80 S42 PA4/Ain 57 S19 TEST 58 S20 PA3/Ain 59 S21 PA2/Ain 60 S22 PA1/Ain 61 S23 PA0/Ain 62 S24 VDD 63 S25 VSS 64 S26
7/72
ST62T40B/E40B
1.2 PIN DESCRIPTIONSDD andVSS. Poweris suppliedto the MCU via
these two pins.VDDis the power connection andSSis the ground connection.
OSCin and OSCout. These pins are internallyconnectedto the on-chip oscillator circuit.A quartz
crystal,a ceramic resonatoror an external clock
signal canbe connected between these two pins.The OSCin pinis the input pin, the OSCout pinis
the output pin.
RESET. The active-low RESET pinis usedto re-
start the microcontroller.
TEST/VPP. The TEST must be heldat VSS for nor-
mal operation (an internal pull-down resistor se-
lects normal operating modeif TEST pinis not
connected).If TEST pinis connectedtoa +12.5V
level during the reset phase, the EPROM/OTP
programming Modeis entered.
NMI. The NMI pin provides the capabilityfor asyn-
chronous interruption,by applyingan external non
maskable interruptto the MCU. The NMI inputis
falling edge sensitive with Schmitt trigger charac-
teristics. The user can selectas option the availa-
bilityofan on-chip pull-upat this pin.
PA0-PA7. These8 lines are organisedas one I/O
port (A). Each line maybe configured under soft-
ware controlas input withor without internal pull- resistors, input with interrupt generation and
pull-up resistor, open-drainor push-pull output,or analog inputs for the A/D converter.
PB0...PB7. These8 lines are organisedas one I/O
port (B). Each line maybe configured under soft-
ware controlas inputs withor without internal pull- resistors, input with interrupt generation and
pull-up resistor, open-drainor push-pull outputs,
analog inputsfor the A/D converter. PB0..PB3 can used as analog inputs for the A/D converter,
while PB7/Sout, PB6/Sin and PB5/Scl canbe used
respectivelyas data out, datain and Clock pinsfor
the on-chip SPI.In addition, PB4..PB7 can sink
20mAfor direct LEDor TRIAC drive.
PC0-PC7. These8 lines are organisedas one I/O
port (C). Each line may be configured under soft-
ware controlas input withor without internal pull- resistor, input with interrupt generation and
pull-up resistor, open-drainor push-pull output,or LCD segment output S33..S40.
TIMER. Thisis the TIMER1 I/O pin.In input mode,is connectedto the prescaler and acts as ex-
ternal timer clockoras control gatefor the internal
timer clock.In output mode, the TIMER pin outputs
the databit whena time-out occurs.The user can
selectas option the availabilityofan on-chip pull-at this pin.
COM1-COM4. These four pins are the LCD pe-
ripheral common outputs. They are the outputsof
the on-chip backplane voltage generator whichis
usedfor multiplexing the45 LCD lines allowingup 180 segmentstobe driven.
S4-S48. These pins are the 45 LCD peripheral
segment outputs. S33..S40 are alternate functions the PortC I/O pins. (Combiports feature)
VLCD. Display voltage supply.It determines the
high voltage level on COM1-COM4 and S4-S48
pins.
VLCD1/3, VLCD2/3. Display supply voltage inputs
for determining the display voltage levels on
COM1-COM4 and S4-S48 pins during multiplex
operation.
PSS. Thisis the Power Supply Supervisor sensing
pin. When the voltage appliedto this pinis falling
belowa software programmed value the highest
priority (NMI) interrupt canbe generated. This pin
hasto be connectedto the voltageto be super-
vised.
OSC32in and OSC32out. These pins are inter-
nally connected with the on-chip 32kHz oscillator
circuit.A 32.768kHz quartz crystal can be con-
nected between these two pinsifitis necessaryto
provide the LCD stand-by clock and real time inter-
rupt. OSC32inis the input pin, OSC32outis the
output pin.
WDON. This pinis an alternate and external
sourceof controlling the watchdog activation, in-
dependantlyof the options set into the MCUby the
user.A low level selects the hardware activated
watchdog, whilea high level selects the software
activated watchdogfor low consumption modes.
This pin overcomes the option byte content. How-
everif WDON pin stateis different from option byte
content, extra consumption mustbe expected.
8/72
ST62T40B/E40B
1.3 MEMORY MAP
1.3.1 Introduction
The MCU operatesin three separate memory
spaces: Program space, Data space, and Stack
space. Operationin these three memory spacesis
describedin the following paragraphs.
Briefly, Program space contains user program
codein Program memory and user vectors; Data
space contains user datain RAM andin Program
memory, and Stack space accommodates six lev-elsof stack for subroutine and interrupt service
routine nesting.
1.3.2 Program Space
Program Space comprises the instructionsto be
executed, the data required for immediate ad-
dressing mode instructions, the reserved factory
test area and the user vectors. Program Spaceis
addressed via the 12-bit ProgramCounter register
(PC register).
Program Spaceis organisedin four 2K pages.
Threeof them are addressedin the 000h-7FFhlo-
cationsof the Program Space by the Program
Counter andby writing the appropriate codein the
Program ROM Page Register (PRPR register).A
common (STATIC) 2K pageis available all the
time for interrupt vectors and common subrou-
tines, independentlyof the PRPR register content.
This “STATIC” pageis directly addressedin the
0800h-0FFFhby the MSBof the Program Counter
register PC 11. Note this page can also be ad-
dressedin the 000-7FFh range.Itis two different
waysof addressing the same physical memory.
Jump froma dynamic pageto another dynamic
pageis achieved by jumping backto the static
page, changing contentsof PRPR and then jump-
ingto the new dynamic page.
Figure3. 8Kbytes Program Space Addressing
Figure4. Memory Addressing Diagram
SPACE
000h
7FFh
800h
FFFh
0000h 1FFFh
Page0
Page1
Static
Page
Page2 Page3
Page1
Static
Page
ROM SPACE
PROGRAM SPACE
PROGRAM
INTERRUPT&
RESET VECTORS
ACCUMULATOR
DATA RAM
BANK SELECT
WINDOW SELECT
RAM REGISTER REGISTER REGISTER REGISTER
DATA READ-ONLY
WINDOW
RAM/ EEPROM
BANKING AREA
000h
03Fh
040h
07Fh
080h
081h
082h
083h
084h
0C0h
0FFh
DATA SPACE
0000h
0FF0h
0FFFh
MEMORY
MEMORY
DATA READ-ONLY
MEMORY
VR01568
9/72
ST62T40B/E40B
MEMORY MAP (Cont’d)
Table2. ST62E40B/T40B Program MemoryMap
Note: OTP/EPROM devices canbe programmed
with thedevelopment toolsavailable fromSTMicro-
electronics (ST62E4X-EPBor ST6240-KIT).
1.3.2.1 Program ROM Page Register (PRPR)
The PRPR register canbe addressed likea RAM
locationin the Data Spaceat the address CAh;neverthelessitisa write only register that cannot accessed with single-bit operations. This regis-
teris usedto select the 2-Kbyte ROM bankof the
Program Space that will be addressed. The
numberof the page hastobe loadedin the PRPR
register. Referto the Program Space descriptionfor additional information concerning the useof
this register. The PRPR registeris not modified
when an interruptora subroutine occurs.
Careis required when handling the PRPR registeritis write only. For this reason,itis not allowed change the PRPR contents while executing in-
terrupt service routine, as the service routine
cannot save and then restoreits previous content.
This operation maybe necessaryif common rou-
tines and interrupt service routines take more than bytes;in this caseit could be necessarytodi-
vide the interrupt service routine intoa (minor) part the static page (start and end) andtoa second
(major) partin oneof the dynamic pages.Ifitis im-
possibleto avoid the writingof this register ininter-
rupt service routines, an imageof this register
must be savedina RAM location, and each time
the program writesto the PRPRit must write also the image register. The image register mustbe
written before PRPR,soifan interrupt occurs be-
tween the two instructions the PRPRis not af-
fected.
Program ROM Page Register (PRPR)
Address: CAh — Write Only
Bits 7-2= Not used.
Bits 1-0= PRPR1-PRPR0: Program ROM Select.
These two bits select the corresponding pageto addressedin the lower partof the 4K program
address spaceas specifiedin Table3.
Caution: This registeris undefinedon Reset. Nei-
ther read nor singlebit instructions maybe usedto
address this register.
Table3. 8Kbytes Program ROM Page Register
Coding
1.3.2.2 Program Memory Protection
The Program Memoryin OTPor EPROM devices
canbe protected against external readoutof mem-
oryby selecting the READOUT PROTECTION op-
tionin the option byte. the EPROM parts, READOUT PROTECTION
option can be disactivated onlyby U.V. erasure
that also results into the whole EPROM context
erasure.
Note: Once the Readout Protectionis activated,itno longer possible, evenfor STMicroelectronics, gain accessto the Program memory contents.
Returned parts witha protection set can therefore
notbe accepted.
ROM Page Device Address Description
Page0 0000h-007Fh
0080h-07FFh
Reserved
User ROM
Page1
“STATIC”
0800h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
User ROM
Reserved
Interrupt Vectors
Reserved
NMI Vector
Reset Vector
Page2 0000h-000Fh
0010h-07FFh
Reserved
User ROM
Page3 0000h-000Fh
0010h-07FFh
Reserved
User ROM - - - - - PRPR1 PRPR0
PRPR1 PRPR0 PCbit11 Memory Page X 1 Static Page (Page1) 0 0 Page0 1 0 Page1 (Static Page) 0 0 Page2 1 0 Page3
10/72
ST62T40B/E40B
MEMORY MAP (Cont’d)
1.3.3 Data Space
Data Space accommodatesall the data necessary
for processing the user program. This space com-
prises the RAM resource, the processor core and
peripheral registers, as well as read-only data
suchas constants and look-up tablesin Program
memory.
1.3.3.1 Data ROM
All read-only datais physically storedin program
memory, which also accommodates the Program
Space. The program memory consequently con-
tains the program codetobe executed,as wellas
the constants and look-up tables required by the
application.
The Data Space locationsin which the differentconstants and look-up tables are addressedby the
processor core may be thoughtof asa 64-byte
window through whichitis possibleto access theread-only data storedin Program memory.
1.3.3.2 Data RAM/EEPROM ST62T40B and ST62E40B devices, the data
space includes60 bytesof RAM, the accumulator
(A), the indirect registers (X), (Y), the short direct
registers (V), (W), the I/O port registers, the pe-
ripheral data and control registers, the interrupt
option register and the Data ROM Window Regis-
ter (DRW register).
Additional RAM and EEPROM pages can alsobe
addressed using banksof 64 bytes located be-
tween addresses 00h and 3Fh.
1.3.4 Stack Space
Stack space consistsof six 12-bit registers which
are usedto stack subroutine and interrupt return
addresses,as wellas the current program counter
contents.
Table4. Additional RAM/EEPROM Banks.
Table5. ST62T40B/E40B Data Memory Space
Device RAM EEPROM
ST62T40B/E40B 2x64 bytes 2x64 bytes
DATAand EEPROM 000h
03Fh
DATAROM WINDOW AREA 040h
07Fh REGISTER 080h REGISTER 081h REGISTER 082h REGISTER 083h
DATA RAM 084h
0BFh
PORTA DATAREGISTER 0C0h
PORTB DATAREGISTER 0C1h
SPI INTERRUPT DISABLEREGISTER 0C2h
PORTC DATAREGISTER 0C3h
PORTA DIRECTION REGISTER 0C4h
PORTB DIRECTION REGISTER 0C5h
PORTC DIRECTIONREGISTER 0C6h
RESERVED 0C7h
INTERRUPT OPTION REGISTER 0C8h*
DATAROM WINDOWREGISTER 0C9h*
ROM BANK SELECT REGISTER 0CAh*
RAM/EEPROM BANKSELECT REGISTER 0CBh*
PORTA OPTION REGISTER 0CCh
RESERVED 0CDh
PORTB OPTION REGISTER 0CEh
PORTC OPTION REGISTER 0CFh
A/D DATAREGISTER 0D0h
A/D CONTROL REGISTER 0D1h
TIMER1 PRESCALER REGISTER 0D2h
TIMER1 COUNTERREGISTER 0D3h
TIMER1 STATUS/CONTROL REGISTER 0D4h
TIMER2 PRESCALER REGISTER 0D5h
TIMER2 COUNTERREGISTER 0D6h
TIMER2 STATUS/CONTROL REGISTER 0D7h
WATCHDOG REGISTER 0D8h
RESERVED 0D9h
PSS STATUS/CONTROL REGISTER 0DAh
32kHz OSCILLATOR CONTROL REGISTER 0DBh
LCD MODE CONTROL REGISTER 0DCh
SPI DATAREGISTER 0DDh
RESERVED 0DEh
EEPROM CONTROL REGISTER 0DFh
LCD RAM 0E0h
0F7h
DATA RAM 0F8h
0FEh
ACCUMULATOR OFFh WRITE ONLY REGISTER
11/72
ST62T40B/E40B
MEMORY MAP (Cont’d)
1.3.5 Data Window Register (DWR)
The Data Read-Only Memory windowis located
from address 0040hto address 007Fhin Data
space.It allows direct readingof64 consecutive
bytes located anywherein program memory, be-
tween address 0000h and 1FFFh (top memory ad-
dress dependson the specific device).All the pro-
gram memory can therefore be usedto store either
instructionsor read-only data. Indeed, the window
canbe movedin stepsof64 bytes along the pro-
gram memoryby writing the appropriate codein the
Data Window Register (DWR).
The DWR can beaddressed like any RAM location the Data Space,itis howevera write-only regis-
ter andtherefore cannotbe accessed using single-
bit operations. This registeris usedto position the
64-byte read-only data window (from address 40hto address 7Fhof the Data space)in program
memoryin 64-byte steps. The effective addressof
the bytetobe readas datain program memoryisobtainedby concatenating the6 least significant
bitsof the register address givenin the instruction
(as least significant bits) and the contentof the
DWR register (as most significant bits),as illustrat-in Figure5 below. For instance, when address-
ing location 0040hof the Data Space, with0 load-in the DWR register, the physical location ad-dressed inprogram memoryis 00h. The DWR reg-
isteris not clearedon reset, thereforeit must be
writtento priorto the first accessto the Data read-only memory window area.
Data Window Register (DWR)
Address: 0C9h — Write Only
Bits6,7= Not used.
Bit 5-0= DWR5-DWR0: Data read-only memory
Window Register Bits. These are the Data read-
only memory Window bits that correspondto the
upper bitsof the data read-only memory space.
Caution: This registeris undefinedon reset. Nei-
ther read nor singlebit instructions maybe usedto
address this register.
Note: Careis required when handling the DWR
register asitis write only. For this reason, the
DWR contents should notbe changed while exe-
cutingan interrupt service routine,as the service
routine cannot save and then restore the register’s
previous contents.Ifitis impossibleto avoid writ-
ingto the DWR during the interrupt service routine, imageof the register must be savedina RAM
location, and each time the program writesto the
DWR,it must also writeto the image register. The
image register mustbe written firstso that,ifanin-
terrupt occurs between the two instructions, the
DWRis not affected.
Figure5. Data read-only memory Window Memory Addressing - DWR5 DWR4 DWR3 DWR2 DWR1 DWR0
DATA ROM
WINDOW REGISTER
CONTENTS
DATA SPACE ADDRESS
40h-7Fh INSTRUCTION
PROGRAM SPACE ADDRESS
765 4 3 2 0 4 321 0 4 321 0
READ17891011
VR01573A
DATA SPACE ADDRESS
59h000 0 0 11
Example:
(DWR)
DWR=28h 0000 00001ROM
ADDRESS:A19h 11 1
12/72
ST62T40B/E40B
MEMORY MAP (Cont’d)
1.3.6 Data RAM/EEPROM Bank Register
(DRBR)
Address: CBh — Write only
Bit 7-5= These bits are not used
Bit4- DRBR4. This bit, when set, selects RAM
Page2.
Bit3- DRBR3. This bit, when set, selects RAM
Page1.
Bit2. These bits are not used.
Bit1- DRBR1. This bit, when set, selects
EEPROM Page1.
Bit0- DRBR0. This bit, when set, selects
EEPROM Page0.
The selectionof the bankis madeby programming
the Data RAM Bank Switch register (DRBR regis-
ter) locatedat address CBhof the Data Space ac-cordingto Table1. No more than one bank should setata time.
The DRBR register canbe addressed likea RAM
Data Spaceat the address CBh; neverthelessitis write only register that cannotbe accessed with
single-bit operations.This registeris usedto select
the desired 64-byte RAM/EEPROM bankof the
Data Space. The numberof banks hastobe load-in the DRBR register and the instruction hasto
pointto the selected locationasifit wasin bank0
(from 00h addressto 3Fh address).
This registeris not cleared during the MCU initiali-
zation, thereforeit must be written before the first
accessto the Data Space bank region. Referto
the Data Space description for additional informa-
tion. The DRBR registeris not modified when an
interruptora subroutine occurs.
Notes:
Careis required when handling the DRBR registeritis write only. For this reason,itis not allowedto change the DRBR contents while executing in-
terrupt service routine,as the service routine can-
not save and then restoreits previous content.Ifitis impossibleto avoid the writingof this registerin
interrupt service routine,an imageof this register
mustbe savedina RAM location, and each time
the program writesto DRBRit must write alsoto
the image register. The image register must be
written first,soif an interrupt occurs between the
two instructions the DRBRis not affected. DRBR Register, only1bit must be set. Other-
wise twoor more pages are enabledin parallel,
producing errors.
Table6. Data RAM Bank Register Set-up - - DRBR4 DRBR3 - DRBR1 DRBR0
DRBR ST62T40B/E40B
00h None
01h EEPROM Page0
02h EEPROM Page1
08h RAM Page1
10h RAM Page2
other Reserved
13/72
ST62T40B/E40B
MEMORY MAP (Cont’d)
1.3.7 EEPROM Description
EEPROM memoryis locatedin 64-byte pagesin
data space. This memory maybe usedby the user
programfor non-volatile data storage.
Data space from 00hto 3Fhis pagedas described Table7. EEPROM locations are accessed di-
rectlyby addressing these paged sectionsof data
space.
The EEPROM does not require dedicated instruc-
tions forread orwrite access. Once selectedvia the
Data RAM Bank Register, the active EEPROM
pageis controlledby the EEPROM Control Regis-
ter (EECTL), whichis described below.
Bit E20FFof the EECTL register must bereset prior any writeor read accessto the EEPROM.Ifno
bank has been selected,orif E2OFFis set, any ac-cessis meaningless.
Programming must be enabled by setting the
E2ENAbitof the EECTL register.
The E2BUSYbitof the EECTL registeris set when
the EEPROMis performinga programming cycle.
Any accessto the EEPROM when E2BUSYis set meaningless.
Provided E2OFF and E2BUSY are reset, an EEP-
ROM locationis read just like any other data loca-
tion, alsoin termsof access time.
Writingto the EEPROM maybe carried outin two
modes: Byte Mode (BMODE) and Parallel Mode
(PMODE).In BMODE, one byteis accessedata
time, whilein PMODE upto8 bytesin the same
row are programmed simultaneously (with conse-
quent speed and power consumption advantages,
the latter being particularly importantin battery
powered circuits).
General Notes:
Data shouldbe written directlyto the intended ad-
dressin EEPROM space. Thereisno buffer mem-
ory between data RAM and the EEPROM space.
When the EEPROMis busy (E2BUSY= “1”)
EECTL cannot be accessedin write mode,itis
only possibleto read the statusof E2BUSY. Thisimplies thatas longas the EEPROMis busy,itis
not possibleto change the statusof the EEPROM
Control Register. EECTL bits4 and5 are reserved
and must neverbe set.
Careis required when dealing withthe EECTL reg-
ister,as some bits are write only. For this reason,
the EECTL contents must notbe altered while ex-
ecutingan interrupt service routine.itis impossibleto avoid writingto this register
withinan interrupt service routine,an imageof the
register must be savedina RAM location, and
each time the program writesto EECTLit must
also writeto the image register. The image register
mustbe writtento firstso that,if an interrupt oc-
curs between the two instructions, the EECTL will
notbe affected.
Table7. Row Arrangement for Parallel Writingof EEPROM Locations
Dataspace
addresses.
Banks0 and1.
Byte 0 1234 56 7
ROW7 38h-3Fh
ROW6 30h-37h
ROW5 28h-2Fh
ROW4 20h-27h
ROW3 18h-1Fh
ROW2 10h-17h
ROW1 08h-0Fh
ROW0 00h-07hto8 bytesin each row maybe programmed simultaneouslyin Parallel Write mode.
The numberof available 64-byte banks(1or2)is device dependent.
14/72
ST62T40B/E40B
MEMORY MAP (Cont’d)
Additional Notes on Parallel Mode: the user wishesto perform parallel program-
ming, the first step should beto set the E2PAR2
bit. From this time on, the EEPROM will be ad-
dressedin write mode, the ROW address willbe
latched andit willbe possibleto changeit onlyat
the endof the programming cycle,orby resetting
E2PAR2 without programming the EEPROM. Af-
ter the ROW addressis latched, the MCU can only
“see” the selected EEPROM row and any attempt writeor read other rows will produce errors.
The EEPROM should not be read while E2PAR2 set. soonas the E2PAR2bitis set, the8 volatile
ROW latches are cleared. From this moment on,
the user can load datainallorin partof the ROW.
Setting E2PAR1 will modify the EEPROM regis-
ters correspondingto the ROW latches accessed
after E2PAR2. For example,if the software sets
E2PAR2 and accesses the EEPROMby writingto
addresses 18h, 1Ah and 1Bh, and then sets
E2PAR1, these three registers willbe modifiedsi-
multaneously; the remaining bytesin the row will unaffected.
Note that E2PAR2is internally resetat the endof
the programming cycle. This implies that the usermust setthe E2PAR2bit between two parallel pro-
gramming cycles. Note thatif the user triesto set
E2PAR1 while E2PAR2is not set, there willbeno
programming cycle and the E2PAR1bit willbe un-
affected. Consequently, the E2PAR1bit cannotbe
setif E2ENAis low. The E2PAR1bit canbe setby
the user, onlyif the E2ENA and E2PAR2 bits are
also set.
EEPROM Control Register (EECTL)
Address: DFh — Read/Write
Reset status: 00h
Bit7= D7: Unused.
Bit6 =E2OFF: Stand-by Enable Bit. WRITE ONLY. thisbitis setthe EEPROMis disabled(anyaccess
willbe meaningless) and thepower consumptionof
the EEPROMis reducedtoits lowest value.
Bit 5-4= D5-D4: Reserved. MUSTbe kept reset.
Bit3= E2PAR1: Parallel Start Bit. WRITE ONLY.
Once inParallel Mode,as soonasthe user software
sets the E2PAR1 bit, parallel writingof the8 adja-
cent registers will start. Thisbitis internally resetat
the endof the programming procedure. Note that
less than8 bytes canbe writtenif required, the un-
defined bytes being unaffectedby the parallel pro-
gramming cycle;thisis explainedin greater detailin
the Additional Notes on Parallel Mode overleaf.
Bit2= E2PAR2: Parallel Mode En. Bit. WRITE
ONLY. Thisbit mustbe setby the user programin
orderto perform parallel programming.If E2PAR2 set and the parallel startbit (E2PAR1)is reset,to8 adjacent bytes can be written simultane-
ously. These8 adjacent bytes are consideredasa
row, whose address lines A7, A6, A5, A4, A3 are
fixed while A2,A1 and A0 are the changing bits,as
illustratedin Table7. E2PAR2is automatically re-
setat the endof any parallel programming proce-
dure.It canbe reset by the user software before
starting the programming procedure, thus leaving
the EEPROM registers unchanged.
Bit1= E2BUSY: EEPROM Busy Bit. READ ON-
LY. Thisbitis automatically setby the EEPROM
control logic when the EEPROMisin program-
ming mode. The user program should testit before
any EEPROM reador write operation; any attempt access the EEPROM while the busybitis set
will be aborted and the writing procedure in
progress willbe completed.
Bit0= E2ENA: EEPROM Enable Bit. WRITE ON-
LY. Thisbit enables programmingof the EEPROM
cells.It must be set before any writeto the EEP-
ROM register. Any attemptto writeto the EEP-
ROM when E2ENAis lowis meaningless and will
not triggera write cycle.
Caution: This registeris undefinedon reset. Nei-
ther read nor singlebit instructions maybe usedto
address this register. E2OFF D5 D4 E2PAR1 E2PAR2 E2BUSY E2ENA
15/72
ST62T40B/E40B
1.4 PROGRAMMING MODES
1.4.1 Option Byte
The Option Byte allows configuration capabilityto
the MCUs. Option byte’s contentis automatically
read, and the selected options enabled, when the
chip resetis activated. can only be accessed during the programming
mode. This accessis made either automatically
(copy froma master device)or by selecting the
OPTION BYTE PROGRAMMING modeof the pro-grammer.
The option byteis locatedina non-user map. No
address hastobe specified.
EPROM Code Option Byte
Bit7. Reserved.
Bit6= NMI PULL.. Thisbit mustbe set hightore-
move the NMI pin pullup resistor. Whenitis low,a
pullupis provided.
Bit5= PROTECT. Thisbit allows the protectionofthe software contents against piracy. When thebit
PROTECTis set high, readoutof the OTP con-
tentsis preventedby hardware. No programming
equipmentis ableto gain accessto the user pro-
gram. When thisbitis low, the user program can read.
Bit4. Reserved.
Bit3= WDACT. Thisbit controls the watchdog ac-
tivation. Whenitis high, hardware activationis se-
lected. The software activationis selected when
WDACTis low.
Bit2= TIM PULL. Thisbit mustbe set highto con-
figure the TIM pin witha pullup resistor whenitis
low,no pullupis provided.
Bit 1-0= Reserved.
The Option byteis written during programming ei-
therby using the PC menu (PC driven Mode)or
automatically (stand-alone mode)
1.4.2 Program Memory
EPROM/OTP programming modeis set bya
+12.5V voltage appliedto the TEST/VPP pin. The
programming flowof the ST62T40B/E40Bis de-
scribedin the User Manualof the EPROM Pro-
gramming Board.
The MCUs can be programmed with the
ST62E4xB EPROM programming tools available
from STMicroelectronics.
1.4.3 EEPROM Data Memory
EEPROM data pages are suppliedin the virgin
state FFh. Partialor total programmingof EEP-
ROM data memory can be performed either
through the application software,or throughan ex-
ternal programmer. Any STMicroelectronics tool
usedfor the program memory (OTP/EPROM) can
alsobe usedto program the EEPROM data mem-ory.
1.4.4 EPROM Erasing
The EPROMof the windowed packageof the
MCUs maybe erasedby exposureto Ultra Violet
light. The erasure characteristicof the MCUsis
such that erasure begins when the memoryis ex-posedto light witha wave lengths shorter than ap-
proximately 4000Å.It should be noted that sun-
lights and some typesof fluorescent lamps have
wavelengthsin the range 3000-4000Å.is thus recommended that the windowof the
MCUs packagesbe coveredbyan opaque labelto
prevent unintentional erasure problems when test-
ing the applicationin suchan environment.
The recommended erasure procedure of the
MCUs EPROMis the exposureto short wave ul-
traviolet light which havea wave-length 2537A.
The integrated dose (i.e. U.V. intensityx exposure
time) for erasure should bea minimumof 15W-
sec/cm2. The erasure time with this dosageis ap-
proximately 15to 20 minutes using an ultraviolet
lamp with 12000μW/cm2 power rating. The
ST62E40B should be placed within 2.5cm (1Inch)of the lamp tubes during erasure. NMI
PULL
PRO-
TECT - WDACT TIM
PULL --
16/72
ST62T40B/E40B CENTRAL PROCESSING UNIT
2.1 INTRODUCTION
The CPU Coreof ST6 devicesis independentofthe
I/Oor Memory configuration. As such,it may be
thoughtof as an independent central processor
communicating with on-chip I/O, Memory and Pe-
ripherals via internal address, data, and control
buses. In-core communicationis arranged as
shownin Figure6; the controller being externally
linkedto both the Reset and Oscillator circuits,
while thecoreis linkedto thededicated on-chip pe-
ripherals via the serial data bus and indirectly, for
interrupt purposes, through the control registers.
2.2 CPU REGISTERS
The ST6Family CPU core features sixregisters and
three pairsof flags availableto the programmer.
These are describedin the following paragraphs.
Accumulator (A). The accumulatoris an 8-bit
general purpose register usedinall arithmetic cal-
culations, logical operations, and data manipula-
tions. The accumulator canbe addressedin Data
spaceasa RAM locationat address FFh. Thus the
ST6 can manipulate the accumulator just like any
other registerin Data space.
Indirect Registers (X, Y). These two indirect reg-
isters are usedas pointersto memory locationsin
Data space. They are usedin the register-indirect
addressing mode. These registers can be ad-
dressedin the data spaceas RAM locationsat ad-
dresses 80h (X) and 81h (Y). They can alsobe ac-
cessed with the direct, short direct,orbit direct ad-
dressing modes. Accordingly, the ST6 instruction
set can use the indirect registersas any other reg-
isterof the data space.
Short Direct Registers (V, W). These two regis-
ters are usedto savea bytein short direct ad-
dressing mode. They can be addressedin Data
spaceas RAM locationsat addresses 82h (V) and
83h (W). They can alsobe accessed using the di-
rect and bit direct addressing modes. Thus, the
ST6 instruction set can use the short direct regis-
tersas any other registerof the data space.
Program Counter (PC). The program counterisa
12-bit register which contains the addressof the
next ROM locationto be processedby the core.
This ROM location may be an opcode, an oper-
and, or the addressof an operand. The 12-bit
length allows the direct addressingof 4096 bytes Program space.
Figure6. ST6 Core Block Diagram
PROGRAM
RESET
OPCODE
FLAG
VALUES
CONTROLLER
FLAGS
ALU
A-DATA B-DATA
ADDRESS/READLINE
DATA SPACE
INTERRUPTS
DATA
RAM/EEPROM
DATA
ROM/EPROM
RESULTSTO DATA SPACE (WRITE LINE)
ROM/EPROM
DEDICATIONS
ACCUMULATOR
CONTROL
SIGNALS
OSCin OSCout
ADDRESS
DECODER
Program Counter
and LAYER STACK
0,01TO 8MHz
VR01811
17/72
ST62T40B/E40B
CPU REGISTERS (Cont’d)
However,if the program space contains more than
4096 bytes, the additional memoryin program
space can be addressed by using the Program
Bank Switch register.
The PC valueis incremented after reading the ad-
dressof the current instruction.To execute relative
jumps, the PC and the offset are shifted through
the ALU, where they are added; the resultis then
shifted back into the PC. The program counter can changedin the following ways: JP (Jump) instructionPC=Jump address CALL instructionPC= Call address Relative Branch Instruction.PC= PC +/- offset Interrupt PC=Interrupt vector Reset PC= Reset vector RET& RETI instructionsPC= Pop (stack) Normal instructionPC= PC+1
Flags (C,Z). The ST6 CPU includes three pairsof
flags (Carry and Zero), each pair being associated
with oneof the three normal modesof operation:
Normal mode, Interrupt mode and Non Maskable
Interrupt mode. Each pair consistsofa CARRY
flag anda ZERO flag. One pair (CN, ZN)is used
during Normal operation, another pairis used dur-
ing Interrupt mode (CI, ZI), anda third pairis used the Non Maskable Interrupt mode (CNMI, ZN-
MI).
The ST6 CPU uses the pairof flags associated
with the current mode:as soonasan interrupt (or Non Maskable Interrupt)is generated, the ST6
CPU uses the Interrupt flags (resp. the NMI flags)
insteadof the Normal flags. When the RETI in-
structionis executed, the previously used setof
flagsis restored.It shouldbe noted that each flag
set can onlybe addressedinits own context (Non
Maskable Interrupt, Normal Interruptor Main rou-
tine). The flags are not cleared during context
switching and thus retain their status.
The Carry flagis set whena carryora borrow oc-
curs during arithmetic operations; otherwiseitis
cleared. The Carry flagis also setto the valueof
thebit testedinabit test instruction;it also partici-
patesin the rotate left instruction.
The Zero flagis setif the resultof the last arithme-
ticor logical operation was equalto zero; other-
wiseitis cleared.
Switching between the three setsof flagsis per-
formed automatically whenan NMI,an interruptor RETI instructions occurs. As the NMI modeis
automatically selected after the resetof the MCU,
the ST6 core usesat first the NMI flags.
Stack. The ST6 CPU includesa true LIFO hard-
ware stack which eliminates the need fora stack
pointer. The stack consistsof six separate 12-bit
RAM locations that do not belongto the data
space RAM area. Whena subroutine call(or inter-
rupt request) occurs, the contentsof each level are
shifted into the next higher level, while the content the PCis shifted into the first level (the original
contentsof the sixth stack level are lost). Whena
subroutineor interrupt return occurs (RETor RETI
instructions), the first level registeris shifted back
into the PC and the valueof each levelis popped
back into the previous level. Since the accumula-
tor,in common withall other data space registers, not storedin this stack, managementof these
registers shouldbe performed within the subrou-
tine. The stack will remaininits “deepest” position more than6 nested callsor interrupts are execut-
ed, and consequently the last return address will lost.It will also remaininits highest positionif
the stackis empty anda RETor RETIis executed. this case the next instruction willbe executed.
Figure7. ST6 CPU Programming Model
SHORT
DIRECT
ADDRESSING
MODEVREGISTER REGISTER
PROGRAMCOUNTER
SIXLEVELS
STACKREGISTERNORMAL FLAGS
INTERRUPTFLAGS
NMI FLAGS
INDEX
REGISTER
VA000423b11
ACCUMULATOR REG. POINTER REG. POINTER
18/72
ST62T40B/E40B CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES
3.1 CLOCK SYSTEM
3.1.1 Main Oscillator
The MCU featuresa Main Oscillator which canbe
drivenbyan external clock,or usedin conjunction
withan AT-cut parallel resonant crystalora suita-
ble ceramic resonator.
Figure8 illustrates various possible oscillator con-
figurations usingan external crystalor ceramic res-
onator,an external clock input. CL1an CL2 should
havea capacitancein the range12to22 pFforan
oscillator frequencyin the 4-8 MHz range.
The internal MCU clock Frequency(FINT)is divid-by13to drive the CPU core andby12to drive
the A/D converter and the watchdog timer, while
clock usedto drive on-chip peripherals depends the peripheral as shownin the clock circuit
block diagram.
Withan 8MHz oscillator frequency, the fastest ma-
chine cycleis therefore 1.625μs. machine cycleis thesmallest unitof time needed execute anyoperation (for instance,to increment
the Program Counter). An instruction may require
two, four,or five machine cycles for execution.
Figure8. Oscillator Configurations
Figure9. Clock Circuit Block Diagram
OSCin OSCout
CL1n CL2
ST6xxx
CRYSTAL/RESONATOR CLOCK
OSCin OSCout
ST6xxx
EXTERNAL CLOCK
VA0016
VA0015A
MAIN
OSCILLATOR
Core:13
:12
Timer1&2
Watchdog
POR
fINT
ADC
OSCin
OSCout
fOSC
fINT
OSC32in
OSC32out
32kHz
OSCILLATOR
MUX LCD
CONTROLLER
DRIVER
EOCRbit5
(START/STOP)
19/72
ST62T40B/E40B
CLOCK SYSTEM (Cont’d)
3.1.232 KHz STAND-BY OSCILLATOR additional32KHz stand-byon chip oscillatoral-
lowsto generate real time interrupts andto supply
the clockto the LCD driver with the main oscillator
stopped. This enables the MCUto perform real
time functions with the LCD display running while
keeping advantagesof low power consumption.
Figure 10 shows the 32KHz oscillator block dia-
gram. 32.768KHz quartz crystal mustbe connectedto
the OSC32in and OSC32out pinsto perform the
real time clock operation. Two external capacitors 15-22pF each must be connected between the
oscillator pins and ground. The 32KHz oscillatoris
managed by the dedicated status/control register
32OCR. longas the 32KHz stand-by oscillatoris ena-
bled, 32KHz internal clockis availableto drive
LCD controller driver. This clockis divideby214to
generate interrupt request every 500ms. The peri-
odic interrupt request serves as reference time-
base for real time functions.
Note: When the 32KHz stand-by oscillator is
stopped (bit5 of the Status/Control register
cleared) the divider chainis supplied witha clock
signal synchronous with machine cycle(fINT /13),
this produces an interrupt request every 13x214
clock cycle (i.e. 26.624ms) with an 8MHz quartz
crystal.
32KHz Oscillator Register (32OCR)
Address: DBh- Read/Write
Bit7= EOSCI. Enable Oscillator Interrupt. This bit,
when set, enables the 32KHz oscillator interrupt
request.
Bit6= OSCEOC. Oscillator Interrupt Flag. Thisbit
indicates when the 32KHz oscillator has measured 500ms elapsed time (providing a
32.768KHzquartz crystal is connected to the
32KHz oscillator dedicated pins). An interrupt re-
quest can be generatedin relationto the stateof
EOSCI bit. Thisbit must be cleared by the user
program before leaving the interrupt service rou-
tine.
Bit5= START/STOP.Oscillator Start/Stop bit.
This bit, when set, enables the 32KHz stand-by
oscillator and the free running divider chainis sup-
pliedby the 32KHz oscillator signal. When thisbit clearedto zero the divider chainis supplied withINT /13.
This registeris cleared during reset.
Note: achieve minimum power consumptionin STOP
mode (no system clock), the stand-by oscillator
mustbe switchedoff (real time function not availa-
ble)by clearing the Start/Stopbitin the oscillator
status/control register.
Figure 10. 32KHz Oscillator Block Diagram
EOSCI OSCEOC S/S D4 D3 D2 D1 D0
OSC32KHz
EOSCI OSCEOC START
STOP X XX X X
INT
OSC32IN
OSC32OUT
2x15...22pF
32.768KHz
Crystal fINT/13
OSC32KHz MUX
DIV214
20/72
ST62T40B/E40B
3.2 RESETS
The MCU canbe resetin three ways:by the external Reset input being pulled low;by Power-on Reset;by the digital Watchdog peripheral timing out.
3.2.1 RESET Input
The RESET pin maybe connectedtoa deviceof
the application boardin orderto reset the MCUif
required. The RESET pin may be pulled lowin
RUN, WAITor STOP mode. This input can be
usedto reset the MCU internal state and ensurea
correct start-up procedure. The pinis active low
and featuresa Schmitt trigger input. The internal
Reset signalis generatedby addinga delayto the
external signal. Therefore even short pulses on
the RESET pin are acceptable, providedVDD has
completedits rising phase and that the oscillatoris
running correctly (normal RUNor WAIT modes).
The MCUis keptin the Reset stateas longas the
RESET pinis held low. RESET activation occursin the RUNor WAIT
modes, processingof the user programis stopped
(RUN mode only), the Inputs and Outputs are con-
figured as inputs with pull-up resistors and the
main Oscillatoris restarted. When the levelon the
RESET pin then goes high, the initialization se-
quenceis executed following expiryof the internal
delay period. RESET pin activation occursin the STOP mode,
the oscillator startsup andall Inputs and Outputs
are configured as inputs with pull-up resistors.
When the levelof the RESET pin then goes high,
the initialization sequenceis executed following
expiryof the internal delay period.
3.2.2 Power-on Reset
The functionof the POR circuit consistsin waking the MCUat an appropriate stage during the
power-on sequence.At the beginningof this se-
quence, the MCUis configuredin the Reset state:
all I/O ports are configuredas inputs with pull-up
resistors andno instructionis executed. When the
power supply voltage risestoa sufficient level, the
oscillator startsto operate, whereuponan internal
delayis initiated,in orderto allow the oscillatorto
fully stabilize before executing the first instruction.
The initialization sequenceis executed immediate- following the internal delay.
The internal delayis generatedbyan on-chipcoun-
ter. The internal reset lineis released 2048 internal
clock cycles after releaseof the external reset.
Notes: ensure correct start-up, the user should take
care that the reset signalis not released before theDD levelis sufficientto allow MCU operationat
the chosen frequency (see Recommended Oper-
ating Conditions). proper reset signal fora slow risingVDD supply
can generallybe providedby an external RC net-
work connectedto the RESET pin.
Figure 11. Reset and Interrupt Processing
INT LATCHCLEARED
NMI MASKSET
RESETIF PRESENT)
SELECT
NMI MODE FLAGS RESET STILL
PRESENT
YES
PUT FFEH ADDRESS BUS
FROM RESETLOCATIONS
FFE/FFF
FETCH INSTRUCTION
LOADPC
VA000427
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ST62T40B/E40B
RESETS (Cont’d)
3.2.3 Watchdog Reset
The MCU providesa Watchdog timer functionin
orderto ensure graceful recovery from software
upsets.If the Watchdog registeris not refreshed
before an end-of-count conditionis reached, the
internal reset willbe activated. This, amongst oth- things, resets the watchdog counter.
The MCU restarts just as though the Reset had
been generatedby the RESET pin, including the
built-in stabilisation delay period.
3.2.4 Application Notes external resistoris required betweenVDD and
the Reset pin, thanksto the built-in pull-up device.
The POR circuit operates dynamically,in thatit
triggers MCU initialization on detecting the rising
edgeof VDD. The typical thresholdisin the region2 volts, but the actual valueof the detected
threshold dependson the wayin which VDD rises.
The POR circuitis NOT designedto supervise
static,or slowly risingor falling VDD.
3.2.5 MCU Initialization Sequence
Whena reset occurs the stackis reset, the PCis
loaded with the addressof the Reset Vector (locat-in program ROM startingat address 0FFEh).A
jump tothe beginningof the user program mustbe
codedat this address. Followinga Reset, the In-
terrupt flagis automatically set,so that the CPUis Non Maskable Interrupt mode; this prevents the
initialisation routine from being interrupted. Thein-
itialisation routine should thereforebe terminateda RETI instruction,in orderto revertto normal
mode and enable interrupts.Ifno pending interrupt presentat the endof the initialisation routine, the
MCU will continue by processing the instruction
immediately following the RETI instruction.If, how-
ever,a pending interruptis present,it willbe serv-
iced.
Figure 12. Reset and Interrupt Processing
Figure 13. Reset Block Diagram
RESET
RESET
VECTOR JP:2 BYTES/4 CYCLES
RETI
RETI:1 BYTE/2 CYCLES
INITIALIZATION
ROUTINE
VA00181
VDD
RESET
300kΩ
2.8kΩ
POWER
WATCHDOG RESET
COUNTER
RESET
ST6
INTERNAL
RESET
fOSC
RESET RESET
VA0200B
22/72
ST62T40B/E40B
RESETS (Cont’d)
Table8. Register Reset Status
Register Address(es) Status Comment
EEPROM Control Register
Port Data Registers
Port A,B Direction Register
Port A,B Option Register
Interrupt Option Register
SPI Registers
LCD Mode Control Register
32kHz Oscillator Register
0DFh
0C0h, 0C2h, 0C3h
0C4hto 0C5h
0CCh, 0CEh
0C8h
0C2hto 0DDh
0DCh
0DBh
00h
EEPROM enabled
I/O are Input with pull-up
Interrupt disabled
SPI disabled
LCD displayoff
Interrupt disabled
PortC Direction Register
PortC Option Register
0C6h
0CFh FFh LCD OutputY,V,W, Register
Accumulator
Data RAM
Data RAM Page REgister
Data ROM Window Register
EEPROM
A/D Result Register
080H TO083H
0FFh
084hto 0BFh
0CBh
0C9h
00hto 03Fh
0D0h
Undefined As writtenif programmed
TIMER1 Status/Control
TIMER1 Counter Register
TIMER1 Prescaler Register
TIMER2 Status/Control
TIMER2 Counter Register
TIMER2 Prescaler Register
Watchdog Counter Register
A/D Control Register
0D4h
0D3h
0D2h
0D7h
0D5h
0D6h
0D8h
0D1h
00h
FFh
7Fh
00h
FFh
7Fh
FEh
40h
TIMER1 disabled/Max count loaded
TIMER2 disabled/Max count loaded
A/Din Standby
23/72
ST62T40B/E40B
3.3 DIGITAL WATCHDOG
The digital Watchdog consistsofa reloadable
downcounter timer which can be usedto provide
controlled recovery from software upsets.
The Watchdog circuit generatesa Reset when the
downcounter reaches zero. User software can
prevent this reset by reloading the counter, and
should therefore be written so that the counteris
regularly reloaded while the user program runs
correctly.In the eventofa software mishap (usual- caused by externally generated interference),
the user program willno longer behaveinits usual
fashion and the timer register will thus not be re-
loaded periodically. Consequently the timer will
decrement downto 00h and reset the MCU.In or-
derto maximise the effectivenessof the Watchdog
function, user software must be written with this
conceptin mind.
Watchdog behaviouris governedby one option,
known as “WATCHDOG ACTIVATION” (i.e.
HARDWAREor SOFTWARE) (See Table9). the SOFTWARE option, the Watchdogis disa-
bled untilbitCof the DWDR register has been set.
When the Watchdogis disabled, low power Stop
modeis available. Once activated, the Watchdog
cannotbe disabled, exceptby resetting the MCU. the HARDWARE option, the Watchdogis per-
manently enabled. Since the oscillator will run con-
tinuously, low power modeis not available. The
STOP instructionis interpretedasa WAIT instruc-
tion, and the Watchdog continuesto countdown.
When the MCU exits STOP mode (i.e. whenanin-
terruptis generated), the Watchdog resumesits
activity.
Table9. Recommended Option Choices
Functions Required Recommended Options
Stop Mode “SOFTWARE WATCHDOG”
Watchdog “HARDWARE WATCHDOG”
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ST62T40B/E40B
DIGITAL WATCHDOG (Cont’d)
The Watchdogis associated witha Data space
register (Digital WatchDog Register, DWDR, loca-
tion 0D8h) whichis describedin greater detailin
Section 3.3.1 Digital Watchdog Register (DWDR).
This registeris setto 0FEh on Reset: bitCis
clearedto “0”, which disables the Watchdog; the
timer downcounter bits, T0to T5, and the SRbit
areall setto “1”, thus selecting the longest Watch-
dog timer period. This time period canbe setto the
user’s requirementsby setting the appropriate val-for bits T0to T5in the DWDR register. The SR
bit mustbe setto “1”, sinceitis thisbit which gen-
erates the Reset signal whenit changesto “0”;
clearing thisbit would generatean immediate Re-
set. shouldbe noted that the orderof the bitsin the
DWDR registeris inverted with respectto the as-
sociated bitsin the down counter: bit7of the
DWDR register corresponds,in fact,to T0 andbitto T5. The user should bearin mind the fact that
these bits are inverted and shifted with respectto
the physical counter bits when writingto this regis-
ter. The relationship between the DWDR register
bits and the physical implementationof the Watch-
dog timer downcounteris illustratedin Figure 14.
Only the6 most significant bits maybe usedto de-
fine the time period, sinceitisbit6 which triggers
the Reset whenit changesto “0”. This offers the
usera choiceof 64 timed periods ranging from
3,072to 196,608 clock cycles (with an oscillator
frequencyof 8MHz, thisis equivalentto timer peri-
ods ranging from 384μsto 24.576ms).
Figure 14. Watchdog Counter Control
WATCHDOG
CONTROL
REGISTER
WATCHDOG
COUNTER
OSC ÷12
RESET
VR02068A8
25/72
ST62T40B/E40B
DIGITAL WATCHDOG (Cont’d)
3.3.1 Digital Watchdog Register (DWDR)
Address: 0D8h — Read/Write
Reset status: 1111 1110b
Bit0=C: Watchdog Controlbit the hardware optionis selected, thisbitis forced
high and the user cannot changeit (the Watchdog always active). When the software optionis se-
lected, the Watchdog functionis activatedby set-
tingbitCto1, and cannot thenbe disabled (save resetting the MCU).
WhenCis kept low the counter canbe usedasa
7-bit timer.
Thisbitis clearedto“0”on Reset.
Bit1= SR: Software Resetbit
Thisbit triggersa Reset when cleared.
WhenC=“0” (Watchdog disabled)itis the MSBof
the 7-bit timer.
Thisbitis setto “1”on Reset.
Bits 2-7= T5-T0: Downcounter bits should be noted that the register bits are re-
versed and shifted with respectto the physical
counter: bit-7 (T0)is the LSBof the Watchdog
downcounter and bit-2 (T5)is the MSB.
These bits are setto“1”on Reset.
3.3.2 Application Notes
The Watchdog playsan important supporting role the high noise immunityof ST62xx devices, and
should be used wherever possible. Watchdog re-
lated options shouldbe selectedon the basisofa
trade-off between application security and STOP
mode availability.
When STOP modeis not required, hardware acti-
vation should be preferred, asit provides maxi-
mum security, especially during power-on.
When software activationis selected and the
Watchdogis not activated, the downcounter may usedasa simple 7-bit timer (remember that the
bits arein reverse order).
The software activation option should be chosen
only when the Watchdog counteristobe usedas timer.To ensure the Watchdog has not been un-
expectedly activated, the following instructions
shouldbe executed within the first27 instructions:
jrr 0, WD, #+3 T1 T2 T3 T4 T5 SR C
26/72
ST62T40B/E40B
DIGITAL WATCHDOG (Cont’d)
These instructions test theC bit and Reset the
MCU (i.e. disable the Watchdog)if the bitis set
(i.e.if the Watchdogis active), thus disabling the
Watchdog.all modes,a minimumof28 instructions are ex-
ecuted after activation, before the Watchdog can
generatea Reset. Consequently, user software
should load the watchdog counter within the first instructions following Watchdog activation
(software mode),or within the first 27 instructions
executed followinga Reset (hardware activation). shouldbe noted that when the GENbitis low (in-
terrupts disabled), the NMI interruptis active but
cannot causea wakeup from STOP/WAIT modes.
Figure 15. Digital Watchdog Block Diagram
RSFF
DATA BUS
VA00010 -12
OSCILLATOR
RESET
WRITE
RESET
DB0S
DB1.7 SETLOAD 8-2
SET
CLOCK
27/72
ST62T40B/E40B
3.4 INTERRUPTS
The CPU can manage four Maskable Interrupt
sources,in additiontoa Non Maskable Interrupt
source (top priority interrupt). Each sourceis asso-
ciated witha specific Interrupt Vector which con-
tainsa Jump instructionto the associated interrupt
service routine. These vectors are locatedin Pro-
gram space (see Table 10).
When an interrupt source generates an interrupt
request, and interrupt processingis enabled, the registeris loaded with the addressof the inter-
rupt vector (i.e.of the Jump instruction), which
then causesa Jumpto the relevant interrupt serv-
ice routine, thus servicing the interrupt.
Interrupt sources are linkedto events eitheron ex-
ternal pins,or on chip peripherals. Several events
can be ORed on the same interrupt source, and
relevant flags are availableto determine which
event triggered the interrupt.
The Non Maskable Interrupt request has the high-
est priority and can interrupt any interrupt routine any time; the other four interrupts cannot inter-
rupt each other.If more than one interrupt request pending, these are processedby the processor
core accordingto their priority level: source#1 has
the higher priority while source#4 the lower. The
priorityof each interrupt sourceis fixed.
Table 10. Interrupt Vector Map
3.4.1 Interrupt request
All interrupt sources but the Non Maskable Inter-
rupt source canbe disabledby setting accordingly
the GENbitof the Interrupt Option Register (IOR).
This GENbit also definesif aninterrupt source,in-
cluding the Non Maskable Interrupt source, canre-
start the MCU from STOP/WAIT modes.
Interrupt request from the Non Maskable Interrupt
source#0is latchedbya flip flop whichis automat-
ically resetby the coreat the beginningof the non-
maskable interrupt service routine.
Interrupt request from source #1 can be config-
ured eitheras edgeor level sensitiveby setting ac-
cordingly the LESbitof the Interrupt Option Regis-
ter (IOR).
Interrupt request from source#2 are always edge
sensitive. The edge polarity can be configuredby
setting accordingly the ESBbitof the Interrupt Op-
tion Register (IOR).
Interrupt request from sources#3& #4 are level
sensitive. edge sensitive mode,a latchis set whena edge
occurs on the interrupt source line andis cleared
when the associated interrupt routineis started.
So, the occurrenceof an interrupt canbe stored,
until completionof the running interrupt routine be-
fore being processed.If several interrupt requests
occurs before completionof the running interrupt
routine, only the first requestis stored.
Storageof interrupt requestsis not availablein lev- sensitive mode. To be taken into account, the
low level mustbe presenton the interrupt pin when
the MCU samples the line after instruction execu-
tion. the endof every instruction, the MCU tests the
interrupt lines:if thereis an interrupt request the
next instructionis not executed and the appropri-
ate interrupt service routineis executed instead.
Table 11. Interrupt Option Register Description
Interrupt Source Priority Vector Address
Interrupt source#0 1 (FFCh-FFDh)
Interrupt source#1 2 (FF6h-FF7h)
Interrupt source#2 3 (FF4h-FF5h)
Interrupt source#3 4 (FF2h-FF3h)
Interrupt source#4 5 (FF0h-FF1h)
GEN SET Enableall interrupts
CLEARED Disableall interrupts
ESB
SET Rising edge modeon inter-
rupt source#2
CLEARED Falling edge modeon inter-
rupt source#2
LES
SET Level-sensitive modeonin-
terrupt source#1
CLEARED Falling edge modeon inter-
rupt source#1
OTHERS NOT USED
28/72
ST62T40B/E40B
INTERRUPTS (Cont’d)
3.4.2 Interrupt Procedure
The interrupt procedureis very similartoa call pro-
cedure, indeed the user can consider the interrupt an asynchronous call procedure. As thisis an
asynchronous event, the user cannot know the
context and the timeat whichit occurred. Asa re-
sult, the user should saveall Data space registers
which may be used within the interrupt routines.
There are separate setsof processor flagsfor nor-
mal, interrupt and non-maskable interrupt modes,
which are automatically switched and so do not
needtobe saved.
The following list summarizes the interrupt proce-
dure:
MCU The interruptis detected. TheC andZ flags are replacedby the interrupt
flags (orby the NMI flags). The PC contents are storedin the first levelof
the stack. The normal interrupt lines are inhibited (NMI still
active). The first internal latchis cleared. Theassociated interruptvectoris loaded inthe PC.
WARNING: In some circumstances, whena
maskable interrupt occurs while the ST6 coreisin
NORMAL mode and especially during the execu-
tionof an ”ldi IOR, 00h” instruction (disablingall
maskable interrupts):if the interrupt arrives during
the first3 cyclesof the ”ldi” instruction (whichisa
4-cycle instruction) the core will switchto interrupt
mode BUT the flags CN and ZN will NOT switchto
the interrupt pairCI andZI.
User User selected registers are saved within thein-
terrupt service routine (normally ona software
stack). Thesourceof the interruptis found bypolling the
interrupt flags(if more than one sourceis associ-
ated with the same vector). The interruptis serviced. Return from interrupt (RETI)
MCU Automatically the MCU switches backto the nor-
mal flag set (or the interrupt flag set) and pops
the previous PC value from the stack.
The interrupt routine usually beginsby the identify-
ing the device which generated the interrupt re-
quest (by polling). The user should save the regis-
ters which are used within the interrupt routineina
software stack. After the RETI instructionis exe-
cuted, the MCU returnsto the main routine.
Figure 16. Interrupt Processing Flow Chart
INSTRUCTION
FETCH
INSTRUCTION
EXECUTE
INSTRUCTION
WAS
THEINSTRUCTION
ARETI
CLEAR
INTERRUPTMASK
SELECT
PROGRAM FLAGS
”POP”
THE STACKEDPC
CHECK IFTHEREIS INTERRUPTREQUEST
AND INTERRUPTMASK
SELECT
INTERNALMODE FLAG
PUSHTHE
PCINTO THESTACK
LOAD PCFROM
INTERRUPTVECTOR
(FFC/FFD)
SET
INTERRUPT MASK
YES ISTHE CORE
ALREADYIN
NORMAL MODE
VA000014
YES
YES
29/72
ST62T40B/E40B
INTERRUPTS (Cont’d)
3.4.3 Interrupt Option Register (IOR)
The Interrupt Option Register (IOR)is usedto en-
able/disable the individual interrupt sources andto
select the operating modeof the external interrupt
inputs. This registeris write-only and cannot be
accessedby single-bit operations.
Address: 0C8h — Write Only
Reset status: 00h
Bit7, Bits 3-0= Unused.
Bit6= LES: Level/Edge Selection bit.
When thisbitis setto one, the interrupt source#1 level sensitive. When clearedto zero the edge
sensitive modefor interrupt requestis selected.
Bit5= ESB: Edge Selection bit.
The bit ESB selects the polarityof the interrupt
source #2.
Bit4= GEN: Global Enable Interrupt. When thisbit setto one,all interrupts are enabled. When this
bitis clearedto zeroall the interrupts (excluding
NMI) are disabled.
When the GENbitis low, the NMI interruptis ac-
tive but cannot causea wakeup from STOP/WAIT
modes.
This registeris clearedon reset.
3.4.4 Interrupt sources
Interrupt sources available on the
ST62E40B/T40B are summarizedin the Table 12
with associated maskbitto enable/disable thein-terrupt request.
Table 12. Interrupt Requests and Mask Bits LES ESB GEN - - - -
Peripheral Register Address
Register Maskbit Masked Interrupt Source Interrupt
source
GENERAL IOR C8h GEN All Interrupts, excluding NMI All
TIMER1
TIMER2
TSCR1
TSCR2
D4h
D7h ETI TMZ: TIMER Overflow source3
A/D CONVERTER ADCR D1h EAI EOC: Endof Conversion source4
SPI SPI C2h ALL Endof Transmission source1
Port PAn ORPA-DRPA C0h-C4h ORPAn-DRPAn PAnpin source2
Port PBn ORPB-DRPB C1h-C5h ORPBn-DRPBn PBnpin source2
Port PCn ORPC-DRPC C6h-CFh ORPCn-DRPCn PCn pin source2
PSS PSSCR DAh PEI PIF: source0
32kHz OSC 32OCR DBh EOSCI OSCEOC source3
30/72
ST62T40B/E40B
INTERRUPTS (Cont’d)
Figure 17. Interrupt Block Diagram
PORTA
PBE
VDD
FROM REGISTER PORT A,B,C
SINGLEBIT ENABLE
CLK Q
CLR Start
INT#0 NMI (FFC,D))
INT#2 (FF4,5)
NMI
PORTB
Bits
SPI
CLK Q
CLR
MUX Start
IORbit6 (LES)
PBE FF
CLK Q
CLR
IORbit5 (ESB) Start
INT#1 (FF6,7)
INT#3 (FF2,3)
INT#4 (FF0,1)
IOR bit4(GEN)
PORTC
TMZETI
TMZ
ETI
OSCEOC
EOSCI
EAI
EOC
RESTART
STOP/WAIT
FROM
PBE
PIF
PEI
TIMER1
TIMER2
OSC32kHz
A/D CONVERTER
PSS
VR0426R
31/72
ST62T40B/E40B
3.5 POWER SAVING MODES
The WAIT and STOP modes have been imple-
mentedin the ST62xx familyof MCUsin orderto
reduce the product’s electrical consumption during
idle periods. These two power saving modes are
describedin the following paragraphs.
3.5.1 WAIT Mode
The MCU goes into WAIT modeas soon as the
WAIT instructionis executed. The microcontroller
canbe consideredas beingina “software frozen”
state where the core stops processing the pro-
gram instructions, the RAM contents and peripher- registers are preservedas long as the power
supply voltageis higher than the RAM retention
voltage.In this mode the peripherals are still ac-tive.
WAIT mode can be used when the user wantsto
reduce the MCU power consumption during idle
periods, while not losing trackof timeor the capa-
bilityof monitoring external events. The active os-
cillatoris not stoppedin orderto providea clock
signalto the peripherals. Timer counting may be
enabledas wellas the Timer interrupt, before en-
tering the WAIT mode: this allows the WAIT mode be exited whena Timer interrupt occurs. The
same appliesto other peripherals which use the
clock signal. the WAIT modeis exited duetoa Reset (either activating the external pinor generatedby the
Watchdog), the MCU entersa normal reset proce-
dure.If an interruptis generated during WAIT
mode, the MCU’s behaviour depends on the state the processor core priorto the WAIT instruction,
but also on the kindof interrupt request whichis
generated. Thisis describedin the following para-
graphs. The processor core does not generatea
delay following the occurrenceof the interrupt, be-
cause the oscillator clockis still available and no
stabilisation periodis necessary.
3.5.2 STOP Mode the Watchdogis disabled, STOP modeis availa-
ble. Whenin STOP mode, the MCUis placedin
the lowest power consumption mode.In this oper-
ating mode, the microcontroller canbe considered being “frozen”, no instructionis executed, the
oscillatoris stopped, the RAM contents and pe-ripheral registers are preserved as long as the
power supply voltageis higher than the RAM re-
tention voltage, and the ST62xx core waitsfor the
occurrenceof an external interrupt requestora
Resetto exit the STOP state. the STOP stateis exited duetoa Reset (by acti-
vating the external pin) the MCU will entera nor-
mal reset procedure. Behaviourin responsetoin-
terrupts depends on the stateof the processor
core priorto issuing the STOP instruction, and
alsoon the kindof interrupt request thatis gener-
ated.
This case will be describedin the following para-
graphs. The processor core generatesa delay af-
ter occurrenceof the interrupt request,in orderto
waitfor complete stabilisationof the oscillator, be-
fore executing the first instruction.
32/72
ST62T40B/E40B
POWER SAVING MODE (Cont’d)
3.5.3 Exit from WAIT and STOP Modes
The following paragraphs describe how the MCU
exits from WAIT and STOP modes, whenan inter-
rupt occurs (nota Reset).It should be noted that
the restart sequence dependson the original state the MCU (normal, interruptor non-maskablein-
terrupt mode) priorto entering WAIT or STOP
mode,as wellason the interrupt type.
Interruptsdo not affect the oscillator selection.
3.5.3.1 Normal Mode the MCU wasin the main routine when the WAIT STOP instruction was executed, exit from Stop Wait mode will occuras soonasan interrupt oc-
curs; the related interrupt routineis executed and, completion, the instruction which follows theSTOPor WAIT instructionis then executed, pro-
vidingno other interrupts are pending.
3.5.3.2 Non Maskable Interrupt Mode the STOPor WAIT instruction has been execut- during executionof the non-maskable interrupt
routine, the MCU exits from the Stopor Wait modeas soon as an interrupt occurs: the instruction
which follows the STOPor WAIT instructionis ex-
ecuted, and the MCU remains innon-maskablein-terrupt mode, evenif another interrupt has been
generated.
3.5.3.3 Normal Interrupt Mode the MCU wasin interrupt mode before the STOP WAIT instruction was executed,it exits from
STOPor WAIT modeas soonasan interrupt oc-
curs. Nevertheless, two cases must be consid-ered:If the interruptisa normal one, the interrupt rou-
tinein which the WAITor STOP mode was en-
tered will be completed, starting with the
executionof the instruction which follows the
STOPor the WAIT instruction, and the MCUis
stillin the interrupt mode.At the endof this rou-
tine pending interrupts willbe servicedin accord-
ance with their priority.In the eventofa non-maskable interrupt, the
non-maskable interrupt service routineis proc-
essed first, then the routinein which the WAITor
STOP mode was entered will be completedby
executing the instruction following the STOPor
WAIT instruction. The MCU remainsin normal
interrupt mode.
Notes: achieve the lowest power consumption during
RUNor WAIT modes, the user program must take
careof: configuring unused I/Osas inputs without pull-up
(these should be externally tiedto well defined
logic levels); placing all peripheralsin their power down
modes before entering STOP mode;
When the hardware activated Watchdogis select-
ed,or when the software Watchdogis enabled, theSTOP instructionis disabled anda WAIT instruc-
tion willbe executedinits place.all interrupt sources are disabled (GEN low), the
MCU can only be restartedbya Reset. Although
setting GEN low does not mask the NMIasan in-
terrupt,it will stopit generatinga wake-up signal.
The WAIT and STOP instructions are not execut-ifan enabled interrupt requestis pending.
33/72
ST62T40B/E40B ON-CHIP PERIPHERALS
4.1 I/O PORTS
The MCU features Input/Output lines which may individually programmedas anyof the following
inputor output configurations: Input without pull-upor interrupt Input with pull-up and interrupt Input with pull-up, but without interrupt Analog input Push-pull output Open drain output
The lines are organisedas bytewise Ports.
Each portis associated with3 registersin Data
space. Each bitof these registersis associated
witha particular line (for instance, bits0of PortA
Data, Direction and Option registers are associat- with the PA0 lineof Port A).
The DATA registers (DRx), are usedto read the
voltage level valuesof the lines which have been
configuredas inputs,orto write the logic valueof
the signaltobe outputon the lines configuredas
outputs. The port data registers canbe readto get
the effective logic levelsof the pins, but they can also written by user software,in conjunction
with the related option registers,to select the dif-
ferent input mode options.
Single-bit operationson I/O registers are possible
but careis necessary because readingin input
modeis done from I/O pins while writing will direct- affect the Port data register causing an unde-
sired changeof the input configuration.
The Data Direction registers (DDRx) allow the
data direction (inputor output)of each pinto be
set.
The Option registers (ORx) are usedto select the
different port options available bothin input andin
output mode.
All I/O registers can be reador writtento justas
any other RAM locationin Data space,sono extra
RAM cells are needed for port data storage and
manipulation. During MCU initialization,all I/O reg-
isters are cleared and the input mode with pull-ups
andno interrupt generationis selected forall the
pins, thus avoiding pin conflicts.
Figure 18. I/O Port Block Diagram
VDDRESETSIN CONTROLS
SOUT
SHIFT
REGISTER
DATA
DATA
DIRECTION
REGISTER
REGISTER
OPTION
REGISTER
INPUT/OUTPUT INTERRUPT
VDD ADC
VA00413
34/72
ST62T40B/E40B
I/O PORTS (Cont’d)
4.1.1 Operating Modes
Each pin maybe individually programmedas input output with various configurations.
Thisis achievedby writing the relevantbitin the
Data (DR), Data Direction (DDR) and Option reg-
isters (OR). Table 13 illustrates the various port
configurations which canbe selectedby user soft-
ware.
4.1.1.1 Input Options
Pull-up, High Impedance Option. All input lines
canbe individually programmed withor withoutan
internal pull-upby programming the OR and DR
registers accordingly.If the pull-up optionis not
selected, the input pin willbein the high-imped-
ance state.
4.1.1.2 Interrupt Options
All input lines can be individually connected by
softwareto the interrupt systemby programming
the OR and DR registers accordingly. The inter-
rupt trigger modes (falling edge, rising edge and
low level) can be configured by software as de-
scribedin the Interrupt Chapter for each port.
4.1.1.3 Analog Input Options
Some pins canbe configuredas analog inputsby
programming the OR and DR registers according-
ly. These analog inputs are connectedto the on-
chip 8-bit Analogto Digital Converter. ONLY ONE
pin should be programmedas an analog inputat
any time, since by selecting more than one input
simultaneously their pins willbe effectively short-
ed.
Table 13. I/O Port Option Selection
Note:X= Don’t care
DDR OR DR Mode Option 0 0 Input With pull-up,no interrupt 0 1 Input No pull-up,no interrupt 1 0 Input With pull-up and with interrupt 1 1 Input Analog input (when available) 0 X Output Open-drain output (20mA sink when available) 1 X Output Push-pull output (20mA sink when available)
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ST62T40B/E40B
I/O PORTS (Cont’d)
4.1.2 Safe I/O State Switching Sequence
Switching the I/O ports from one stateto another
shouldbe doneina sequence which ensures that unwanted side effects can occur. The recom-
mended safe transitions are illustratedin Figure
19. All other transitions are potentially risky and
shouldbe avoided when changing the I/O operat-
ing mode,asitis most likely that undesirable side-
effects willbe experienced, suchas spurious inter-
rupt generationor two pins shorted togetherby the
analog multiplexer.
Singlebit instructions (SET, RES, INC and DEC)
should be used with great caution on Ports Data
registers, since these instructions makean implicit
read and write backof the entire register.In port
input mode, however, the data register reads from
the input pins directly, and not from the data regis-
ter latches. Since data register informationin input
modeis usedto set the characteristicsof the input
pin (interrupt, pull-up, analog input), these maybe
unintentionally reprogrammed depending on the
stateof the input pins.Asa general rule,itis better limit the useof singlebit instructions on data
registersto when the whole (8-bit) portisin output
mode.In the caseof inputsorof mixed inputs and
outputs,itis advisableto keepa copyof the data
registerin RAM. Single bit instructions may then used on the RAM copy, after which the whole
copy register canbe writtento the port data regis-
ter:
SET bit, datacopy a, datacopy DRA,a
Warning: Care must also be takento not usein-
structions that act ona whole port register (INC,
DEC,or read operations) whenall8 bits are not
available on the device. Unavailable bits must be
maskedby software (AND instruction).
The WAIT and STOP instructions allow the
ST62xxto be usedin situations where low power
consumptionis needed. The lowest power con-
sumptionis achievedby configuring I/Osin input
mode with well-defined logic levels.
The user must take care notto switch outputs with
heavy loads during the conversionof oneof the
analog inputsin orderto avoid any disturbanceto
the conversion.
Figure 19. Diagram showing Safe I/O State Transitions
Note*. xxx= DDR, OR, DR Bits respectively
Interrupt
pull-up
Output
Open Drain
Output
Push-pull
Input
pull-up (Reset
state)
Input
Analog
Output
Open Drain
Output
Push-pull
Input
010*
111
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ST62T40B/E40B
I/O PORTS (Cont’d)
Table 14. I/O Port configuration for the ST62T40B/E40B
Note1. Providedthe correct configurationhas been selected.
MODE AVAILABLE ON(1) SCHEMATIC
Input
PA0-PA7
PB0-PB7
PC0-PC7
Input
with pullup
(Reset state exceptfor
PC0-PC7)
PA0-PA7
PB0-PB7
PC0-PC7
Input
with pullup
with interrupt
PA0-PA7
PB0-PB7
PC0-PC7
Analog Input PA0-PA7
PB0-PB3
Open drain output
5mA
Open drain output
20mA
PA0-PA7
PB0-PB7
PC0-PC7 (1mA)
PB4-PB7
Push-pull output
5mA
Push-pull output
20mA
PA0-PA7
PB0-PB7
PC0-PC7 (1mA)
PB4-PB7
Datain
Interrupt
Datain
Interrupt
Datain
Interrupt
Data out
ADC
Dataout

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