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1.1 INTRODUCTION . ..
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1.1 INTRODUCTION . ..
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STP40NF03L. ,NSTP40NF03L®N - CHANNEL 30V - 0.020 Ω - 40A TO-220STripFET™ POWER MOSFETTYPE V R IDSS DS(on) DSTP ..
STP40NF10 ,N-CHANNEL 100VSTP40NF10STB40NF10 - STB40NF10-12 2N-CHANNEL 100V - 0.024Ω - 50A TO-220/D PAK/I PAKLOW GATE CHARGE ..
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STP40NF12 ,N-CHANNEL 120VABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V =0) 120 VDS GSV Drain- ..
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ST6215CM1-ST6225CM6-ST62E25CF1-ST62T15CB6-ST62T15CB6.-ST62T15CM6-ST62T25CB6-ST62T25CM6
8-BIT MICROCONTROLLER ( MCU ) WITH OTP, ROM, FASTROM, EPROM, A/D CONVERTER, OSCILLATOR SAFEGARD, SAFE RESET AND 28 PINS
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ST6215C/ST6225C
8-BIT MCUS WITH A/D CONVERTER,
TWO TIMERS, OSCILLATOR SAFEGUARD & SAFE RESET
n Memories
-2k or 4K bytes Program memory (OTP,
EPROM, FASTROM or ROM) with read-out
protection
- 64 bytes RAM
a Clock, Reset and Supply Management
- Enhanced reset system
- Low Voltage Detector (LVD) for Safe Reset
- Clock sources: crystal/ceramic resonator or
RC network, external clock, backup oscillator
(LFAO)
- Oscillator Safeguard (OSG)
- 2 Power Saving Modes: Wait and Stop
Interrupt Management
- 4 interrupt vectors plus NMI and RESET
- 20 external interrupt lines (on 2 vectors)
- 1 external non-interrupt line
a 20 I/O Ports
- 20 multifunctional bidirectional l/O lines
- 16 alternate function lines
- 4 high sink outputs (20mA)
2 Timers
- Configurable watchdog timer
- 8-bit timer/counter with a 7-bit prescaler
Analog Peripheral
- 8-bit ADC with 16 input channels
Instruction Set
- 8-bit data manipulation
- 40 basic instructions
- 9 addressing modes
- Bit manipulation
Device Summary
CDIP28W
(See Section 12.5 for Ordering Information)
II Development Tools
- Full hardware/software development package
July 2001
ST62T150(OTP) ST62T25C(OTP)
Features ST6215C(ROM) ST6225C(ROM) ST62E25C(EPROM)
ST62P15C(FASTROM) ST62P25C(FASTROM
Program memory - bytes 2K 4K
RAM - bytes 64
Operating Supply 3.0V to 6V
Clock Frequency 8MHz Max
Operating Temperature -40°C to +125°C
Packages PDIP28 / SO28/ SSOP28 CDIP28W
Rev. 3.2
Table of Contents
1 INTRODUCTION w............................................................. 6
2 PIN DESCRIPTION M........................................................... 7
3 MEMORY MAPS, PROGRAMMING MODES AND OPTION BYTES ...................... 9
3.1 MEMORY AND REGISTER MAPS .......................................... 9
3.1.1 Introduction w....................................................... 9
3.1.2 Program Space .................................................... 11
3.1.3 Readout Protection w................................................ 11
3.1.4 Data Space M...................................................... 11
3.1.5 Stack Space ....................................................... 11
3.1.6 Data ROM Window Mechanism ........................................ 13
3.2 PROGRAMMING MODES ................................................ 15
3.2.1 Program Memory ................................................... 15
3.2.2 EPROM Erasing .................................................... 15
3.3 OPTION BYTES w...................................................... 16
4 CENTRAL PROCESSING UNIT ................................................. 17
4.1 INTRODUCTION _...................................................... 17
4.2 MAIN FEATURES ...................................................... 17
4.3 CPU REGISTERS ...................................................... 17
5 CLOCKS, SUPPLY AND RESET ................................................ 19
5.1 CLOCK SYSTEM w...................................................... 19
5.1.1 Main Oscillator _.................................................... 20
5.1.2 Oscillator Safeguard (OSG) ........................................... 21
5.1.3 Low Frequency Auxiliary Oscillator (LFAO) ............................... 22
5.1.4 Register Description ................................................. 22
5.2 LOW VOLTAGE DETECTOR (LVD) ........................................ 23
5.3 RESET ............................................................... 24
5.3.1 Introduction ....................................................... 24
5.3.2 RESET Sequence .................................................. 24
5.3.3 RESET Pin ........................................................ 25
5.3.4 Watchdog Reset P.................................................. 26
5.3.5 LVD Reset _....................................................... 26
6 INTERRUPTS ............................................................... 27
6.1 INTERRUPT RULES AND PRIORITY MANAGEMENT ......................... 29
6.2 INTERRUPTS AND LOW POWER MODES .................................. 29
6.3 NON MASKABLE INTERRUPT ............................................ 29
6.4 PERIPHERAL INTERRUPTS ............................................. 29
6.5 EXTERNAL INTERRUPTS (IIO PORTS) .................................... 30
6.5.1 Notes on using External Interrupts ...................................... 30
6.6 INTERRUPT HANDLING PROCEDURE ..................................... 31
6.6.1 Interrupt Response Time ............................................. 31
6.7 REGISTER DESCRIPTION w.............................................. 32
