ST5451D ,ISDN HDLC AND GCI CONTROLLERST5451 ISDN HDLC AND GCI CONTROLLERMONOLITHIC ISDN ORIENTED HDLC ANDGCI CONTROLLER.GCI AND μW/DSI ..
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ST5771-1 ,PNP Switching Transistorapplications at currents to 100mA. Sourced from Process 65.See PN4258 for characteristics.Absolute ..
ST5771-1 ,PNP Switching Transistorapplications involving pulsed or low duty cycle operations.Thermal Characteristics TA = 25°C u ..
ST5R30MTR ,MICROPOWER VFM STPE-UP DC/DC CONVERTER
ST5R33MTR ,MICROPOWER VFM STPE-UP DC/DC CONVERTER
STN4NE03L ,N-CHANNEL 30V
STN715 ,NPN MEDIUM POWER TRANSISTORSSTF715STN715®NPN MEDIUM POWER TRANSISTORSType MarkingSTF715 715STN715 N7152■ SURFACE-MOUNTING DEVIC ..
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STN878 , Medium current, high performance, low voltage NPN transistor
STN8810B3HSBE , Mobile multimedia application processor
STN8810B3HSBE , Mobile multimedia application processor
ST5451D
ISDN HDLC AND GCI CONTROLLER
ST5451ISDN HDLC AND GCI CONTROLLER
MONOLITHIC ISDN ORIENTED HDLC AND
GCI CONTROLLER.
GCI AND μW/DSI COMPATIBLE.
FULLY CONTROLLING GCI AND GCI-SCIT& C/I CHANNELS MANAGEMENT.
FULLY SUPPORTING LAPB AND LAPD PRO-
TOCOL ONB ORD CHANNEL.
EASILY INTERFACEABLE WITH ANY KIND STANDARD NON MULTIPLEXED OR
MULTIPLEXED BUS MICROPROCESSOR.
DMA ACCESS WITH MULTIPLEXED BUSμP
CAN HANDLE AND STORE AT THE SAME
TIME TWO FRAMES IN TRANSMISSION
(64bytes FIFO Tx) AND EIGHT FRAMES IN
RECEPTION (64bytes FIFO Rx)
COMPATIBLE WITH ALL THE STMicroelec-
tronics ISDN PRODUCT FAMILY.
GENERAL DESCRIPTIONST5451 HDLC and GCI controllerisa CMOS cir-
cuit fully developed by STMicroelectronics and
diffusedin advanced 1.2 μm HCMOS3 technol-
ogy.
The deviceis intendedtobe used mainlyin ISDN
applications,in Terminal (TE) andin Line Termi-
nations (LT).
ST5451 can handle HDLC packets either on
16Kbit/sD channelor64 Kbit/sB channel;it can
work witha wide range of PCM signals go-
ing from GCI (General Circuit Interface)to DSI
(Digital System Interface) to any PCM-like
stream.
ST5451isa complete GCI controller designedto
comply with the GCI and GCI-SCIT (Special Cir-
cuit Interface for Terminal) completely handling
Monitor (M) and Command/Indicate (C/I) chan-
nels.
ST5451 can be easily controlledby many differ-
ent kindof microprocessorsor microcontrollers
having either non-multiplexedor multiplexed bus
structure.
ST5451 canbe usedin connectionwith ST5420/1 Interface Devices (SID-μW and SID-GCI) and
ST5080 Programmable ISDN Combo (PIC)in
Terminals and with ST5410U Interface Device
(UID)in Line Terminations.
March 2000
PIN CONNECTION (Top view)
SO28
ORDERING NUMBER: ST5451D1/34
BLOCK DIAGRAM
PIN DESCRIPTION
NAME PIN TYPE FUNCTION 1 I Chip Select.A lowlevel enables ST5451for read/write operations.
INT 25 O Interrupt requestis assertedby ST5451 whenit requesta service.
Open drain output.
MULT 2 I
Multiplexed Bus. Indicates the μP bus interface selected.
MULT=1: multiplexed bus and DMA available.
MULT=0: address and data busseparated.
I/M 4 I Intel/Motorola. When MULT=1 thispin selectseither Intelor
Motorola 6805 bus.
ST54512/34
DEMULTIPLEXED MICROPROCESSOR BUS INTERFACE (MULT=0)
NAME PIN TYPE FUNCTIONA0/A5 3-8 I Address Bus.To transfer addresses fromμPto ST5451.
D0/D7 17-24 I/O Data Bus.To transfer data betweenμP and ST5451.
R/W 27 I Read/Write.”1” indicatesa read operation;”0”a write operation.
E26 I Enable. Read/write operations are synchronized with thissignal;its
falling edge marks the endofan operation.
MULTIPLEXED MICROPROCESSOR BUS INTERFACE (MULT=1 I/M=1)
NAME PIN TYPE FUNCTIONAD0/AD7 17-24 I/O Address Data Bus.To transfer addresses and data betweenμP
and ST5451. 27 I Write. This signal indicatesa write operation. 26 I Read. This signal indicatesa read operation.
ALE 3 I Falling edge latches the address from the external A/D Bus.
MULTIPLEXED MICROPROCESSOR BUS INTERFACE (MULT=1; I/M=0)
NAME PIN TYPE FUNCTIONAD0/AD7 17-24 I/O Address Data Bus.To transfer addresses and data betweenμP
and ST5451.
R/W 27 I Read/Write.”1” Indicatesa write operation;”0”a write operation. 26 I Data Strobe. Read/Write operations are synchronized with this
signal:its falling edge marks the end ofan operation. 3 I Address Strobe. Fallingedge latches the address from the external
A/D Bus.
DMA (direct memory access):only whenMULT=1
NAME PIN TYPE FUNCTIONDMA REQX
DMA REQR
Direct Memory Access Requests: these outputs are assertedby
the deviceto requestan exchangeof byte from the memory.
DMA ACKX
DMA ACKR
Direct Memory Access Acknowledge: these inputs are assertedby
the DMA controllerto signaltothe HDLC controller thata byteis
being transferredin responsetoa previous transfer request.
GCI INTERFACE
NAME PIN TYPE FUNCTIONDOUT 15 I/O
Data output forB andD channels.In GCI modeit outputs B1,
B2,M andC/I channels. InTE mode (GCI-SCIT)it can invertto
input dataforM’ and C/I’ channels (See Table2).
DIN 12 I/O
Data inputforB andD channels.In GCImodeit inputs B1, B2,M
andC/I channels.In TE mode (GCI-SCIT)it can invert tooutput
dataforM’ and C/I’ channels (See Table2).
CLK 11 I Data Clock.It determines the data shift ratefor GCI channelson
the module interface. 13 I
Frame synchronization. This signalisa8 kHz signalfor frame
synchronization. The front edge givesthe time referenceof the first
bitin the frame.
DEN 10 I
Data Enable.InTE mode, this pinisa normally low input pulsing
highto indicate the activebit timesforD channel transmitat DOUT
pin.Itis intendedtobe gated with CLKto controlthe shiftingof
data from HDLC controllertoS interface device.
ST54513/34
- FUNCTIONS-1- Basic HDLC Functions-1-1-In Receive Direction: Channel selection GCI channelB1or B2orD maybe selected.or B2 may be selected withoutM and C/Ichannels Flag detection zero followedby six consecutiveones and an-
other zerois recognizedasa flag Zero delete zero, after five consecutive ones within an
HDLC frame,is deleted CRC checking
The CRC fieldis checked accordingto the gen-
erator polynomial16 +X12 +X5 +1 Checkfor abort
Sevenor more consecutiveones are interpretedan abort flag Checkfor idle
Fifteen or more consecutive ones are inter-
pretedas ”idle” Minimum lenght checking
HDLC frames with less thann bytes between
start and end flag are ignored: allowed val-
ues are3 ≤ n≤6.
This valueis setbya programmable register Address Field recognition SAPI and/or3 TEI maybe recognized. Sev-
eral programmable registers indicate the recog-
nized address types.-1-2-In Transmit Direction: Shift controlin TE mode channeldata are signalledby DEN pin. Flag generation flagis generatedat the beginning andat the
endof every frame. Zero insert zerois inserted after five consecutive ones
withinan HDLC frame CRC generation
The CRC fieldof the transmitted frameis gener-
ated accordingto the generatorpolynomial16 +X12 +X5 +1 Abort sequence generation HDLC frame may be terminated with an
abort sequence under microprocessorcontrol Interframetimefill
Flagsor idle (consecutive ones) may be trans-
mitted during the interframe time.A programma-
blebit selects the mode.
NON GCI INTERFACE
NAME PIN TYPE FUNCTIONDOUT 15 O
Data output. Digital outputfor serial data. Three modes: HDLC Protocol multiplexed link HDLC Protocol non multiplexed link Non HDLC protocol (transparent Mode).
DIN 12 I Data input. Digital inputfor serial data. Three modes (See DOUT).
CLK 11 I Data Clock.It determines the data shift rate. Two modes: Singleor
doublebit rate. 13 I
Frame synchronization. Usedin mode HDCL protocol multiplexed
link. Don’t carein other modes. The rising edge givesthe time
referenceofthe firstbitofthe frame.
DEN 10 I Data Enable. When high, enable the data transfer.on DOUT
OTHERS
NAME PIN TYPE FUNCTIONVDD 28 I Positive power supply=5V +5%
VSS 14 I Signal ground
RST 16 I Reset 9 I Special Test. (Reserved) mustbe tiedto VSS
ST54514/34
-2- FIFO Structure-2-1- Receive FIFO Structure receive direction,a 64 byte FIFO memoryisused.Itis dividedin8 blocksof8 bytes automat-
ically chained. caseofa frame lengthof64 bytesor less, the
whole frame can be storedin the FIFO. After the
first 32 bytes have been received μPis inter-
rupted and may read the available data. caseof frames longer than 64 bytes, the μPis
interruptedto read out the FIFOby32 byte block. caseof several short frames,upto eight maybe
stored inside the FIFO. Afteran interrupt, one frame available for the μP. The eventual other seven
framesarequeuedandtransferredoneby one.-2-2- TransmitFIFO Structure transmit direction,a 64 byte FIFO memoryis
used, structuredin2 blocksof 32 bytes. ST5451 requestedto transmit after32 bytes have been
written into the FIFO.a transmission request does not includea mes-
sage end, the HDLC controller will request the
next data blockbyan interrupt.-3- Microprocessor Interface
Three types of microprocessor interfaces are
available (MULT and I/M control pins set the de-
sired interface). Motorola non multiplexed families. Motorola multiplexed family (6805 type) Intel family.
You can connect ST5451toa Direct Memory Ac-
cess Controller as MC68440or MC6450 (dualor
quad channels). programmable register indicates DMA Interface
enabling.
TABLE1- ST5451 Internal Registers
Address Hexa Read Write Receive FIFO Transmit FIFO - - ISTA0 ISTA0 ISTA1 ISTA1 ISTA2 ISTA2 STAR CMDR MODE MODE RFBC TSR CA CA CB CB CC CC CD CD CE CE CF CF CIR1 CIX1 CIR2 CIX2 MONR1 MONX1/0 - MONX1/1 MONR2 MONX2/0 - MONX2/1 - MASK0 - MASK1 - MASK2 CCR CCR
ST54515/34
TABLE2- CHANNEL ASSIGNMENT SELECT
ST54516/34
- REGISTER DESCRIPTIONForall the register pictures MSBis on the left and
LSBon the right
Ifnot otherwisestatedbit are considered activeat1.
FIFOSRFIFO (read), XFIFO (write).
The address rangeof the two FIFOs are identical.
All the 32 addresses give accessto the ”current”
FIFO location.
When the closing Flagofa receive frameis de-
tected,a status byteis availablein the RFIFO.
This byte has the following format:
RBC RDO CRC RAB 0 0 0 0
RBC Receive Byte Count.
The lengthof the received frameisn
time8 bits (n=3,4,5,...)
RDO Receive Data Overflow partof the frame has not been lost
because the receiveFIFO was full
CRC CRC Check
The receivedCRCbytes were notcorrect
RAB Receive Abort
The received frame was not aborted status byte equalto D0H indicatesa correctly
received frame
ISTA0 Interrupt Status Register0
After RESET 10H
RME RPF RFO XPR XDU EXI2 EXI1 0
RME Receive Message End
One complete frameof length less than equalto 32 bytes,or the last partof frameof length greater than32 bytes storedin the RFIFO.
RPF Receive Pool Full bytesofa frame arein RFIFO. The
frameis not yet completelyreceived.
RFO Receive Frame Overflow complete frame was lost becauseno
storage space was availablein the
RFIFO.
XPR Transmit Pool Ready
One data block (32 bytes max) maybe
entered into the XFIFO.
XDU Transmit Data Underrun transmitted frame was terminated
with an abort sequence because no
data were available for transmissionin
XFIFO and no XME command was is-
sued.Itis not possible to transmit
frame when that interrupt remains un-
acknowledged and XRES has not been
set.
EXI2 ExtendedInterrupt2
The interrupt reasonis indicatedin reg-
ister ISTA2
EXI1 ExtentedInterrupt1
The interrupt reasonis indicatedin reg-
ister ISTA1.
ISTA1 Interrupt Status Register1
After RESET 01H
(GCI mode only) 0 CIC1 EOM1 XAB1 RMR1 RAB1 XMR1
CIC1 Comman/IndicateChange changein the valueof CIR1is de-
tected
EOM1 Endof Message1 (monitor channel)
MON1 has received an endof mes-
sage.
XAB1 Monitor Transmit ABORT
The received byte has not been de-
tectedin two successiveframes.
MON1 has sent an ABORT(A bit)to
the remote transmitter.
RMR1 Receive Monitor Register1 ready byte has been receivedin register
MONR1.
RAB1 Receive Abort
MON1 receivedan ABORT from the re-
mote receiver.
XMR1 Transmit Monitor Register1 ready byte can be stored in register
MONX1
ISTA2 Interrupt Status Register2
After RESET 01H
(GCI and TE modeonly) 0 CIC2 EOM2 XAB2 RMR2 RAB2 XMR2
CIC2 Command/Indicate Change changein the valueof CIR2is de-
tected.
ST54517/34
EOM2 Endof Message2 (monitor channel)
MON2 has received an endof mes-
sage.
XAB2 Monitor Transmit ABORT
The received byte has not been de-
tectedin two successive frames.
MON2 has sent an ABORT(A bit)to
the remote transmitter.
RMR2 Receive Monitor Register2 ready byte has been receivedin register
MONR2.
RAB2 Receive ABORT
MON2 receivedan ABORT from the re-
mote receiver.
XMR2 Transmit Monitor Register2 ready byte can be stored in register
MONX2.
MASK0, MASK1, MASK2After Reset FF; the three mask registers MASK0,
MASK1, MASK2 are associated respectivelyto
the three interrupt registers ISTA0, ISTA1,and
ISTA2.
Each interrupt sourcein ISTA registers canbe se-
lectively maskedby settingto ”1” the correspond-
ing bitin MASK1. Interrupt sources (maskedor
not) are indicated when ISTAis readby the mi-
croprocessor. When an interrupt sourceis not
masked, INT goes low.
STAR Status Register
After Reset 48H
XDOV XFW IDLE RLA DCIO 0 0 0
XDOV Transmit Data Overflow
More than 32 bytes have been written
into the XFIFO.
XFW XFIFO Write enable
Data canbe entered into the XFIFO.
IDLE IDLE State or more consecutive ones have
been detectedon the input data line.
RLA Receive Line Active
Framesor interframe flags are being
received
DCIO D and C/I Channels are occupied
CMDR Command Register
After Reset00
XHF XME RMC RMD RHR XRES M2RES M1RES
XHF HDLC frame transmission can start.
XME Transmit Message End
The last partof the frame was entered XFIFO and canbe sent.
RMC Receive Message Complete
Reactionto RPFor RME interrupt. The
received frame (or one poolof data)
has been read and the corresponding
RFIFOis free.
RMD Receive Message Delete
Reactionto RPFor RME interrupt. The
entire frame will be ignored. The partof
frame already storedis deleted.
RHR Reset HDLC receiver
XRES Reset HDLC transmitter
XFIFOis cleared and the transmitted
frame(if any)is aborted.
M2RES Monitor2 Reset
Reset MONITOR and C/I channels (TX
and RX).
M1RES Monitor1 Reset
Reset MONITOR and C/I channels (TX
and RX). For the four first bits (XHF, XME, RMC,
RMD), the resetis doneby the device;
the other bitslevel sensitive
MODE HDLC Mode Register
After Reset00
DMA FL1 FL0 ITF RAC CAC NHF FLA
DMA DMA Interface activation
FL1/0 Frame Length
Minimum frame length accepted
FL1 FL0 bytes bytes bytes bytes
ITF InterframeTime Fill
ITF=1: Flags are transmitted
ITF=0: IDLEis transmitted
RAC RAC=1: Activate RX
RAC=0: deactivate RX
ST54518/34
CAC Channel Activation
CAC=1: Activate RX and TX
CAC=0: deactivate RX and TX
NHF HDLC Function Select
NHF=1: disable HDLC function
FLA Flag
FLA=1: transmit shared flags
FLA=0: transmit two flags between
consecutiveframes.
RFBC Receive Frame Byte Counter
After reset00
RDC7 RDC6 RDC5 RDC4 RDC3 RDC2 RDC1 RDC0
RDC 0/7 Receive Data Count
Total number of bytes of received
frame without CRC.
RDC 0/4 Indicate the numberof bytesin the cur-
rent block availablein RFIFO.
RDC 5/7 Indicate the numberof32 bytes blocks
received.If the frame exceeds 223
bytes, RDC 5/7 hold the value ”111”,
only RDC 4/0 continueto count modulo
See Table3.
The contentsof the register are valid after an
RME interrupt. The μP must read N+1 bytesto
transfer the numberof bytes received and the
status byte into the memory.
CIX1 Command/Indicate TransmitRegister1
After reset FFH
(GCI only) 1 1 1 C1C2 C3C4
C1, C2, C3, C4:
Code to be transmitted permanently the outgoing GCI C/I channel.
CIR1 Command/Indicate Receive Register1
After reset FFH
(GCI only) 1 1 1 C1C2 C3C4
C1, C2, C3, C4:
Incoming GCI C/I channel.
MONX1 Monitor Transmit Register1
After reset FFH
(GCI only) M2 M3 M4 M5 M6 M7 M8
The value writtenin MONX1is trans-
mittedin the outgoing Monitor channel
according to GCI transfer protocol.
XMR1 interrupt indicates when MONX1 again available.
MONR1 Monitor Receive Register1
After reset FFH
(GCI only) M2 M3 M4 M5 M6 M7 M8
The value read from MONR1 gives the
valueof the byte receivedin the moni-
tor channel accordingto GCI transfer
protocol. RMR1 interrupt indicates
whena new byte is available in
MONR1 register.
CIX2 Command/Indicate Transmit Register2
After Reset FFH
(GCI and TE modeonly) 1 P1 P2 P3 P4 P5 P6
P1/P6 Code transmitted permanentlyin the
2nd GCI C/I channel.
CIR2 Command/Indicate Receive Register2
After reset FFH
(GCI and TE modeselected only) 1 P1 P2 P3 P4 P5 P6
P1/P6 The contentsof the 2nd C/I channel;
they are the different requests received
from TE peripheral devicesto μP.
Six peripherals can makea simultane-
ous request.
MONX2 Monitor Transmit Register2
After reset FFH
(GCI and TE modeonly)
The value writtenin MONX2is trans-
mittedin the 2nd GCIM channeltoa
peripheral(if PI=1; register CF).
ST54519/34
MONR2 Monitor Receive Register2
After reset FFH
(GCI and TE mode only)
The value read from MONR2 gives the
value of the byte received fromM
channelin 2nd GCI channel.
TSR Time Slot Register
After reset00
TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0 GCI mode (MDS1=1in CF Register) CCS=1in CF Reg. (64 Kbit/s)
Then: TSR2 indicatesB1or B2
TSR4/7 indicate positionof
GCI channel CCS=0in CF Reg. (16 Kbit/s)
Then: TSR4/7 indicate positionof
GCI anditsD channel Multiplexed Mode
(MDS1=0in CF Register) CCS=1in CF Reg. (64 Kbit/s)
Then: TSR2/7 indicate channel
positionin the64 time slots
multiplex CCS=0in CF Reg. (16 Kbit/s)
Then: TSR0/7 indicate channel
positionin the 256 time slots
multiplex. Configurationn RegisterA
After reset00
CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
CA0 SAPI0is recognized CA0=1
CA1 SAPI63 CA1=1
CA2 SAPIx CA2=1
CA3 SAPIy CA3=1
CA4 TEI 127 CA4=1
CA5 TEIz CA5=1
CA6 TEIt CA6=1
CA7 Address filter active CA7=1 Configuration registerB
After reset00
Contentof CB indicate SAPIx value
HighOrder6 Bits
SAPI 0 0 Configuration RegisterC
After reset00
Contentof CC indicate SAPIy value
HighOrder6 Bits
SAPI 0 0
(numberof bytesin the
frame received without CRC)
Counter n (numberof32 bytes blocks
received)765 43210 m n Min 000 00001 0 000 00010 0 000 00011 0 000 11110 0 000 11111 0 001 00000 1 001 00001 1 001 11110 1 001 11111 1 010 00000 2
222 110 11110 6
223 110 11111 6
224 111 11111 7
256 111 00000 7
257 111 00001 7 111 - 7
TABLE3
ST545110/34
Configuration RegisterDAfter reset00
Contentof CD indicate TEIz value. High Order Bits
TEI 0 Configuration RegisterE
After reset00
Contentof CE indicate TEIt value. High Order Bits
TEI 0 Configuration RegisterF
After00 MAS/SSC CCS CMS/SCPI VZDOUT MDS1 MDS0 TE mode=1: the frameis constitued by
three GCI channels (GCI-SCIT)
MAS/SSCIf CCS=0, TE=1, MDS0 and MDS1=1
(i.e. GCI mode, TE mode,16 Kbit/s)
MAS/SScis MAS and:
MAS=0 means ”Slave device”
MAS=1 means ”Master device” SC=1 (i.e.a sub-channelis se-
lected) MAS/SSCis SSC;if 16Kbis se-
lected SSC chooses between first on
secondbitof the stream while,if 64Kb selected SSC chooses between first last seven bitsof the stream (see
TABLE2 and CMS/SC)
CCS Channel Capacity Selection
CCS=1:64 Kb/s
CCS=0:16 Kb/s.
CMS/SCIf CCS=0, TE=1, MDS0 and MDS1=1
(i.e. GCI mode, TE mode, 16Kbit/s)
CMS/SCis CMS (Contention mode se-
lection) and:
CMS=1 means”D and C/I channel
access procedure active”
CMS=0 means”D and C/Z channel
access procedure active” CCS=1 and TE=1 CMS/SCis SC
(Subchannel) and:=0 means ”16Kbit/sor 64Kbit/sis
used”=1 means ”an 8Kbit/sor 56Kbit/s
subchannelinsidea 16Kbit/sor
64kbit/sis used” (see MAS/SSC) Peripheral Interface (onlyif TE=1)=1: CIX2, CIR2, MONX2, MONR2,
active
VZDOUT When level1 deviceis inactive (i.e.
CIR1=DI= 1111) and GCI hastobe
wakenup (i.e. TIM= 0000in CIX1),
DOUTis setto zero requiring FS
and CLK if VZ DOUT=1.
MDS1 ModeBit1
MDS1= 1:GCI mode
MDS1=0: Multiplexed mode
MDS0 ModeBit0
MDS0= 1: Multiplexer and Demulti-
plexer are active.
MDS=0 No multiplexer.
CCR Configuration Register00
After reset00
TLP ADDR AD3 AD2 AD1 AD0 CRS TRI
TLP Test Loop
TLP=1: The transmitteris internally
connectedto the receiver; the transmit
outputis not activated. The digital inter-
face must be activatedto provide the
bit clock and frame Synchro.
ADDR Address Recognized TE=1 andPI=1
ADDR=1: The first byte receivedin
MONR2is compared with AD0/3.If
equal the messageis accepted, other-
wiseis ignored.
ADDR=0: The messageis always ac-
cepted.
AD0/3 When PI=1,is the component ad-
dress.
AD0/2 Addressbit usedto accessD and C/I
channels (TE= CMS =1, CCS=0).
CRS Clock Rate Selection
CRS=1: Clock frequencyis twice the
data rate (GCI).
CRS=0: Clock frequency and data
rate are identical.
TRI Tristate
TRI=1: DOUTin tristate
TRI=0: DOUTin open drain.
ST545111/34
- WORKING PROCEDURES-1- RECEIVE FRAMERecognized frame (by meansof SAPI and/or TEI
identification), havinga minimum lengthis stored the RFIFO withall bytes between the opening
flag and CRC field.
When the frameis less thanor equalto 32 bytes, transferredin one block, and just after the re-
ceiving completion interrupt (RME),a status byte appendedat the end. The frame andits status
byte remain stored until μP acknowledgement
(RMC).
When the frameis longer than32 bytes, blocksof bytes plus one remainder blockof lenght1to are transferredto the microprocessor. The re-
ceiving 32 byte block generatesa RPF interrupt
and the datain RFIFO remains valid until μPac-
knowledgement(RMC).
The μP can ignorea received frameby meaning
RMD (Receive Memory Delete), reactionto RPF RME. The partof frame already storedis de-
leted and the remainder frameis ignoredby the
HDLC Controller.
The last blockof the frame generates the RMEin-
terrupt.
RFBC register bits0to4 indicate the numberof
bytes currently storedin the RFIFO. Bits5to7 in-
dicate the total numberof 32 byte blocks already
received. Bits5to7 do not overflow. When the
counter status7 has been reached,it indicatesa
frame length greater than 223 bytes (see Table
3).
RFBC registeris valid only after the RME inter-
rupt and remains valid until RMC acknow-
ledgementby μP. each read accessby the μP, RFBC 5/7 bits re-
main unchanged, RFBC 0/4 bits are decreasedto
reach value0 when the whole blockis read.
Interrupts are queued inside the device. They are
sent oneby oneto the microprocessor after each
acknowledgement RMC.Ifa frameis lost be-
cause the RFIFO was full,a RFO interruptis gen-
erated.
Figure1: Receivingofan HDCL frame
ST545112/34
2- TRANSMIT FRAMEAfter pollingbit XFWor aftera XPR interrupt,up 32 bytes may be storedin XFIFO. Transmis-
sion begins after that XHF commandis issuedbyμP. ST5451 will request another data blockbyan
XPR interruptif the XFIFO contains less than 32
bytes.
When XMEis set,all remaining XFIFO bytes are
transmitted, the CRC field and the closing flag are
added. The HDLC controller then generatesa
new XPR interrupt. the XFIFO becomes empty while XME com-
mand has not been set, an abort sequenceis
generated, followed by interframe time fill and
XDU interruptis generated. frame may be aborted by XRES commandas
well.
Figure2: Transmissionofan HDCL frame
ST545113/34
-3- COMMAND/INDICATE PROCEDUREThe exchangeof informationin the C/I channel
runsas follows:
The two circuits (i.e. ST5421 and ST5451) con-
nected on the GCI interface send one each other permanent fourbit command codein C/I field.
RECEIVE C/I
The ST5451 storeson every framethe four bitsof
C/I channel coming from level1 circuitina first
register CIR. This valueis compared with the pre-
vious one.Ifa one new appears during two con-
secutive frames, this new valueis loadedin regis-
ter CIR1 anda CIC1 interruptis generated.
TRANSMIT C/I
The transmit register CIX1 can be writtenat any
timeby the μP.Its contentis continuously sentin
the C/I channel.
Note: The TIM command (0000) forcesa low
level on DOUT,if CIR1= DI (1111) when VZ
DOUT=1to require FS and CLK.-4- MONITOR CHANNEL
The GCI Monitor channel procedure allows full
duplex data transmission with acknowledgement
usingA bit.
MESSAGE RECEIVING interrupt (bit RMR1in ISTA1 register)is gen-
erated whena new byteis availablein register
MONR1.
ST5451 generates an interrupt bit (XAB1 in
ISTA1)ifit does not read twice the same bytes
meanwhile sending an ABORTto the remote
transmitter. performs an interrupt (EOMin ISTA1) also
whenit has received an End Of Message. Ac-
knowledgementto remote transmitteris sentif: the byte was received twice with the same value the microprocessor reads the previous byte
storedin register MONR1.
This procedure performs flow control betweenS
interface device and μP.
MESSAGE TRANSMISSION
ST5451generatesan interrupt (XMR1in ISTA1)
when register MONX1is available.
Writing register MONX1/0 generatesa message
transmission. When the last byteis storedin the
register MONX1/1, ST5451 sends the End of
Messageto remote receiver.If an Abortis re-
ceived, one interrupt (RAB1)is generated.-5-M’ and C/I’ CHANNELS
The procedure allowsa full duplex data transmis-
sion between microprocessor and the peripheral
devices connected on C/I’ local and M’ channel
throughGCI-SCIT channel1.
Receive Interrupton C/I’ (DOUTis aninput). new value on C/I’ indicatesto ST5451 master
that one devicein the terminal wantsto senda
message. Upto six peripherals may generate
suchan interruptto the microprocessor.
ST5451 writesat every frame the six bitsof C/I’
channel coming from peripheralsin registerCIR’.
This valueis compared with the previous one anda new one appears during two consecutive
frames,is loadedin register CIR2 and CIC2 inter-
rupt (ISTA2 register)is generated.μP may senda messageonM’ channel (DIN be-
comesan output)to allow the peripheral deviceto
transmit.
MESSAGETRANSMISSION ONM’ CHANNEL
ST5451 sets interrupt XMR2 (ISTA2 register)if
register MONX2/0is available. Writing MONX2/0
generatesa message transmission. When the
last byte is stored in register MONX2/1,
ST5451sends Endof Messageto remote periph-
eral. an ABORTis received, interrupt RAB2 (ISTA2
register)is issued. Then microprocessor may
sendits message again.
MESSAGERECEPTION ONM’ CHANNEL
Interruptbit RMR2 (ISTA2 register)is generated
whena new byteis availablein MONR2 register.
ST5451 sets interruptbit XAB2 (ISTA2 register)if does not read twice the same byte;in this case, sendsan ABORTto remote peripheral.
The controller generates interrupt bit EOM2
(ISTA2 register) when End Of Messageis re-
ceived.-6- ACCESS PROCEDURE TOD AND C/I
CHANNELS (GCI and TE mode selected only)to eight HDLC controllers may be connectedD channel and C/I channel.A contentionreso-
lution mechanismis usedif bit CMS (Contention
Mode Selection)is set.
The mechanism allowsto givean access without
losing data. access request may be generated,if CIX1
(Command/Indicate Register1) containsa differ-
ent code fromDI (1111). During the procedure,M
channel (withA andE bits) may be used. On in-
put DIN, the GCI controller checks the CMS4bit
(CMS channel- Third GCI channel) (see Fig.4).
CMS4 indicates the statusof C/I andD channels
CMS4=1 ”channels free”; CMS4=0 channels oc-
cupied. the channels are free, the HDLC controller
starts transmitting its individual address AD2 on
CMS1, AD1 on CMS2, AD0on CMS3.Ifan erro-
neous addressis detected, the procedureis ter-
minated immediately.If the complete address can read without error, theD and C/I channels are
occupied: the ST5451 transmits CMS4=0: The
HDLC controller which has the lowest address
has priority over the others.
The access requestis withdrawnif the HDLC
controller transmits codeDI= 1111. the CMS4bit
(CMS field)is set.
ST545114/34
Figure3: GCI-SCIT Frame Timing
Figure4: GCI-SCIT Channels Timing
ST545115/34
-7- DMA ACCESSThe HDLC controller hasa DMA interface which activated by DMA bitin MODE register.The
DMA interfaceis available only when multiplexed
busis selected. 5451 asserts DMA REQRor DMA REQXto
requestan exchangeof bytesbetween the FIFOS
and the external memory.
The external DMA controller asserts DMA ACKR DMA ACKXto access the FIFOS.
These signals are equivalentto E/DS/RD func-
tions.
During DMA access, CS/CE pin mustbe inactive; andE/DS/RD signals canbe present.
Outside DMA Access,all registers are accessible the μP except the FIFOS.
FRAME RECEPTION:
When one block has been storedin RFIFO, DMA
REQR pin goes low and RPF (or RME) interrupts
the μP. The DMA controller reads the RFIFO. Af-
ter the RME interrupt, the frame length will be
availablein RFBC register. The blockis acknow-
ledgedby RMC command.
FRAME TRANSMISSION:
Whena 32 byte blockis freein XFIFO, DMA re-
quest goes low and XPR interrupts the μP. The
DMA controller can write datain the XFIFO.At
the endof the frame, the μP send XMEto HDLC
controller; CRC and closing flag will be sent by
the HDLC controller.
Figure5:D and C/I channels Access Procedure
ST545116/34
-8- INTERRUPT PROCEDURE-8-1- HDLC CHANNELS-8-1-1- RECEIVEDIRECTION
RRE and RPF interruptsRPF bit (register ISTA0) set highto indicate the
HDLC controller has receiveda blockof32 bytes
whichis nota complete message.
Thisbit remains high untilitis erasedby the mi-
croprocessor. for each bitof ISTA0 register, except the ex-
tension bitsof ISTA1 and ISTA2 (EXI1, EXI2), the
wayto erase RPFisto writea ”0”atits location
andto writea ”1”at the locationof the others (for
example 7FH into ISTA0to erase RME). The
processing orderis: put Mask0on ISTA0(if Mask Off) (Read FIFOR)X32 Write ISTA0to erase RPF (BFH) Write RMCto ”1” for asking for another block the frame
(NB: RMC, RMD are automatically erased the controller) Remove Mask0
RMEbit (register ISTA0) set highto indicate the
HDLC controller has receiveda short frameor the
last blockofa large frame. The messageis now
complete, thebit remains high untilitis erasedby
the microprocessor. The processingorderis: put Mask0on ISTA0(if upper level Mask Off) Read RFBC witha maskon the3 most sig-
nificant bits,to know the number ”N”of
transferstodo (Read FIFOR)xNfor data Read FIFORfor statuson the frame Write ISTA0to erase RME (7FH) Write RMCor RMDto ”1” for asking for an-
other frame.
RF0 interruptsRF0isa bitof the interrupt register ISTA0 set
highto indicatean overflowof the receive FIFO
has been detected, either because more than8
frames cannot be storedor because more than bytes can’tbe stored. This informationis also
stored into the statusof the concerned frame
(RDO).
The processing orderof the microprocessoris: Lookingfor RPF and RME bits and pop-up
the frames. Then look for the status and
throw down the frame concerned.In general
case, only one frameis lost.-8-1-2- TRANSMIT DIRECTION
XPR InterruptXPRisabitof the interrupt register ISTA0 coming
highto indicate HDLC controller hasa free block 32 bytes. Thisbit remains high until the micro-
processor writea byte into the block and erase
thisbit into ISTA0;if another blockis free, XPR
get high again immediately.
The processing orderof the microprocessorisin
non DMA Mode: Put Mask0on ISTA0(if upper level Mask Off) Writeat leastone byte into FIFOX Write ISTA0to erase XPR Write XHFto ”1” for launching the transmit
operationof block(a blockis not necessarily bytes) write XMEto ”1” for launching the trans-
mitofa short frameorof the last partofa
frame Removemasks DMA Mode two general cases are possible:
The external DMA controller worksby ”pages”
lessor equalto 32 bytes. The ”process”of the
DMACisa short frame transmission and the
processor must give an XMEat the endof the
DMAC process (referto figure2).
The DMA controller worksby ”pages”of more
than 32 bytes. It’s processis the transferof the
whole frame.
The circuit doesn’t need an XHFat the endofan
intermediate 32 byte block; sinceit has reached bytes written into the current fifo,it begins the
transfer and toggleson the second fifoas soonas
the firstis full. (At this momentan XMEis possi-
bleif the 32nd byte was the endof the frame-
case1) and then,a 33rd write operation into the
fifo generatesan internal XHF and the frame fol-
lowing blocks are expected.In the two cases the flow controlis done be-
tween DMAC and ST5451 by the wayof
REQX and ACKX signals
The processing orderis: Put Mask0 Give orderto DMACto begin transfer Waitfor DMAC endof process Write ISTAto eraseon XPR Write XMEto signal the endof the frameto
the ST5451 (otherwise the ST5451 will put
”underrun” interrupt, as soon as its two
blocks are free).
XDU InterruptXDUisabitof the interrupt register ISTA0 com-
ing highto indicate HDLC controller has detected underrun(a frameis being transmitted and no
more bytes are availableinto the FIFO).
The HDLC controller finish the frameby transmit-
tingan ”Abort” andno more data canbe transmit-
ted evenin NHF mode. To be sure XDUis seen the MIcroprocessor, XDU interruptbit mustbe
erasedin ISTA0in additionof XRESsecurity pro-
cedure
The transmit controlis frozen and the only wayto
reinitializea transmit sessionisto writean XRES,
after erasing XDU.
ST545117/34
