ST5092TQFPTR ,2.7V SUPPLY 14-BIT LINEAR CODEC WITH HIGH-PERFORMANCE AUDIO FRONT-ENDBLOCK DIAGRAMMIC3-MIC PREAMP MIC AMP 20dB 0 -> 22.5 MIC2- EN+ MUTE 1.5dB STEPMIC1-PREFILTER & DETRA ..
ST50V-27F , Trankiller
ST5201 , TELECOMMUNICATIONS PRODUCTS
ST52E440G3D6 ,8-BIT INTELLIGENT CONTROLLER UNIT ICU Timer/PWM, Analog Comparator, Triac/PWM Timer, WDGfeaturesInterrupts■ 6 interrupt vectors■ Top Level External Interrupt (INT)I/O Ports■ 13 or 21 I/O ..
ST52F513F3M6 ,8-BIT INTELLIGENT CONTROLLER UNIT (ICU) Two Timer/PWMs, ADC, I2C, SPI, SCIFunctional Description 7211.2 Register Description . .7212 PWM/TIMERS . 7412.1 I ..
ST52F513G3M6 ,8-BIT INTELLIGENT CONTROLLER UNIT (ICU) Two Timer/PWMs, ADC, I2C, SPI, SCIST52F510/F513/F514®ST52F510/F513/F5148-BIT INTELLIGENT CONTROLLER UNIT (ICU)2Two Timer/PWMs, ADC, I ..
STN1NF10 ,N-CHANNEL 100V
STN1NK60Z ,N-CHANNEL 600Vapplications. Such seriescomplements ST full range of high voltage MOS-FETs including revolutionary ..
STN1NK80Z ,N-CHANNEL 800VAbsolute Maximum ratingsSymbol Parameter Value UnitTO-92 SOT-223 DPAK/IPAKV Drain-source Voltage (V ..
STN2222ASF , NPN Silicon Transistor
STN2222S , NPN Silicon Transistor
STN2222SF , NPN Silicon Transistor
ST5092TQFPTR
2.7V SUPPLY 14-BIT LINEAR CODEC WITH HIGH-PERFORMANCE AUDIO FRONT-END
ST50922.7V SUPPLY 14-BIT LINEAR CODEC
WITH HIGH-PERFORMANCE AUDIO FRONT-END
PRELIMINARY DATA
FEATURES:
Complete CODECand FILTER systemincluding: BIT LINEAR ANALOG TO DIGITAL AND
DIGITAL TO ANALOG CONVERTERS. BIT COMPANDED ANALOG TO DIGITAL
AND DIGITAL TO ANALOG CONVERTERS
A-LAW OR μ-LAW.
TRANSMITAND RECEIVE BAND-PASS FILTERS
ACTIVE ANTIALIAS NOISE FILTER.
Phone Features:THREE SWITCHABLE MICROPHONE AM-
PLIFIER INPUTS. GAIN PROGRAMMABLE: dB PREAMP. (+MUTE),0.. 22.5 dB AM-
PLIFIER, 1.5 dB STEPS.
EARPIECE AUDIO OUTPUT. ATTENUATION
PROGRAMMABLE:0..30 dB,2 dB STEPS.
EXTERNAL AUDIO OUTPUT. ATTENUATION
PROGRAMMABLE:0..30 dB,2 dB STEPS.
TRANSIENT SUPRESSION SIGNAL DURING
POWER ON AND DURING AMPLIFIER
SWITCHING.
INTERNAL PROGRAMMABLE SIDETONE
CIRCUIT. ATTENUATION PROGRAMMABLE: dB RANGE,1 dB STEP. ROUTING POSSI-
BLE TO BOTH OUTPUTS.
INTERNAL RING OR TONE GENERATOR IN-
CLUDING DTMF TONES, SINEWAVE OR
SQUAREWAVE WAVEFORMS. ATTENU-
ATION PROGRAMMABLE: 27dB RANGE,
3dB STEP. THREE FREQUENCY RANGES: 3.9Hz.... 996Hz, 3.9Hz STEP 7.8Hz.... 1992Hz, 7.8Hz STEP 15.6Hz.... 3984Hz,15.6Hz STEP
PROGRAMMABLE PULSE WIDTH MODU-
LATED BUZZER DRIVER OUTPUT.
General Features:SINGLE 2.7Vto 3.6V SUPPLY
EXTENDED TEMPERATURE RANGE OPERA-
TION(*) -40°Cto 85°C.
1.5 μW STANDBY POWER (TYP. AT 3.0V).
15mW OPERATING POWER (TYP. AT 3.0V).
13mW OPERATING POWER (TYP. AT 2.7V).
CMOS COMPATIBLE DIGITAL INTERFACES.
PROGRAMMABLE PCM AND CONTROL IN-
TERFACE MICROWIRE COMPATIBLE.
APPLICATIONS:GSM DIGITAL CELLULAR TELEPHONES.
CT2 DIGITAL CORDLESS TELEPHONES.
DECT DIGITAL CORDLESS TELEPHONES.
BATTERY OPERATED AUDIO FRONT-ENDS
FOR DSPs.
(*) Functionalityguaranteedin therange– 40°Cto +85°C;
Timingand ElectricalSpecificationsare guaranteedin therange
–30°Cto +85°C.
GENERAL DESCRIPTIONST5092isa high performancelow power combined
PCM CODEC/FILTER device tailoredto implement
the audio front-end functions requiredby the next
generation low voltage/low power consumption
digitalterminals.
ST5092 offersa numberof programmable func-
tions accessed througha serialcontrol channel that
easily interfacesto anyclassical microcontroller.
The PCM interface supportsbothnon-delayed(nor-
mal and reverse) and delayed frame synchroniza-
tion modes.
ST5092 canbe configurated eitherasa 14-bit lin-
earorasan 8-bit compandedPCM coder.
Additionally to the CODEC/FILTER function,
ST5092 includesa Tone/Ring/DTMF generator,a
sidetone generation,anda buzzer driver output.
ST5092 fulfills and exceeds D3/D4 and CCITT rec-
ommendations and ETSI requirements for digital
handsetterminals.
Main applications include digital mobile phones,as
cellular and cordless phones,or any battery pow-
ered equipment that requires audio codecs operat-
ingat low single supply voltages
June 1997
TQFP44(10x10x1.4) SO28
ORDERING NUMBERS:
Package Dim. Cond.
ST5092AD
ST5092ADTR
ST5092TQFP
ST5092TQFPTRSO28
SO28
TQFP44
TQFP44
10x10x1.4
10x10x1.4
Tube
Tape&Reel
Tray 8x20
Tape&Reel
1/29
&TEMICPREAMP
20dB MUTE
MICAMP ->22.5
1.5dBSTEP
(A)
(B)
PREFILTER&
BANDPASS
FILTER
PCMADC
BANDPASS
FILTER PCMDAC
TRANSMIT
REGISTER
RECEIVE
REGISTER
12dB
12dB
TONE, RING DTMF
GENER. FILTER
EARA OUTPUT 0 ->-30dB,
2dB STEP
EXTA OUTPUT
RTE
TONEAMP ->-27dB
3dBSTEP
SIDETONEAMP
-12.5-> -27.5dB
1dB STEP
CONTROL INTERFACE
μ-WIRE
CLOCK GENERATOR SYNCHRONIZER
INTERFACE LATCH
BUZZER
DRIVERBE
GNDP GNDA GND VCCA VCC VCCP
LEVEL ADJUST
(PWM)
MIC3-
MIC2-
MIC1-
MIC2+
MIC1+
MIC3+
VFr+
VFr-
VLr-
VLr+
CS-
CCLK
MCLK
D93TL074
BLOCK DIAGRAM
PIN CONNECTIONS (Topview)
N.C.
VCCA
VCCP
N.C.
VFr-
VLr-
VFr+
VLr+
GNDP MCLK
MIC2-
MIC1-
MIC2+
MIC1+
GNDA
MIC3-
MIC3+1 FS
D94TL094
CCLK
CS- CO
GND1114BZ VCC 19 20 21 22 43 42 41 3940 38 37 36 35 34
VLr+
VLr-
N.C.
VFr-
N.C.
VFr+
N.C.
N.C.
N.C.
GNDP
N.C. N.C.
CCLK
CS-
VCC DX
GND
N.C.
N.C. N.C. VCCP VCCA N.C.N.C. MIC3+ MIC3- GNDA N.C. MIC1+
N.C.
N.C.
N.C.
MCLK
MIC1-
N.C.
MIC2+
N.C.
MIC2-
D94TL095 13 14 15 16
TQFP44SO28
ST50922/29
PIN FUNCTIONS (SO28)
Pin Name Description N.C. Not Connected.
2VCCA Positive power supply inputforthe analog section.
VCC and VCCA mustbe directly connected together.
3VCCP Positive power supply inputforthe power section. VCCP and VCC mustbe connected together. N.C. Not Connected.
5,6 VFr+,VFr– Receive analog earpiece amplifier complementary outputs. Theseoutputs can drive directly earpiece
transductor. Thesignalat thisoutput canbe thesumof: Receive Speech signal from DR, Internal Tone Generator, Sidetone signal.
7,8 VLr+,VLr– Receive analog extra amplifier complementary outputs. The signalat these outputs canbethe
sumof: Receive Speech signal from DR, Internal Tone generator, Sidetone signal. GNDP Power ground.VFr andVLr driver are referencedto this pin. GNDP and GND mustbe connected
together closetothe device. DR Receive data input: Datais shiftedin duringthe assigned Received timeslotsIn delayed andnon-
delayed normal framesynchr. modes voice data byteis shiftedinatthe MCLK frequencyonthe
falling edges ofMCLK, whilein non-delayed reverse framesynchr. mode voice data byteis shiftedinthe MCLKfrequency onthe rising edgesof MCLK. CCLK Control Clock input: This clock shifts serial control information intoCI and out from CO whenthe
CS- inputis low, dependingonthe current instruction. CCLK maybe asynchronous withthe other
system clocks. CS- Chip Select input: When thispinis low, control informationis written into andout from the ST5092
viaCI and CO pins. CI Control data Input: SerialControl informationis shifted into the ST5092on thispin when CS-is lowthe rising edgesof CCLK. BZ Pulse width modulated buzzer driver output. VCC Positive power supply inputforthe digital section. CO Control data Output: Serial control/statusinformationis shifted out from the ST5092on thispin
when CS-is lowonthe falling edgesof CCLK. DX Transmit Data ouput: Datais shifted outon thispin duringthe assigned transmittime slots.
ElsewhereDX outputisinthe high impedance state.In delayed and non-delayed normal frame
synchr. modes, voice data byteis shiftedout from TRISTATE outputDXatthe MCLKon the rising
edgeof MCLK, whilein non-delayed reverse frame synchr mode voice data byteis shiftedouton
the falling edgeof MCLK. GND Ground:All digital signals are referencedto this pin. FS Frame Sync input: This signalisa 8kHz clock which definesthe startofthe transmit and receive
frames. Anyof three formats maybe usedfor this signal: non delayed normal mode, delayed
mode, and non delayed reverse mode. MCLK Master Clock Input: This signalis used bythe switched capacitor filters and theencoder/decoder
sequencing logic. Values mustbe 512 kHz, 1.536 MHz, 2.048 MHzor 2.56 MHz selected bymeansof
ControlRegister CRO. MCLKis used alsoto shift-inand outdata. LO A logic1 written into DO (CR1) appearsatLOpinasa logic0 logic0 written into DO (CR1) appearsatLOpinasa logic1. MIC2- Secondnegative high impedance inputto transmit pre-amplifierfor microphone connection. MIC2+ SecondPositivehighimpedance inputto transmitpre-amplifierfor microphone connection. MIC1- Negative high impedance inputto transmit pre-amplifier formicrophone connection. MIC1+ Positivehigh impedance inputto transmit pre-amplifier formicrophone connection. GNDA Analog Ground:All analogsignals arereferencedto this pin.GND and GNDA mustbe connected
together closetothe device. MIC3- Third negative high impedance outputto transmit preamplifier formicrophone connection. MIC3+ Third positive high impedance outputto transmit preamplifierfor microphone connection.
ST50923/29
PIN FUNCTIONS (TQFP44)
Pin Name Description N.C. Not Connected.
2,3 VFr+,VFr– Receive analog earpiece amplifier complementary outputs. Theseoutputs can drive directly earpiece
transductor. Thesignalat thisoutput canbe thesummof: Receive Speech signal from DR, Internal Tone Generator, Sidetone signal. N.C. Not Connected.
5,6 VLr+,VLr– Receive analog extra amplifier complementary outputs. The signalat these outputs canbethe sumof: Receive Speech signal from DR, Internal Tone generator, Sidetone signal. N.C. Not Connected. GNDP Power ground.VFr andVLr driver are referencedto this pin. GNDP and GND mustbe connected
together closetothe device. N.C. Not Connected. DR Receive datainput: Datais shiftedin duringthe assigned Received time slotsIn delayed and non-
delayed normal frame synchr. modes voice data byteis shiftedinat the MCLK frequencyonthe
falling edgesof MCLK, whilein non-delayed reverse frame sinchr. mode voice data byteis shifted atthe MCLK frequencyonthe risingedgesof MCLK.
11,12,13 N.C. Not Connected. CCLK Control Clock input: This clock shifts serial control information intoCI and out from CO when the
CS- inputis low, dependingonthe current instruction. CCLK maybe asynchronous withthe other
system clocks. CS- Chip Select input: Whenthispinis low, control informationis written into andout from the ST5092
viaCI and CO pins. CI Control data Input: SerialControl informationis shifted into the ST5092on thispin when CS-is lowthe rising edgesof CCLK. BZ Pulse width modulated buzzer driver output. VCC Positive power supply inputforthe digital section. CO Control data Output: Serial control/statusinformationis shifted out from the ST5092on thispin
when CS-is lowonthe falling edgesof CCLK. DX Transmit Dataouput: Data isshiftedouton thispin duringthe assigned transmit timeslots. Elsewhere outputisin thehigh impendance state.In delayed and non-delayed normal frame synchr. modes,
voice data byteis shiftedout from TRISTATEoutputDX attheMCLK onthe rising edgeof MCLK, while
innon-delayed reverse framesynchr mode voice data byteisshiftedouton thefalling edgeof MCLK. GND Ground:All digital signals are referencedto this pin.
22,23 N.C. Not Connected. FS Frame Sync input: This signalisa 8kHz clock which definesthe startofthe transmit and receive
frames. Eitherof three formats maybe usedfor this signal: non delayed normal mode, delayed
mode, and non delayed reverse mode. MCLK Master Clock Input: This signalis used bythe switched capacitor filters and theencoder/decoder
sequencing logic. Values mustbe 512 kHz, 1.536 MHz, 2.048 MHzor 2.56 MHz selected bymeansof
ControlRegister CRO. MCLKis used alsoto shift-inand outdata. LO A logic1 written into DO (CR1) appearsatLOpinasa logic0 logic0 written into DO (CR1) appearsatLOpinasa logic1.
27,28,29 N.C. Not Connected. MIC2- Secondnegative high impedance inputto transmit pre-amplifierfor microphone connection. MIC2+ SecondPositivehighimpedance inputto transmitpre-amplifierfor microphone connection. N.C. Not Connected. MIC1- Negative high impedance inputto transmit pre-amplifier formicrophone connection. MIC1+ Positivehigh impedance inputto transmit pre-amplifier formicrophone connection. N.C. Not Connected. GNDA Analog Ground:All analogsignals arereferencedto this pin.GND and GNDA mustbe connected
together closetothe device. MIC3- Third negative high impedance outputto transmit preamplifier formicrophone connection. MIC3+ Third positive high impedance outputto transmit preamplifierfor microphone connection.
39,40 N.C. Not Connected. VCCA Positive power supply inputforthe analog section.
VCC and VCCA mustbe directly connected together. VCCP Positive power supply inputforthe power section. VCCP and VCC mustbe connected together.
43,44 N.C. Not Connected.
ST50924/29
FUNCTIONAL DESCRIPTION DEVICE OPERATION
I.1
Power on initialization:When poweris first applied, power on reset cir-
cuitry initializes ST5092 and putsit into the power
down state. Gain Control Registersfor the various
programmable gain amplifiers and programmable
switches are initializedas indicatedin the Control
Register description section.All CODEC functions
are disabled.
The desired selection forall programmable func-
tions may be intialized priortoa power up com-
mand using the MICROWIRE control channel.
I.2
Power up/down control:Following power-on initialization, power up and
power down control maybe accomplishedby writ-
ing anyof the control instructions listedin Table1
into ST5092 with ”P”bit setto0 for powerupor1
for power down.
Normally,itis recommended thatall programma-
ble functions be initially programmed while the
deviceis powered down. Power state control can
then be included with the last programming in-
structionorina separate single byte instruction.
Anyof the programmable registers may also be
modified while ST5092is poweredupor downby
setting ”P” bit as indicated. When power up or
down controlis enteredasa single byte instruc-
tion,bit1 mustbe settoa0.
Whena power up commandis given,all de-acti-
vated circuits are activated, but output DX will re-
mainin the high impedance state until the second pulse after power up.
I.3
Power down state:Followinga periodof activity, power down state
may be reentered by writinga power down in-
struction.
Control Registers remainin their current state and
can be changed by MICROWIRE control inter-
face. additionto the power down instruction, detec-
tionof loss MCLK (no transition detected) auto-
matically enters the devicein ”reset” power down
state withDX outputin the high impedance state.
I.4
Transmit section:Transmit analog interfaceis designedin two
stagesto enable gains upto 42.5 dBto be real-
ized. Stage1isa low noise differential amplifier
providing 20 dB gain.A microphone maybe ca-
pacitevely connectedto MIC1+, MIC1- inputs,
while the MIC2+ MIC2– and MIC3+ MIC3- inputs
maybe usedto capacitivelyconnecta second mi-
crophoneora third microphone respectivelyor an
auxiliary audio circuit. MIC1or MIC2or MC3or
transmit muteis selected with bits6 and7of reg-
ister CR4. the mute case, the analog transmit signalis
grounded and the sidetone pathis also disabled.
Following the first stageisa programmable gain
amplifier which provides from0to 22.5 dBof ad-
ditional gainin 1.5dB step. The total transmit gain
shouldbe adjustedso that,at reference pointA,
see Block Diagram description, the internal0
dBm0 voltageis 0.49 Vrms (overload levelis 0.7
Vrms). Second stage amplifier gain can be pro-
grammedwith bits4to7of CR5. active RC prefilter then precedes the 8th order
band pass switched capacitor filter. A/D converter
canbe eithera 14-bit linear (bit CM=0in register
CR0)or can havea compressing characteristics
(bit CM=1in register CR0) accordingto CCITTA MU255 coding laws.A precision on chip volt-
age reference ensures accurate and highly stable
transmission levels.
Any offset voltage arisingin the gain-set amplifier,
the filtersor the comparatoris cancelledbyan in-
ternal autozero circuit.
Each encode cycle begins immediatlyat the be-
ginningof the selected Transmit time slot. The to-
tal signal delay referencedto the startof the time
slotis approximatively 195μs (dueto the transmit
filter) plus 125μs (dueto encoding delay), which
totals 320 μs. Voice datais shifted outon DX dur-
ing the selected time slot on the transmit rising
edgesof MCLKin delayedor non-delayed normal
modeoron the falling edgesof MCLKin non-de-
layed reverse mode.
I.5
Receive section:Voice Datais shifted into the decoder’s Receive
voice data Register via the DR pin during the se-
lected time slot on the falling edgesof MCLKin
delayedor non-delayed normal modeor on the
rising edges of MCLKin non-delayed reverse
mode.
The decoder consistsof eithera 14-bit linearor expanding DAC withAor MU255 law decod-
ing characteristic. Following the Decoderisa
3400 Hz 8th order band-pass switched capacitor
filter with integral Sin X/X correctionfor the8 kHz
sample and hold. dBmO voltageat this (B) reference point (see
Block Diagram description)is 0.49 Vrms.A tran-
scient suppressing circuitry ensure interference
noise suppressionat power up.
The analog speech signal output can be routed
eitherto earpiece (VFR+,VFR- outputs)ortoan ex-
tra analog output (VLr+,VLr- outputs)by setting
bits OE and SE(1 and0of CR4).
Total signal delayis approximatively 190μs (filter
plus decoding delay) plus 62.5 μs (1/2 frame)
which gives approximatively252 μs.
Differential outputs VFR+,VFR- are intendedto di-
rectly drive an earpiece. Preceding the outputsis programmable attenuation amplifier, which must
ST50925/29
setby writingto bits4to7in register CR6. At-tenuationsin the range0to -30 dB relativeto the
maximum levelin2 dB step canbe programmed.
The inputof this programmable amplifieris the
sumof several signals which can be selectedby
writingto registerCR4.: Receive speech signal which has been de-
coded and filtered, Internally generated tone signal, (Tone ampli-
tudeis programmed with bits4to7of register
CR7), Sidetone signal, the amplitudeof whichis pro-
grammed with bits0to3of register CR5
VFR+ andVFR- outputsare capableof driving output
power level upto 66mW into differentially con-
nected load impedanceof30Ω. Piezoceramic re-
ceiversupto 50nF can alsobe driven.
Differential outputs VLr+,VLr- are intendedto di-
rectly drivean extra output. Preceding the outputsa programmable attenuation amplifier, which
must be set by writingto bits0to3in register
CR6. Attenuationsin the range0to -30 dB rela-
tiveto the maximum levelin 2.0 dB step can be
programmed. The inputof this programmable am-
plifier canbe the sumof signals which canbe se-
lectedby writingto register CR4: Receive speech signal which has been de-
coded and filtered, Internally generated tone signal, (Tone ampli-
tudeis programmed with bits4to7of register
CR7), Sidetone signal, the amplitudeof whichis pro-
grammed with bits0to3of register CR5.
VLr+ and VLr- outputsare capableof driving output
power level upto 66mW into differentially con-
nected load impedanceof30Ω. Piezoceramicre-
ceiversupto 50nF can alsobe driven.
BUZZER OUTPUT:
Single ended output BZis intendedto drivea
buzzer, via an external BJT, witha squarewave
pulse width modulated (PWM) signal the fre-
quencyof whichis stored into register CR8.
For some applicationsitis also possibleto ampli-
tude modulate this PWM signal witha square-
wave signal havinga frequencystoredin register
CR9.
Maximum loadfor BZis 5kΩ and 50pF.
I.6
Digital Interface (Fig.1) Frame Sync input determines the beginningof
frame.It may have any duration froma single cy-
cleof MCLKtoa squarewave. Three different re-
lationships may be established between the
Frame Sync input and the first time slotof frame setting bits DM1 and DM0in register CR1.
Non delayed data modeis similarto long frame
timing on ST5080A: first time slot begins nomi-
nally coincident with the rising edgeof FS. Alter-
nativeisto use delayed data mode, whichis simi-
larto short frame sync timing on ST5080A,in
whichFS input mustbe highat leasta half cycle MCLK earlier the frame beginning.In the case companded code only (bit CM=1in register
CRO)a time slot assignment circuit on chip may used withall timing modes, allowing connec-
tionto oneof the twoB1 and B2 voice data chan-
nels.
Two data formats are available:in Format1, time
slot B1 correspondsto the8 MCLK cycles follow-
ing immediately the rising edgeof FS, while time
slot B2 correspondsto the8 MCLK cycles follow-
ing immediately time slot B1. Format2, time slot B1is identicalto Format1.
Time slot B2 appears twobit slots after time slot
B1. This two bits spaceis left availablefor inser-
tionof theD channel data.
Data formatis selected by bit FF (2)in register
CR0. Time slot B1or B2is selectedbybit TS (1) Control Register CR1.
Bit EN (2)in control register CR1 enablesor dis-
ables the voice data transfer on DX and DR as
appropriate. During the assigned time slot, DX
output shifts data out from the voice data register the rising edgesof MCLKin the caseof de-
layed and non-delayed normal modesor on the
falling edgesof MCLKin the caseof non-delayed
reverse mode. Serial voice datais shifted into DR
input during the same time slot on the falling
edgesof MCLKin the caseof delayed and non-
delayed normal modesor on the rising edgesof
MCLKin the caseof non-delayedreverse mode.isin the high impedance Tristate condition
whenin the non selected time slots.
I.7
Control Interface:Control informationor datais written intoor read-
back from ST5092 via the serial control port con-
sistingof control clock CCLK, serial data inputCI
and output CO, and Chip Select input, CS-. All
control instructions require2 bytesas listedin Ta-
ble1, with the exceptionofa single byte power-
up/down command. shift control data into ST5092, CCLK must be
pulsed high8 times while CS-is low. DataonCI
inputis shifted into the serial input registeron the
rising edgeof each CCLK pulse. Afterall datais
shiftedin, the contentof the input shift registeris
decoded, and may indicate thata 2nd byteof
control data will follow. This second byte may
either be defined bya second byte-wide CS-
pulseor may follow the first contiguously, i.e.itis
not mandatory for CS-to return highin between
the first and second control bytes.At the endof
the 2nd control byte, datais loaded into the ap-
ST50926/29
propriate programmable register. CS- must return
highat the endof the 2nd byte. read-backstatus information from ST5092, the
first byteof the appropriate instructionis strobed during the first CS- pulse,as definedin Table CS- must be set low fora further8 CCLK cy-
cles, during which datais shifted outof the CO
pinon the falling edgesof CCLK.
When CS-is high, CO pinisin the high imped-
ance Tri-state, enabling CO pinsof several de-
vicestobe multiplexed together.
Thus,to summarise,2 byte READ and WRITEin-
structions may use either two 8-bit wide CS-
pulsesora single16bit wide CS- pulse.
I.8
Control channel accessto PCM interface:is possibleto access theB channel previously
selectedin Register CR1in the caseof com-
panded code only. byte written into Control Register CR3 will be
automatically transmitted from DX outputin the
following framein placeof the transmit PCM data. byte written into Control Register CR2 will be
automatically sent through the receive pathto the
Receive amplifiers. orderto implementa continuous data flow from
the Control MICROWIRE interfacetoaB chan-
nel,itis necessaryto send the control byte on
each PCM frame. current byte received on DR input can be read the register CR2.In orderto implementa con-
tinuous data flow froma B channel to MI-
CROWIRE interface,itis necessaryto read regis-
ter CR2at each PCM frame.
(nondelayedtiming)
(delayedtiming)F5B2B1 XXB1
MCLK
FORMAT1(nondelayedtiming)
(delayedtiming)F8
XB2B1 XXB1
MCLK
FORMAT2D93TL075
Figure1: Digital Interface Format(*)
(*) Significant OnlyFor Companded Code.
ST50927/29
PROGRAMMABLE FUNCTIONSFor both formatsof Digital Interface, programma-
ble functions are configuredby writingtoa num-
berof registers usinga 2-byte write cycle.
Mostof these registers can also be read-backfor
verification. Byte oneis always register address,
while byte twois Data.
Table1 lists the register set and their respective
adresses.
Table1: Programmable Register Intructions
Function Address byte Data byte 54321 0
Single byte Power up/down P X X X X X 0 X none
Write CR0 P 0 00001 X see CR0 TABLE2
Read-back CR0 P 0 00011 X see CR0
Write CR1 P 0 00101 X see CR1 TABLE3
Read-back CR1 P 0 00111 X see CR1
Write Datato receive path P 0 01001 X see CR2 TABLE4
Read data fromDR P 0 01011 X see CR2
Write DatatoDX P 0 01101 X see CR3 TABLE5
Write CR4 P 0 10001 X see CR4 TABLE6
Read-back CR4 P 0 10011 X see CR4
Write CR5 P 0 10101 X see CR5 TABLE7
Read-back CR5 P 0 10111 X see CR5
Write CR6 P 0 11001 X see CR6 TABLE8
Read-back CR6 P 0 11011 X see CR6
Write CR7 P 0 11101 X see CR7 TABLE9
Read-back CR7 P 0 11111 X see CR7
Write CR8 P 1 00001 X see CR8 TABLE10
Read-back CR8 P 1 00011 X see CR8
Write CR9 P 1 00101 X see CR9 TABLE11
Read-back CR9 P 1 00111 X see CR9
Write CR10 P 1 01001 X see CR10 TABLE12
Read-back CR10 P 1 01011 X see CR10
Write CR11 P 1 01101 X see CR11 TABLE13
Read-back CR11 P 1 01111 X see CR11
Write Test Register CR14 P 1 11001 X reserved
NOTE1: bit7ofthe address byteand data byteis alwaysthefirstbit clocked intoorout from:CIandCO pins when MICROWIRE serial
port isenabled.= reserved:write0
NOTE2: ”P”bitis Power up/downControlbit.P=1 Means PowerDown.
Bit1 indicates,ifset,the presenceofa secondbyte.
NOTE3: Bit2 iswrite/read selectbit.
NOTE4: RegistersCR12, CR13,and CR15 arenot accessible.
ST50928/29
Table2: Control Register CR0 Functions
6 54 32 10 FunctionF1 F0 CM MA IA FF B7 DLMCLK= 512 kHz
MCLK= 1.536 MHz
MCLK= 2.048 MHz
MCLK= 2.560 MHz
Linear code
Companded code
Linear Code Companded Code
2-complement *
sign and magnitude
2-complement
1-complement
MU-law: CCITT D3-D4 *
MU-law: Bare Coding
A-lawincluding evenbit inversion
A-law: Bare Coding andB2 consecutive andB2 separated (1)
(1) bits time-slot bits time-slot (1)
(1)
Normal operation
Digital Loop-back state atpoweron initialization
(1): significantin companded mode only
Table3: Control Register CR1 Functions
543 21 0 Function
DM1 DM0 DO MR MX EN TSdelayed data timing
non-delayed normal datatiming
non-delayed reverse data timing latchsetto1 latchsetto0 connectedto rec. path
CR2 connectedto rec. path
(1)
Trans path connectedtoDX
CR3 connectedtoDX
(1)
voice data transfer disable
voice data transfer enable channel selected channel selected (1)
(1) stateat poweron initialization
(1):
significantin companded mode only
reserved: write0
ST50929/29
Table4: Control Register CR2 Functions
6 54 32 10 Functiond7 d6 d5 d4 d3 d2 d1 d0msb lsb Data sentto Receive pathor Data received fromDR input (1)
(1)Significantin companded mode only.
Table5: Control Registers CR3 Functions
6 54 32 10 Function d6 d5 d4 d3 d2 d1 d0msb lsb DX data transmitted (1)
(1)Significantin companded mode only
Table6: Control Register CR4 Functions
6 54 32 10 Function TE SI OE1 OE2 RTE HPB SETransmit input muted
MIC1 Selected
MIC2 Selected
MIC3 Selected
Internal sidetone disabled
Internal sidetone enabled
Receive output muted
VFr output selected
VLr output selected
NOT ALLOWED
Ring/ TonetoVFrorVLr disabled
Ring/ TonetoVFrorVLr enabled
Receive HP filter enabled
Receive HP filter disabled
Receive SignaltoVFrorVLr disabled
Receive SignaltoVFrorVLr enabled state atpoweron initialization reserved: write0
ST509210/29
Table8: Control Register CR6 Functions
6 54 32 10
FunctionEarpiece ampifier
[EARA] Extra amplifier [EXTA]dB gaindB gain2dB step
-30dB gaindB gaindB gain2dB step
-30dB gain stateat poweron initialization
Table9: Control Register CR7 Functions
6 5 4 3 2 1 0 Function
Tone gain F1 F2 SN DE Attenuation f1 Vpp f2 Vpp....0dB*dBdBdB
-12dB
-15dB
-18dB
-21dB
-24dB
-27dB
...1.6(2)
1.26(2)
0.053 andf2 muted selected selected andf2in summed mode
Squarewave signal selected
Sinewave signal selected
Normal operation
Tone/ Ring Generator connectedto
Transmit path state atpoweron initialization
(2): value providediff1orf2is selectedalone.f1and f2are selectedinthe summed mode, f1=0.89Vpp while f2=0.7Vpp. reserved: write0
Table7: Control Register CR5 Functions
6 54 32 10 Function
Transmit amplifier Sidetone amplifierdB gain
1.5dB gain1.5dB step
22.5dB gain
-12.5dB gain
-13.5dB gain1dB step
-27.5dB gain stateat poweron initialization
ST509211/29
Table 10: Control Register CR8 Functions
6 54 32 10 Function
f17 f16 f15 f14 f13 f12 f11 f10msb lsb Binary equivalentof the decimal number usedto calculatef1
Table 11: Control Register CR9 Functions
6 54 32 10 Function
f27 f26 f25 f24 f23 f22 f21 f20msb lsb Binary equivalentof the decimal number usedto calculatef2
Table 13: Control Register CR11Functions
6 54 32 10 Function BI BZ5 BZ4 BZ3 BZ2 BZ1 BZ0Buzzer outputdisabled (setto0) *
Buzzer outputenabled
Duty Cycleis intendedas the relative widthof logic1*
Duty cycleis intendedas the relative widthof logic0
msb lsb Binary equivalentof the decimal number usedto calculatethe
duty cycle. stateat poweroninitialization
Table 12: Control Register CR10 Functions
6 54 32 10 Function
DFT HFT XXXX
(*) Standard Frequency Tone Range
Halved Frequency Tone Range
Doubled Frequency Tone Range
Forbidden
(*) Default values insertedinto theRegisterat PowerOn. reserved, write0.
ST509212/29
CONTROL REGISTER CR0First byteofa READora WRITE instructionto
Control Register CR0is as shownin TABLE1.
Second byteisas shownin TABLE2.
Master Clock Frequency Selection master clock must be providedto ST5092 for
operationof filter and coding/decodingfunctions.
MCLK frequency can be either 512 kHz, 1.536
MHz, 2.048 MHzor 2.56 MHz.
Bit F1 (7) and F0 (6) mustbe set during initializa-
tionto select the correct internal divider.
Default valueis 512 kHz.
Any clock different from the default one must be
selected priora Power-Upinstruction.
Coding Law SelectionBits MA (4) andIA (3) permit selectionof Mu-255
laworA law coding withor without evenbit inver-
sionif companded code (bit CM=1)is selected.
Bits MA(4) and IA(3) permit selectionof 2-com-
plement, 1-complementor sign and magnitudeif
linear code (bit CM=0)is selected.
Coding SelectionBit CM(5) permits selection eitherof linear coding
(14-bit) or companded coding (8-bit). Default
valueis linear coding.
Digital Interface format (1)Bit FF(2)=0 selects digital interfacein Format1
where B1 and B2 channel are consecutive. FF=1
selects Format2 where B1 and B2 channel are
separatedby two bits. (See digital interface for-
mat section.)
56+8 selection (1)Bit ’B7’ (1) selects capabilityfor ST5092to take
into account only the seven most significant bits the PCM data byte selected.
When ’B7’is set, the LSBbitonDRis ignored and
LSBbitonDXis high impedance. This functional-
lows connectionof an external ”in band” data
generator directly connectedon the Digital Inter-
face.
Digital loopbackDigital loopback modeis entered by setting DL
bit(0) equal1. Digital Loopback mode, data written into Re-
ceive PCM Data Register from the selected re-
ceived time-slotis read-back from that Registerin
the selected transmit time-sloton DX. PCM decodingor encoding takes placein this
mode. Transmit and Receive amplifier stages are
muted.
CONTROL REGISTER CR1First byteofa READora WRITE instructionto
Control Register CR1is as shownin TABLE1.
Second byteisas shownin TABLE3.
Digital Interface TimingBit DM1(7)=0 selects digital interfacein delayed
timing mode, while DM1=1 and DM0=0 selects
non-delayed normal data timing mode, and DM11 and DM0=1 selects non-delayed reverse
data timing mode.
Defaultis delayeddata timing.
Latch output controlBit DO controls directly logical statusof latch out-
put LO: ie,a ”ZERO” writtenin bit DO puts the
output LOat logical1, whilea ”ONE” writteninbit sets the output LOto zero.
Microwire access toB channel on receive
path (1)Bit MR (4) selects access from MICROWIRE
Register CR2to Receive path. When bit MRis
set high, data writtento register CR2is decoded
each frame, sentto the receive path and datain-
putat DRis ignored. the other direction, current PCM data input re-
ceivedat DR canbe read from register CR2 each
frame.
Microwire access toB channel on transmit
path (1)Bit MX (3) selects access from MICROWIRE write
only Register CR3to DX output. Whenbit MXis
set high, data writtento CR3is outputat DX every
frame and the outputof PCM encoderis ignored.
255 law TrueA law evenbit
inversion law without evenbit
inversion
msb lsb msb lsb msb lsbVin=+full scale 1 0 000000 101 01 0 1011 1111 11
Vin=0V 1
Vin=-full scale 0 0 000000 001 01 0 1001 1111 11
MSBis alwaysthe firstPCMbit shiftedin oroutof: ST5092.
(1)Significantin companded mode only
ST509213/29
Transmit/Receiveenabling/disablingBit ’EN’ (2) enablesor disables voice data trans-
feron DX and DR pins. When disabled, PCM data
from DRis not decoded and PCM time-slots are
high impedanceon DX. Default valueis disabled.
B-channel selection(1)Bit TS(1) permits selection between B1 or B2
channels. Default valueisB1 channel.
CONTROL REGISTER CR2 (1)Data sentto receive pathor data received from input. Referto bit MR(4)in ”Control Register
CR1” paragraph.
CONTROL REGISTER CR3 (1) data transmitted. Refertobit MX(3)in ”Control
Register CR1” paragraph.
CONTROL REGISTER CR4First byteofa READora WRITE instructionto
Control Register CR4is as shownin TABLE1.
Second byteisas shownin TABLE6.
Transmit Input SelectionMIC1or MIC2or MIC3or transmit mute canbe
selected with bits6 and7 (VS and TE).
Transmit gain can be adjusted withina 22.5 dB
rangein 1.5 dB step with Register CR5.
Sidetone SelectionBit ”SI” (5) enablesor disables Sidetone circuitry.
When enabled, sidetone gain can be adjusted
with Register (CR5). When Transmit pathis dis-
abled, sidetonecircuitis also disabled.
Output Driver SelectionBits OE1(4) and OE2(3) provide the selection
among the earpiece outputor the extra amplifier
outputor both outputs muted.
OE1=1 and OE2=1is not allowed.
Ring/Tone signal selectionBit RTE (2) provide select capabilityto connect
on-chip Ring/Tone generator eitherto an extra
amplifier inputorto earpiece amplifier input.
Receive High Pass Filter SelectionBit HPB (1) provide the selectionof the receive
high pass filter cutoff frequency.
PCM receive data selectionBits ”SE” (0) provide select capabilityto connect
received speech signal eithertoan extra amplifier
inputorto earpiece amplifier input.
CONTROL REGISTER CR5First byteofa READora WRITE instuctionto
Control Register CR5is as shownin TABLE1.
Second byteisas shownin TABLE7.
Transmit gain selectionTransmit amplifier can be programmedfora gain
from 0dBto 22.5dBin 1.5dB step with bits4to7. dBmO levelat the outputof the transmit ampli-
fier(A reference point)is 0.492 Vrms (overload
voltageis 0.707 Vrms).
Sidetone attenuation selectionTransmit signal picked up after the switched ca-
pacitor low pass filter may be fed back into both
Receive amplifiers.
Attenuationof the signalat the outputof the
sidetone attenuator can be programmed from
–12.5dBto -27.5dB relativeto reference pointin1 dB step with bits0to3.
CONTROL REGISTER CR6First byteofa READora WRITE instructionto
Control Register CR6is as shownin TABLE1.
Second byteisas shownin TABLE8.
Earpiece amplifier gain selection:Earpiece Receive gain can be programmedin2 step from0 dBto -30 dB relativeto the maxi-
mum with bits4to7. dBmO voltageat the outputof the amplifieron
pins VFr+ and VFr-is then 1.965 Vrms when 0dB
gainis selected downto 61.85 Vrms when -30dB
gainis selected.
Extra amplifier gain selection:Extra Receive amplifier gain can be programmed2 dB step from0 dBto -30 dB relativeto the
maximum with bits0to3. dBmO voltage on the outputof the amplifieron
pins VLr+ and VLr- 1.965 Vrms when0 dB gainis
selected downto 61.85 mVrms when -30 dB gain selected.
CONTROL REGISTER CR7:First byteofa READora WRITE instructionto
Control Register CR7is as shownin TABLE1.
Second byteisas shownin TABLE9.
(1)Significantin companded mode only
ST509214/29
Tone/Ring amplifier gain selectionOutput levelof Ring/Tone generator, before at-
tenuationby programmable attenuatoris 1.6 Vpk- when f1 generatoris selected alone or
summed with thef2 generator and 1.26 Vpk-pk
whenf2 generatoris selected alone.
Selected output level can be attenuated downto
-27 dB by programmable attenutatorby setting
bits4to7.
Frequency mode selectionBits ’F1’ (3) and ’F2’ (2) permit selectionoff1
and/orf2 frequency generator accordingto TA-
BLE9.
When f1 (or f2) is selected, output of the
Ring/Toneisa squarewave(ora sinewave) signal the frequency selectedin the CR8 (or CR9)
Register.
Whenf1 andf2 are selectedin summed mode,
output of the Ring/Tone generatorisa signal
wheref1 andf2 frequency are summed. orderto meet DTMF specifications,f2 output
levelis attenuatedby 2dB relativeto thef1 output
level.
Frequency temporization mustbe controlledby the
microcontroller.
Waveform selectionBit ’SN’ (1) selects waveformof the outputof the
Ring/Tone generator. Sinewaveor squarewave
signal canbe selected.
DTMF selectionBit DE (0) permits connectionof Ring/Tone/DTMF
generator on the Transmit Data path insteadof
the Transmit Amplifier output. Earpieceor extra
receive output feed-back may be provided by
sidetone circuitry by setting bitSIor directly by
setting bit RTEin Register CR4. Loudspeaker
feed-back may be provided directlyby settingbit
RTLin Register CR4.
CONTROL REGISTERS CR8 AND CR9First byteofa READora WRITE instructionto
Control Register CR8or CR9isas shownin TA-
BLE1. Second byteis respectivelyas shownin
TABLE10 and 11. ”standard frequency tone range”is selected,
Toneor Ring signal frequency valueis definedby
the formula:= CR8/ 0.128 Hz
and= CR9/ 0.128 Hz
where CR8 and CR9 are decimal equivalentsof
the binary valuesof the CR8 and CR9 registers
respectively.Thus, any frequencybetween 7.8 Hz
and 1992 Hz maybe selectedin 7.8 Hz step. ”halved frequency tone range”is selected, Tone Ring signal frequency valueis definedby the
formula:= CR8/ 0.256 Hz
and= CR9/ 0.256 Hz
This any frequency between 3.9Hz and 996Hz
maybe selectedin 3.9Hz step. ”doubled frequency tone range”is selected,
Toneor Ring signal frequency valueis definedby
the formula:= CR8/ 0.064 Hz
and= CR9/ 0.064 Hz
Thus any frequencybetween 15.6Hz and 3984Hz
maybe selectedin 15.6Hz step.
TABLE12 gives examples for the main frequen-
cies usualfor Toneor Ring generation.
CONTROL REGISTER CR10Bit DFT(1) and HFT(0) permits the selection
among ”standard frequency tone range” (i.e. from
7.8Hz to 1992Hzin 7.8Hz step), ”halved fre-
quency tone range” (i.e. from 3.9Hzto 996Hzin
3.9Hz step), and ”doubled frequency tone range”
(i.e. from 15.6Hzto 3984Hzin 15.6Hz step) ac-
cordingto the values describedin CONTROL
REGISTER CR8 and CR9.
CONTROL REGISTERCR11
Bit BE(7) permits connectionofaf1 squarewave
PWM Ring signal, amplitude modulatedor notbyf2 squarewave signal,to buzzer driver output
BZ. Bits BZ5to BZ0 define the duty cycleof the
PWM squarewave, accordingto the following for-
mula:
Duty Cycle= CR11(5÷0)x 0.78125%
where CR11(5÷0)is the decimal equivalentof
the binary value BZ5÷ BZ0.
When BE=1,if bits F1=1 and F2=0in regis-
ter CR7,af1 PWM ring signalis presentat the
buzzer output, whileif bits F1=1 and F2=1in
register CR7 thef1 PWM ring signalis also am-
plitude modulated bya f2 squarewave fre-
quency. BitBI (6) allowsto chose the logic level which the duty cycleis referred:BI=0 means
that duty cycleis intendedas the relative width the logic1, whileBI=1 means that duty cycle intended as the relative widthof the logic0.
When BE=0 (or during power down) BZ=0if=0or BZ=1ifBI=1.
ST509215/29
