ST5088D ,PROGRAMMABLE AUDIO FRONT END FOR DIGITAL PHONES AND ISDN TERMINALSFeatures:WITH AUTOMATIC DIGITAL ANTICLIPPINGEXTENDED TEMPERATURE RANGE OP-SYSTEM. aTTENUATION PROGR ..
ST5090TQFP ,LOW VOLTAGE 14-BIT LINEAR CODEC WITH HIGH-PERFORMANCE AUDIO FRONT-ENDBLOCK DIAGRAMMIC3-MIC PREAMP MIC AMP 20dB 0 -> 22.5 MIC2-EN+ MUTE 1.5dB STEPMIC1-PREFILTER & DETRAN ..
ST5092TQFP ,2.7V SUPPLY 14-BIT LINEAR CODEC WITH HIGH-PERFORMANCE AUDIO FRONT-ENDBLOCK DIAGRAMMIC3-MIC PREAMP MIC AMP20dB 0 -> 22.5MIC2- EN+ MUTE 1.5dB STEPMIC1-PREFILTER &DETRANSM ..
ST5092TQFPTR ,2.7V SUPPLY 14-BIT LINEAR CODEC WITH HIGH-PERFORMANCE AUDIO FRONT-ENDBLOCK DIAGRAMMIC3-MIC PREAMP MIC AMP 20dB 0 -> 22.5 MIC2- EN+ MUTE 1.5dB STEPMIC1-PREFILTER & DETRA ..
ST50V-27F , Trankiller
ST5201 , TELECOMMUNICATIONS PRODUCTS
STMUX7000QTR ,7-channel MUX/DEMUX for analog video signal
STN1HNC60 ,N-CHANNEL 600V 7 OHM 0.4A SOT-223 POWERMESH II MOSFET
STN1HNK60 ,N-CHANNEL 600Vapplications. Such seriescomplements ST full range of high voltage MOS-FETs including revolutionary ..
STN1N20 ,N-CHANNEL 200V
STN1NF10 ,N-CHANNEL 100V
STN1NK60Z ,N-CHANNEL 600Vapplications. Such seriescomplements ST full range of high voltage MOS-FETs including revolutionary ..
ST5088D
PROGRAMMABLE AUDIO FRONT END FOR DIGITAL PHONES AND ISDN TERMINALS
ST5088PROGRAMMABLE AUDIO FRONT END
FOR DIGITAL PHONES AND ISDN TERMINALS
FEATURES:
CompleteCODEC and FILTER systemincluding:PCM ANALOG TO DIGITAL AND DIGITAL TO
ANALOG CONVERTERS
POWERFUL ANALOG FRONT END CAPA-
BLE TO INTERFACE DIRECTLY: Microphone Dynamicor Electrete Earpiece downto 100Ωorupto 150nF Loudspeaker downto 50Ωor Buzzerupto
600nF.
TRANSMIT BAND-PASS FILTER
ACTIVE RC NOISE FILTER
RECEIVE LOW-PASS FILTER WITH SIN X/X
CORRECTION
MU-LAW OR A-LAW SELECTABLE COM-
PANDING CODER AND DECODER
PRECISION VOLTAGE REFERENCE
Phones Features:DUAL SWITCHABLE MICROPHONE AMPLI-
FIER INPUTS. GAIN PROGRAMMABLE: 15 RANGE,1 dB STEP.
LOUDSPEAKER AMPLIFIER OUTPUT.
SWITCHABLE MAXIMUM GAIN: +9dB/+27dB
WITH AUTOMATIC DIGITAL ANTICLIPPING
SYSTEM. aTTENUATION PROGRAMMABLE:
30dB RANGE, 2dB STEP.
SEPARATE EARPIECE AMPLIFIER OUTPUT.
ATTENUATION PROGRAMMABLE: 15 dB
RANGE,1 dB STEP.
AUXILIARY TAPE RECORDER ANALOG IN-
TERFACE:Tx+ Rx COMBINEDOUTPUT.
AUXILIARY SWITCHABLE EXTERNAL RING
INPUT (EAIN).
TRANSIENT SUPRESSION SIGNAL DURING
POWER ON.
INTERNAL PROGRAMMABLE SIDETONE
CIRCUIT. ATTENUATION PROGRAMMABLE: dB RANGE,1 dB STEP, INDEPENDENT
FROM Rx CONTROL.
INTERNAL RING OR TONE GENERATOR IN-
CLUDING DTMF TONES, SINEWAVE OR
SQUAREWAVE WAVEFORMS. ATTENU-
ATION PROGRAMMABLE: 27 dB RANGE,3 STEP.
RINGER CONTROL PROGRAMMABLE IN-
TERNALLY (μP) OR EXTERNALLY (pin AT)
COMPATIBLE WITH HANDS-FREE CIRCUIT
TEA7540. CHIP SWITCHABLE ANTI-ACOUSTIC
FEED-BACK CIRCUIT (ANTI-LARSEN).
General Features:EXTENDED TEMPERATURE RANGE OP-
ERATION
(*) –25°C TO +85°C.
EXTENDED POWERSUPPLYRANGE 5V±10%. mW OPERATING POWER (TYPICAL).
1.0 mW STANDBY POWER (TYPICAL).
CMOS DIGITAL INTERFACES.
SINGLE+ 5V SUPPLY.
DIGITAL LOOPBACKTEST MODE.
PROGRAMMABLE DIGITAL AND CONTROL
INTERFACES:
–Digital PCM Interface associated with
separate serial Control Interface MI-
CROWIRE compatible.
–GCI interface compatible.
(*) Functionalityguaranteedin therange– 25°Cto +85°C;
Timingand ElectricalSpecificationsare guaranteedinthe range
–5°Cto +70°C.
APPLICATIONS:ISDN TERMINALS.
DIGITAL TELEPHONES
CT2 AND GSM APPLICATIONS
December 1999
ORDERING NUMBERS:ST5088D ST5088FN
PLCC28SO281/33
BLOCK DIAGRAM
PIN CONNECTION (Top view)
HFI
HFO
VFR+
VFR-
VCC
LS+
LS-
GND CS-/A3
MIC2+
MIC1+
TRO
MIC1-
VCCA
MIC2-
GNDA
EAIN1 CCLK/A0
D93TL047
CO/A2
CI/A1 MCLK
N.C.1114DR FS
PLCC28SO28
ST50882/33
TYPICAL ISDN TELEPHONE SET APPLICATION
ST50883/33
GENERAL DESCRIPTIONST5088 PIAFEisa combined PCM CODEC/FIL-
TER device optimizedfor ISDN Terminals and Digi-
tal Telephone applications. This deviceis A-law
and Mu-law selectable and offersa numberof pro-
grammable functions accessed througha serial
control channel.
Depending on mode selected, channel controlis
providedby meansofa separate serial channel
control MICROWIRE compatibleor multiplexed
with the PCM voice data channelina GCI com-
patible format requiring only4 digital interface
pins. When separate serial control interfaceis se-
lected, PCM interfaceis compatible with ComboI
and ComboII families of devices such as
ETC5057/54,TS5070/71.
PIAFEis built using SGS-THOMSON’s advanced
HCMOS process.
Transmit sectionof PIAFE consistsof an amplifier
with switchable high impedance inputs followeda programmable gain amplifier, an active RC
antialiasing pre-filterto provide attenuationof high
frequency noise,an 8th order switched capacitor
band pass transmit filter and an A-law/Mu-law se-
lectable compandigencoder.
Receive section consistof an A-law/Mu-law se-
lectable expanding decoder which reconstructs
the analog sampled data signal,a 3400 Hz low
pass filter with sin X/X correction followedby two
separate programmable attenuation blocks and
two power amplifiers: one canbe usedto drivean
earpiece, and the otherto drivea 50Ω loud-
speakerora piezo transducerupto 600nF.
When the loudspeaker sectionis set up with
maximum gain (+27dB) the device provide inter-
nallya programmable digital anticlipping system avoid output distortion.
Programmable functions on PIAFE includea
Ring/Tone generator which provides oneor two
tones and can be directedto earpieceorto loud-
speaker(or buzzer). simple ringer control interface can bypass μP
controlof sweep frequency and ring ON/OFF
phases. separate programmable gain amplifier allows
gain controlof the signal injected. Ring/Tone gen-
erator provides sinewaveor squarewave signal
with precise frequencies which may be also di-
rectedto the inputof the Transmit amplifier for
DTMF tone generation. auxiliary analog input (EAIN)is also provided enable for example the outputof an external
band limited Ring signal to the Loudspeaker.
Transmit signal may be fed back into the receive
ampifier witha programmable attenuationto pro-
videa sidetone circuitry. switchable anti-accoustic feed-back system
cancels the larsen effectin speech monitoring ap-
plication.
Two additional pins are provided for insertionof external Handfree functionin the Loudspeaker
receive path. output latch controlled by register program-
ming permits external device control.
PIN FUNCTIONS PLCC Name Description1,2 1,2 HFI, HFO Hands freeI/Os:
These two pins canbe usedtoinsertan external Handfree circuit
suchasthe TEA 7540inthe receive path.HFOis anoutput which
provides thesignal issued fromoutput ofthe receive lowpass filter
while HFIis ahigh impendance input whichis connected directlyto
oneofthe inputsof theLoudspeaker amplifier.
3,4 3,4 VFr+,VFr– Receive analog earpiece amplifier complementary
outputs, capableof driving load impedances between 100
and 400Ωora piezo ceramic transducerupto 150nF.
These outputs can drive directly earpiece transductor. The
signalat this output can drivebe the summof: Receive Speech signal from DR, Internal Tone Generator, Sidetone signal. VCC Positive power supplyinputforthe digital section.+5V+ 10%.
6,7 6,7 LS-,LS+ Receive analog loudspeaker amplifier complementary outputs,
intendedfor drivinga Loudspeaker:80 mWon 50Ω load
impedance canbe providedat low distorsion meeting
specifications.
Alternatively this stage can drivea piezo transducerupto
600nF. The signalat these outputs canbethe sumof: Receive Speech signal from DR, Internal Tone generator, External input signal from EAIN input.
ST50884/33
PIN FUNCTIONS (continued)
PLCC Name Description 8,9 GND Ground:All digital signalsare referencedto this pin. 10 MS Mode Select:This input selects COMBOI/II interfacemode
with separate MICROWIRE Control interface when tied high
and GCI mode when tied low. 11 DX Transmit Dataouput: Datais shiftedouton thispin duringthe
assigned transmit time slots. ElsewhereDX outputisinthe
high impendance state.In COMBOI/II mode, voice data byte shiftedout from TRISTATE outputDXatthe MCLK
frequencyonthe rising edgeof MCLK.In GCI mode, voice
data byte and controlbytes are shiftedout from OPEN-DRAIN
outputDXat half the MCLK.An external pullup resistoris
needed. 12 AT Alternate Tone: Ring frequency outis controlled withoutμP
intervention. Tri-state logic controls:f1 (Vcc),f2 (GND), pause
(High Impedance). 15 DR Receive data input: Datais shiftedin during the assigned
Received time slots.Inthe COMBOI/II mode, voice data byte shiftedinatthe MCLK frequencyonthe falling edgesof
MCLK.Inthe GCI mode, PCM data byte and contol byte are
shiftedinat halfthe MCLK frequencyon the receiverising
edgesof MCLK. Thereis one period delaybetween transmit
rising edge and receive rising edgeof MCLK. 16 FS Frame Sync input: This signalisa 8kHz clock which defines
the startof the transmit and receive frames. Eitherof three
formats maybe usedfor this signal: non delayed timingmode,
delayed timing and GCI compatible timing mode. 17 MCLK Master Clock Input: This signalis usedbythe switched
capacitor filters and the encoder/decoder sequencing logic.
Values mustbe 512 kHz, 1.536 MHz, 2.048MHzor 2.56 MHz
selectedby meansof Control Register CRO. MCLKis used
also toshift-in and out data.In GCI mode, 2.56 MHz and 512
kHz arenot allowed. 18 LO Open drain output: logic1 written into DO (CR1) appearsat LOpinasa logic0 logic0 written into DO putsLOpinin highimpedance. – N.C. No connected. 22 MIC2+ Alternative positive high impedance inputto transmit pre-
amplifier. 23 MIC1+ Positive high impedanceinputto transmit pre-amplifierfor
microphone symetrical connection. 24 MIC1- Negative high impedance inputto transmit pre-amplifierfor
microphone symetrical connection. 21 TRO Tape Recorder Output: Thispin providesthe analog
combinationofTx voice signal andRx voice signal. 25 VCCA Positive power supplyinputforthe analog section.V+ 10%. VCC and VCCA mustbe directly connected
together. 26 MIC2- Alternative negative high impedance inputto transmit pre-
amplifier. 27 GNDA Analog Ground:All analog signals arereferencedto this pin.
GND and GNDA mustbe connected together closetothe
device. 28 EAIN External Auxiliary input: This input canbe used toprovide
alternate signalstothe Loudspeakerin placeof Internal Ring
generator. Input signal shouldbe voice band limited.
ST50885/33
FUNCTIONAL DESCRIPTION
Power on initialization:When poweris first applied, power on reset
cicuitry initializes PIAFE and putsit into the power
down state. Gain Control Registersfor the various
programmable gain amplifiers and programmable
switches are initializedas indicatedin the Control
Register description section.All CODEC functions
are disabled. Digital Interfaceis configuredin GCI
modeorin COMBOI/II mode dependingon Mode
Select pin connection.
The desired selection forall programmable func-
tions may be intialized priortoa power up com-
mand using Monitor channelin GCI modeor MI-
CROWIREportin COMBOI/II mode.
Power up/down control:Following power-on initialization, power up and
power down control maybe accomplishedby writ-
ing anyof the control instructions listedin Table1
into PIAFE with ”P”bit setto0 for powerupor1
for power down.
Normally,itis recommended thatall programma-
ble functions be initially programmed while the
deviceis powered down. Power state control can
then be included with the last programming in-
structionorina separate single byte instruction.
Anyof the programmable registers may also be
modified while ST5088is poweredupor downby
setting ”P” bit as indicated. When power up or
down controlis enteredasa single byte instruc-
tion,bit1 mustbe settoa0.
Whena powerup commandis given,all de-acti-
vated circuits are activated, but output DX will re-
mainin the high impedance stateonB time slots
until the secondFs pulse after power up, evenifa channelis selected.
Power down state:Followinga periodof activity, power down state
may be reentered by writinga power down in-
struction.
Control Registers remainin their current state and
canbe changed eitherby MICROWIRE controlin-
terface or GCI control channel depending on
mode selected. additionto the power down instruction, detec-
tionof loss MCLK (no transition detected) auto-
matically enters the devicein ”reset” power down
state with DX outputin the high impedance state
andL0in high impedance state.
Transmit section:Transmit analog interfaceis designedin two
stagesto enable gainsupto35 dBtobe realized.
Stage1isa low noise differential amplifier provid-
ing 20 dB gain.A microphone may be ca-
pacitevely connectedto MIC1+, MIC1- inputs,
while the MIC2+ MIC2– inputs may be usedto
capacitively connecta second microphone (for
digital handsfree operation)or an auxiliary audio
circuit suchas TEA 7540 Hands-freecircuit. MIC1 MIC2 sourceis selected with bit7of register
CR4.
Following the first stageisa programmable gain
Following pin definitions are used only when COMBOI/II mode with separate MICROWIRE com-
patible serial control portis selected. (MS input set equal one)
PIN FUNCTIONS (continued)
PLCC Name Description 13 CO Control data Output: Serial control/status informationis shifted
out fromthe PIAFEon thispin when CS-is lowon the falling
odgesof CCLK. 14 CI Control dataInput: Serial Control informationis shifted intothe
PIAFEon thispin when CS-is lowonthe rising edgesof CCLK. 19 CCLK Control Clock input: This clock shifts serial control information
intoCI andout from CO when the CS- inputis low, dependingthe current instruction. CCLK maybe asynchronous with
the other system clocks. 20 CS- Chip Select input: When thispinis low,control informationis
written into and out fromthe PIAFEviaCI and CO pins.
Following pin definitions are used only when the GCI modeis selected. (MS input set equal zero)
PIN FUNCTIONS (continued)
PLCC Name Description19,13,12,20 19,14,13,20 A0,A1,A2,A3 These pins selectthe addressof PIAFEon GCI interface and
mustbe hardwiredto either VCCor GND. A0,A1,A2,A3 referto
C4,C5,C6,C7 bitsofthe first address byte respectively.
ST50886/33
amplifier which provides from0to 15 dBof addi-
tional gainin1 dB step. The total transmit gain
shouldbe adjustedso that,at reference pointA,
see Block Diagram description, the internal0
dBmO voltageis 0.739V (overload levelis 1.06
Vrms). Second stage amplifier can be pro-
grammed with bits4to7of CR5. To temporarily
mute the transmit input,bit TE(6of CR4) maybe
set low.In this case, the analog transmit signalis
grounded and the sidetone pathis also disabled. active RC prefilter then precedes the 8th order
band pass switched capacitor filter. A/D converter
hasa compressing characteristic accordingto
CCITTAor mu255 coding laws, which must be
selectedby setting bits MA,IAin register CR0.A
precisionon chip voltage reference ensures accu-
rate and highly stable transmission levels.
Any offset voltage arisingin the gain-set amplifier,
the filtersor the comparatoris cancelledbyanin-
ternalautozero circuit.
Each encode cycle begins immediatlyat the be-
ginningof the selected Transmit time slot. The to-
tal signal delay referencedto the startof the time
slotis approximatively 195μs (dueto the transmit
filter) plus 123 μs (dueto encoding delay), which
totals 320 μs. Voice datais shifted outon DX dur-
ing the selected time slot on the transmit rising
adgesof MCLK.
Receive section:Voice Datais shifted into the decoder’s Receive
voice data Register via the DR pin during the se-
lected time sloton the8 receive edgesof MCLK.
The decoder consistsof an expanding DAC with
eitherA or MU255 law decoding characteristic
whichis selectedby the same control instruction
usedto select the Encode law during intitializa-
tion. Following the Decoderisa 3400 Hz 6th or-
der low pass switched capacitorfilter with integral
Sin X/X correctionfor the8 kHz sample and hold. dBmO voltageat this (B) reference point (see
Block Diagram description)is 0.49 Vrms.A tran-
scient suppressing circuitry ensure interference
noise suppressionat power up.
The analog speech signal output can be routed
eitherto earpiece (VFR+,VFR- outputs)orto loud-
speaker (LS+, LS- outputs)by setting bits SL and (1and0of CR4).
Total signal delayis approximatively 190μs (filter
plus decoding delay) plus 62.5 μs (1/2 frame)
which gives approximatively 252 μs.
Differential outputs VFR+,VFR- are intendedto di-
rectly drive an earpiece. Preceding the outputsis programmableattenuationamplifier, which must setby writingto bits4to7in register CR6. At-
tenuationsin the range0to -15 dB relativeto the
maximum levelin1 dB step canbe programmed.
The inputof this programmable amplifieris the
summof several signals which can be selected writingto register CR4.: Receive speech signal which has been de-
coded and filtered, Internally generated tone signal, (Tone ampli-
tudeis programmed with bits4to7of register
CR7), Sidetone signal, the amplitudeof whichis pro-
grammed with bits0to3of register CR5
VFR+ and VFR- outputsare capableof driving output
power level upto 14mW into differentially con-
nectedload impedance between 100 and 400Ω.
Differential outputs LS+,LS- are intendedto di-
rectly drivea Loudspeaker.Preceding the outputsa programmable attenuation amplifier, which
must be set by writingto bits0to3in register
CR6. Attenuationsin the range0to -30 dB rela-
tiveto the maximum levelin 2.0 dB step canbe
programmed. The inputof this programmable am-
plifier can be the summof signals which can be
selectedby writingto register CR4: Receive speech signal which has been de-
coded and filtered, Internally generated tone signal, (Tone ampli-
tudeis programmed with bits4to7of register
CR7), EAIN input which may be an alternate Ring
signalor any voice frequency band limited
signal. (An external decoupling capacitorof
about 0.1μFis necessary).
Receive voice signal may be directedto output
HFOby meansofbit HFEin Register CR4. After
processing, signal mustbe re-entered throughin-
put HFIto Loudspeaker amplifier input. (An exter-
nal decoupling capacitorof about 0.1μFis neces-
sary).
The output loudspeaker section has two switch-
able gainsof +9dB and +27dB.
+9dB LS GainThis gain modeis fully equivalent to PIAFE
ST5080 behaviour.
LS+ and LS- outputs are capableof driving output
power level upto 80 mW into 50Ω differentially
connected load impedanceat low distortion meet-
ing PCM channel specifications. When the signal
sourceisa Ring squarewave signal, power levelsto approximatively 200 mW canbe delivered.
+27dBLS GainAdditional gainof 18dB has the purposeto in-
crease the undistorted output power up to
150mW typical with digital input DR ranging from
-12dBm0to +3dBm0.
Output DC offsetis limitedby high pass filter with
35Hz cut frequency (with LS gain= +9dB cut fre-
quency= 9Hz)
Anti-acoustic feed-back for loudspeakerto hand-
set microphone loop with squelch effect:on chip
ST50887/33
switchable anti-larsen for loudspeakerto handset
microphone feedbackis implemented.A 12dB
depth gain control on both transmit and receive
pathis providedto keep constant the loop gain. the transmit path the 12dB gain controlis pro-
vided starting from the CR5 transmit gain defini-
tion;at the same time, on the receive path the
12dB gain controlis provided starting from CR6
receive gain definition.
DIGITAL ANTICLIPPING SYSTEM(D.A.S.) automatic anticlipping systemis necessaryto
avoid distortion on LS+/LS- when the output
swing approaches the supply rails. (LS GAIN >>
+9dB).
The digital anticlipping system calculates equiva-
lent input signalon DR pin and comparesit witha
selectable anticlipping threshold. The D.A.S.is
then ableto reduce the overall gainin orderto
avoidor limit the distortion.
Four different thresholds are programmable via
register:
-15dBm0 D< 1% Forsafe margin
-13dBm0 D= 1% Fornormal operation
-9dBm0 D≥ 1% Fornoisy ambient(*)
-7dBm0 D>>1% Forvery noisy ambient(*)
(*) When environmentis noisy, power output
mightbe more important than 1% distortion.
Gain reductionof the D.A.S. (Anticlipping Attack)
hasa fixed speedof 8KHz.
Gain recoveryor increase (Anticlipping Release)
has4 programmable speedsof 4Hz, 8Hz, 31Hz
and 62Hz.
TAPE RECORDER OUTPUT (TRO)This section providesa combinationof Tx and Rx
Analog Signalsto an external user likea re-
cordering machine. The output levels relativetoa
signalof 0dBm0on channelDx and DR are: TRO= 0.245VRMS (for 0dBm0on DR) TRO= 0.246VRMS (for 0dBm0on DX)
The single ended Op Ampis ableto drivean ex-
ternalloadas lowas 600Ω.
ALTERNATE TONE CONTROL (AT)This section allowsto simplify the microprocessor
controlof ringer operation. When pin ATis put ex-
ternallyat high impedance state (or left open) the
control of ring frequency emission is totally
througha microprocessor, which updatesin real
time the contentsof various registers.
When pin ATis forcedat GNDor Vcc the ring
generator emits respectively the frequenciesf2
(GND) andf1 (Vcc), previously defined through
registers CR9 (f2) and CR8(f1). This operative
mode requires only start-up interventionof the mi-
croprocessor.
Digital and Control Interface:PIAFE providesa choiceof eitherof two typesof
Digital Interfacefor both control data and PCM.
For compatibility with systems which use time slot
oriented PCM busses witha separate Control In-
terface,as used on COMBO I/II familiesof de-
vices, PIAFE functions are describedin next sec-
tion.
Alternatively, for systemsin which PCM and con-
trol data are multiplexed together using GCI inter-
face scheme, PIAFE functions are describedin
the section following the next one.
PIAFE will automatically switchto oneof these
two typesof interfaceby sensing the MS pin.
Dueto Line Transceiver clock recovery circuitry,a
low jitter may be provided on FS and MCLK
clocks. FS and MCLK must be alwaysin phase.
For ST5421S Transceiver, as an example,
maximun valueof jitter amplitudeisa stepof65at each GCI frame (125μs). So, the maximum
jitter amplitudeis 130ns pk-pk.
COMBOI/II mode.
Digital Interface (Fig.1) Frame Sync input determines the beginningof
frame.It may have any duration froma single cy-
cleof MCLKtoa squarewave. Two different rela-
tionships may be established between the Frame
Sync input and the first time slotof frameby set-
tingbit3in register CR0. Non delayed data mode similar to long frame timing on ETC5057/
TS5070 series of devices (COMBOI and
COMBOII respectively): first time slot begins
nominally coincident with the rising edgeof FS.
Alternativeisto use delayed data mode, whichis
similarto short frame sync timingon COMBOIor
COMBOII,in whichFS input mustbe highat least half cycleof MCLK earlier the frame beginning. time slot assignment circuit on chip may be
used with both timing modes, allowing connection oneof the twoB1 andB2 voice data channels.
Two data formats are available:in Format1, time
slot B1 correspondsto the8 MCLK cycles follow-
ing immediately the rising edgeof FS, while time
slot B2 correspondsto the8 MCLK cycles follow-
ing immediately time slot B1. Format2, time slot B1is identicalto Format1.
Time slot B2 appears twobit slots after time slot
B1. This two bits spaceis left availablefor inser-
tionof theD channel data.
Data formatis selected by bit FF (2)in register
CR0. Time slot B1or B2is selectedbybit T0 (0) Control Register CR1.
Bit EN (2)in control register CR1 enablesor dis-
ables the voice data transfer on DX and DR as
appropriate. During the assigned time slot, DX
ST50888/33
output shifts data out from the voice data register the rising edgesof MCLK. Serial voice datais
shifted into DR input during the same time sloton
the falling edgesof MCLK.isin the high impedance Tristate condition
whenin the non selected time slots.
Control Interface:Control informationor datais written intoor read-
back from PIAFE via the serial control port con-
sistingof control clock CCLK, serial data inputCI
and output CO, and Chip Select input, CS-. All
control instructions require2 bytesas listedin Ta-
ble1, with the exceptionofa single byte power-
up/down command. shift control data into ST5088, CCLK must be
pulsed high8 times while CS-is low. DataonCI
inputis shifted into the serial input registeron the
rising edgeof each CCLK pulse. Afterall datais
shiftedin, the contentof the input shift registeris
decoded, and may indicate thata 2nd byteof
control data will follow. This second byte may
either be defined bya second byte-wide CS-
pulseor may follow the first contiguously, i.e.itis
not mandatory for CS-to return highin between
the first and second control bytes.At the endof
Figure2: GCI InterfaceFrame Structure
Figure1: Digital Interface Format
ST50889/33
the 2nd control byte, datais loaded into the ap-
propriate programmable register. CS- must return
highat the endof the 2nd byte. read-back status information from PIAFE, the
first byteof the appropriate instructionis strobed during the first CS- pulse,as definedin Table CS- must be set low fora further8 CCLK cy-
cles, during which datais shifted outof the CO
pinon the falling edgesof CCLK.
When CS-is high, CO pinisin the high imped-
ance Tri-state, enabling CO pinsof several de-
vicestobe multiplexed together.
Thus,to summarise,2 byte READ and WRITEin-
structions may use either two 8-bit wide CS-
pulsesora single16bit wide CS- pulse.
Control channel accessto PCM interface:is possibleto access theB channel previously
selectedin Register CR1. byte written into Control Register CR3 will be
automatically transmitted from DX outputin the
following framein placeof the transmit PCM data. byte written into Control Register CR2 will be
automatically sent through the receive pathto the
Receive amplifiers. orderto implementa continuous data flow from
the Control MICROWIRE interfacetoaB chan-
nel,itis necessaryto send the control byte on
each PCM frame. current byte receivedon DR input canbe read the register CR2.In orderto implementa con-
tinuous data flow froma B channel to MI-
CROWIRE interface,itis necessaryto read regis-
ter CR2at eachPCM frame.
GCI COMPATIBLE MODEGCI interfaceis an European standardized inter-
faceto connect ISDN dedicated componentsin
the different configurationsof equipmentas Ter-
minals, Network Terminations, PBX, etc...a Terminal equipment, this interface called
SCITfor SpecialCircuit Interfacefor Terminalsal-
lows for example connection between: ST5421 (SID-GCI) and ST5451 (HDLC/GCI
controller) usedfor16 kbit/sD channel packet
frames processingand SID control, Peripheral devices connectedtoa 64 kbit/sB
channel and ST5451 used for GCI peripheral
control.
ST5088 may be assignedto oneof theB chan-
nels present on the GCI interface andis moni-
tored viaa control channel whichis multiplexed
with the64 kbit/s Voice Data channels.
Figure2 shows the frame structureat the GCIin-
terface. Two 256 kbit/s channel are supported.
a)GCI channel0:Itis structuredin four sub-
channels:B1 channel8 bits per frame
–B2 channel8 bits per frame channel8 bits per frame ignoredby PIAFE
–SC channel8 bits per frame ignored by
PIAFE
OnlyB1or B2 channelcanbe selectedin
PIAFEfor PCM data transfer.
b)GCI channel1:Itis structured alsoin four
subchannels:
–B1* channel8 bitsper frame
–B2* channel8 bitsper frame
–M* channel8 bits per frame
–SC* whichis structuredas follows: bits ignoredby PIAFEbit associatedwith M* channelbit associatedwith M* channel.
B1*or B2* channel canbe selectedin PIAFE
for PCM data transfer. channel and two associated bitsE* andA*
areused for PIAFE control.
Thus,to summarize, B1, B2, B1*or B2* channel
can be selectedto transmit PCM data and M*
channelis usedto read/write status/command pe-
ripheral device registers. Protocol for byte ex-
changeon the M* channel usesE* andA* bits.
Physical InterfaceThe interfaceis physically constitued with4 wires:
Input Data wire: DR
Output Data wire: DX
Bit Clock: MCLK
Frame Synchronization: FS
Datais synchronizedby MCLK andFS clock in-
puts. insures reinitializationof time slot counterat
each frame beginning. The rising edgeor FSis
the reference timefor the first GCI channel bit.
Datais transmittedin both directionsat half the
MCLK input frequency. Datais transmittedon the
the rising edgeof MCLK andis sampled one pe-
riod after the transmit rising edge, alsoona rising
edge.
Note: Transmit data maybe sampledby far-end
deviceie SID ST5421on the falling edge 1.5 pe-
riod afterthe transmit rising edge.
Unused channel are high impedance. Data out-
puts are OPEN-DRAIN and needan external pull resistor.
COMBO activation/deactivationST5088is automatically setin power down mode
when GCI clocks are idle. GCI sectionis reacti-
vated when GCI clocks are detected. PIAFEis
completly reactivated after receivingofa power command.
Exchangeprotocolon M* channel
ST508810/33
Protocol allowsa bidirectional transferof bytes
between ST5088 and GCI controller with acknow-
ledgment at each received byte. For PIAFE,
standard protocolis simplifiedto provide reador
write register cycles almost identicalto MI-
CROWIREserial interface.
Write cycleControl Unit sends through the GCI controller fol-
lowing bytes: First byteis the chip select byte. The first four
bits indicate the device address:
(A3,A2,A1,A0). The four last bits are ignored.
ST5088 compare the validated byte received
internally with the addressdefinedby pins A3,
A2, A1, A0.If comparisonis true, byteis ac-
knowledged,if not, ST5088 does not acknow-
ledge the byte.
NOTE: An internal ”messagein progress” flag re-
mains activetill the endof the complete message
transmissionto avoid irrelevant acknowledgement any furtherbyte. Second byteis structuredas definedin Ta-
ble1. Third byteis the Data byteto write into the
Registeras indicatedin Table1.is possible but optionalto writeto several differ-
ent registersina single message.In this case the
Chip Select byteis sent only onceat the begin-
ningof the message, the device automatically
toggles between address byte and data byte.
Read cycleControl Unit sends two bytes. First byteis the
chip select byteas defined above. Second byteis
structuredas definedin Table1. PIAFE identifiesa read-back cycle,bit2of bytein Table1 equal1,it hasto respondto the Con-
trol Unitby sendinga single byte message which the contentof the addressed register.is possible but optionalto request several differ-
ent read-back register cyclesina single message
butitis recommendedto wait the answer before
requestinga new read backto avoid lossof data.
ST5088 respondsby sendinga single data byte
messageat each request.
Received byte validation: received byteis validatedifitis detected two
consecutivetimes identical.
Exchange Protocol:Exchange protocolis identicalfor both directions.
Sender usesE*bitto indicate thatitis sendinga byte while receiver usesA*bitto acknowledge
received byte.
Whenno messageis transferred,E*bit andA*bit
are forcedto inactive state. transmissionis initializedby sender puttingE*
bit from inactive stateto active state andby send-
ing first byteon M* channelin the same frame.
Transmissionofa messageis allowed onlyif A*
bit from the receiver has been set inactive forat
least two frames.
When receiveris ready,it validates the received
byte internally when receivedin two consecutive
frames identical. Then the receiver sets firstA*bit
from inactive to active state (pre-acknow-
legement), and maintainsA*bit activeat leastin
the following frame (acknowledgement).If valida-
tionis not possible, (two last bytes received are
not identical), receiver aborts the message settingbit activefor onlya single frame.
For the first byte received, Abort sequenceis not
allowed. PIAFE does not respond eitherif two last
bytes are not identicalorif the byte received does
not meet the Chip Select byte definedby A0-A3
pins bias. second byte may be transmittedby the sender
putting E* bit from activeto inactive state and
sending the second byteon the M* channelin the
same frame. E* bitis set inactive for only one
frame.Ifit remains inactive more than one frame,is an endof message (i.e. not second byte
available).
The second byte maybe transmittedonly after re-
ceiving the pre-acknowledgmentof the previous
byte transmitted (see Fig. 3). The same protocol usedifa third byteis transmitted. Each byte
hasto be transmittedat leastin two consecutive
frames.
The receiver validates current received byte as
done on first byte and then setA*bitin the next
two frames first from activeto inactive state (pre-
acknowledgement), and after from inactiveto ac-
tive state (acknowledgement).If the receiver can-
not validate the received current byte (two bytes
received are not identical),it pre-acknowledges
normally, butletA*bitin the inactive statein the
next frame which indicatesan abort request.a message sent by ST5088is aborted,it will
stop the message and wait fora new read cycle
instructionfrom the controller. message receivedby ST5088is acknowledged aborted without flow Control.
Figures3 gives timingofa write cycle. Most sig-
nificantbit (MSB)ofa Monitor byteis sent firston channel. andA* bits are active low and inactive stateon
DOUTis high impedance.
PROGRAMMABLE FUNCTIONS
ST508811/33
Figure3:E andA bits Timing
ST508812/33
For both formatsof Digital Interface, programma-
ble functions are configuredby writingtoa num-
berof registers usinga 2-byte write cycle (notin-
cluding chip select bytein GCI).
Mostof these registers can also be read-backfor
verification. Byte oneis always register address,
while byte twois Data.
Table1 lists the register set and their respective
adresses.
Table1: Programmable Register Intructions
Function Address byte Data byte 54321 0
Single byte Power up/down P X X X X X 0 X none
Write CR0 P 0 00001 X see CR0 TABLE2
Read-back CR0 P 0 00011 X see CR0
Write CR1 P 0 00101 X see CR1 TABLE3
Read-back CR1 P 0 00111 X see CR1
Write Datato receive path P 0 01001 X see CR2 TABLE4
Read data fromDR P 0 01011 X see CR2
Write DatatoDX P 0 01101 X see CR3 TABLE5
Write CR4 P 0 10001 X see CR4 TABLE6
Read-back CR4 P 0 10011 X see CR4
Write CR5 P 0 10101 X see CR5 TABLE7
Read-back CR5 P 0 10111 X see CR5
Write CR6 P 0 11001 X see CR6 TABLE8
Read-back CR6 P 0 11011 X see CR6
Write CR7 P 0 11101 X see CR7 TABLE9
Read-back CR7 P 0 11111 X see CR7
Write CR8 P 1 00001 X see CR8 TABLE10
Read-back CR8 P 1 00011 X see CR8
Write CR9 P 1 00101 X see CR9 TABLE11
Read-back CR9 P 1 00111 X see CR9
Write CR10 P 1 01001 X see CR10 TABLE12
Read-back CR10 P 1 01011 X see CR10
NOTE1: bit7ofthe address byteand data byteis alwaysthefirstbit clocked intoorout from:CIandCO pins when MICROWIRE serial
port isenabled,or intoandout fromDR andDX pins when GCI mode selected.= reserved:write0
NOTE2: ”P”bitis Power up/downControlbit.P=1 Means PowerDown.
Bit1 indicates,if set,the presenceofa secondbyte.
NOTE3: Bit2 iswrite/read selectbit.
ST508813/33
Table2: Control Register CR0 Functions
6 54 32 10 FunctionF1 F0 MA IA DN FF B7 DLMCLK= 512 kHz
MCLK= 1.536 MHz
MCLK= 2.048 MHz
MCLK= 2.560 MHz
(1)
(1)
MU-law; CCITT D3-D4
MU-law; Bare Coding
A-law including evenbit inversion
A-law; Bare Coding
Delayed data timing
Non delayed data timing
*(1)
(1) andB2 consecutive andB2 separated
*(1)
(1) bits time-slot bits time-slot
Normal operation
Digital Loop-back state atpoweron initialization
(1): significantin COMBO I/IImode only
Table3: Control Register CR1 Functions
543 21 0 Function
HFE ALE DO MR MX EN T1 T0HFO/ HFI pins disabled
HFO/ HFi pins enabled
Anti-larsen disabled
Anti-larsen enabled latchis putin high impedance latchsetto0 connectedto rec. path
CR2 connectedto rec. path (1)
(1)
Trans path connectedtoDX
CR3 connectedtoDX (1)
(1)
voice data transfer disable
voice data transfer enable channel selected channel selected
B1* channel selected
B2* channel selected
(2)
(2) stateat poweron initialization
(1): significantin COMBOI/II mode only
(2): significantin GCI mode only.
ST508814/33
Table4: Control Register CR2 Functions
6 54 32 10 Functiond7 d6 d5 d4 d3 d2 d1 d0msb lsb Data sentto Receive pathor Data received fromDR input
Table5: Control Registers CR3 Functions
6 54 32 10 Function d6 d5 d4 d3 d2 d1 d0msb lsb DX data transmitted
Table6: Control Register CR4 Functions
6 54 32 10 Function TE SI EE RTL RTE SL SEMIC1 selected
MIC2 selected
Transmit input muted
Transmit input enabled
Internal sidetone disabled
Internal sidetone enabled
EAIN disconnected
EAIN selectedto Loudspeaker
Ring/ Tone muted
Ring/ Toneto Earpiece
Ring/ Toneto Loudspeaker
Ring/ Toneto Earpiece and Loudspeaker
Receive signal muted
Receive signal connectedto earpiece amplifer
Receive signal connectedto loudspeaker amplifier
Receive signal connectedto loudspeaker and
earpiece amplifier state atpoweron initialization
ST508815/33
Table7: Control Register CR5 Functions
6 54 32 10 Function
Transmit amplifier Sidetone amplifierdB gaindB gain1dB stepdB gaindB gaindB gain1dB step
-23dB gain stateat poweron initialization
Table8: Control Register CR6 Functions
6 54 32 10 Function
Earpiece ampifier LoudspeakerdB gaindB gain1dB step
-15dB gaindB gaindB gain2dB step
-30dB gain stateat poweron initialization
Table9: Control Register CR7 Functions
6 5 4 3 2 1 0 Function
Tone gain F1 F2 SN DE Attenuation f1 Vpp f2 Vpp....0dB*dBdBdB
-12dB
-15dB
-18dB
-21dB
-24dB
-27dB
...2.4(1)
....1.9(1)
0.08 andf2 muted selected selected andf2in summed mode
Squarewave signal selected
Sinewave signal selected
Normal operation *
Tone/ Ring Generator connected toTransmit path state atpoweron initialization
(1): value providediff1orf2is selectedalone.f1and f2are selectedinthe summed mode, f1=1.34Vpp while f2=1.06Vpp.
Outputgeneratoris 2.4Vpp reserved: write0
ST508816/33
Table 10: Control Register CR8 Functions
6 54 32 10 Function
f17 f16 f15 f14 f13 f12 f11 f10msb lsb Binary equivalentof the decimal number usedto calculatef1
Table 11: Control Register CR9 Functions
6 54 32 10 Function
f27 f26 f25 f24 f23 f22 f21 f20msb lsb Binary equivalentof the decimal number usedto calculatef2
Table 12: Control Register CR10Functions
6 54 32 10 Function
GLS ACE VT1 VT0 FD1 FD0 DFT HFT+27dB intoLH Path
(*) +9dB intoLH Path
Anticlipping ON
(*) Anticlipping OFF
(*) -15dm0 Anticlipping Threshold
-13dm0 Anticlipping Threshold
-9dm0 Anticlipping Threshold
-7dm0 Anticlipping Threshold
(*) 256ms Gain Recovery Time Constant/ (4Hz)
128ms Gain recovery Time Constant/ (8Hz)
32ms Gain Recovery TimeConstant/ (31Hz)
16ms Gain Recovery TimeConstant/ (62Hz)
(*) Standard Frequency Tone Range
Halved Frequency Tone Range
Doubled Frequency Tone Range
Forbidden
(*) Default values insertedinto theRegisterat PowerOn.
ST508817/33
