ST40RA200XH6 Fast Delivery |IC PHOENIX CO.,LIMITED

ST40RA200XH6 ,32-bit Embedded SuperH DeviceTable of ContentsChapter 1 Scope of this document . . . . .6Chapter 2 ST40 documentation suite ..
ST485ABD ,VERY HIGH SPEED LOW POWER RS-485/RS422 TRANSCEIVERELECTRICAL CHARACTERISTICSV = 4.5V to 5.5V, T = -40 to 85°C, unless otherwise specified. Typical va ..
ST485ABDR ,VERY HIGH SPEED LOW POWER RS-485/RS422 TRANSCEIVERAPPLICATIONS■ -7 TO 12 COMMON MODE INPUT VOLTAGERANGE■ DRIVER MANTAINS HIGH IMPEDANCE IN3-STATE ORW ..
ST485ABN ,VERY HIGH SPEED LOW POWER RS-485/RS422 TRANSCEIVERPIN CONFIGURATIONPIN DESCRIPTIONPlN N° SYMBOL NAME AND FUNCTIONReceiver Output. If A>B by 200mV, RO ..
ST485B ,LOW POWER RS-485/RS-422 TRANSCEIVERABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Supply Voltage7VCCV Control Input Voltage (RE, ..
ST485B ,LOW POWER RS-485/RS-422 TRANSCEIVERPIN CONFIGURATIONPIN DESCRIPTIONPlN N° SYMBOL NAME AND FUNCTION1 RO Receiver Output2RE Receiver Out ..
STM8AF52A8TCY ,Automotive CAN and LIN line 8-bit MCU with 128 Kbytes Flash, 24 MHz CPU, integrated EEPROMFeatures . 175.5.2 16 MHz high-speed internal RC oscillator (HSI) . . 175.5.3 128 kHz low- ..
STM8AF52A8TDY ,Automotive CAN and LIN line 8-bit MCU with 128 Kbytes Flash, 24 MHz CPU, integrated EEPROMThermal characteristics . . . . 60Table 25. Operating lifetime 60Table 26. General oper ..
STM8AF52AATAY ,Automotive CAN and LIN line 8-bit MCU with 128 Kbytes Flash, 24 MHz CPU, integrated EEPROMBlock diagram . . . . . 135 Product overview . . 145.1 STM8A central processing unit (C ..
STM8AF52AATDY ,Automotive CAN and LIN line 8-bit MCU with 128 Kbytes Flash, 24 MHz CPU, integrated EEPROMAbsolute maximum ratings . . . . 5910.3 Operating conditions 6110.3.1 VCAP external capac ..
STM8AF6226TCSSSY ,Automotive LIN line 8-bit MCU with 8 Kbytes Flash, 16 MHz CPU, integrated EEPROMFeatures CAPCOM channels (IC, OC or PWM)  8-bit basic timer with 8-bit prescaler Core  Auto wak ..
STM8AF6246TCSSSY ,Automotive LIN line 8-bit MCU with 16 Kbytes Flash, 16 MHz CPU, integrated EEPROMThermal characteristics . . . . . . 7410.4.1 Reference document . . . . . . . 7510.4.2 Sel ..

ST40RA200XH6
32-bit Embedded SuperH Device
DATASHEET
Overview
The ST40RA is the first member of the ST40 family. Based
on the SH-4, SuperH CPU core from SuperH Inc, the
ST40RA is designed to work as a standalone device, or as
part of a two chip solution for application specific systems.
Example applications the ST40RA is designed for include
digital consumer, embedded communications, industrial
and automotive. The high connectivity of the ST40 through
its PCI bus and its dual memory uses makes it a versatile
device, ideal for data-intensive and high performance
applications.
System features 32-bit SuperH CPU 64-bit hardware FPU (1.16 GFLOPS) 128-bit vector unit for matrix manipulations 166 MHz, 300 MIPS (DMIPS 1.1) Up to 664 Mbytes/s CPU bandwidth Direct mapped, on-chip, ICache (8 Kbytes) and DCache
(16 Kbytes) High-performance 5-channel DMA engine,
supporting 1D or 2D block moves and linked lists SuperHyway internal interconnect Memory protection and VM system support 64-entry unified TLB, 4-entry instruction TLB 4 Gbytes address space Standard ST40 peripherals 2 synchronous serial ports with FIFO (SCIF) Timers and a real-time clock
IO devices Mailbox register for interprocessor communication Additional PIO
Bus interfaces Local memory interface SDRAM & DDR SDRAM Up to 100 MHz (1.6 Gbytes/s peak throughput) PCI interface - 32-bit, 66/33 MHz, 3.3 V Enhanced memory interface (EMI) 32-bit bus, up to 83 MHz, for attaching peripherals High-speed, sync mode, burst flash ROM support SDRAM support MPX initiator and target interface Programmable MPX bus arbiter
ST40RA
32-bit Embedded SuperH Device
able of ContentsChapter 1 Scope of this document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Chapter 2 ST40 documentation suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
CPU documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
System documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chapter 3 ST40RA devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Chapter 4 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2 ST40 system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2.1 SuperH ST40 SH-4 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2.2 SuperHyway internal interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2.3 Standard ST40 peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.3 Bus interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.3.1 Local memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.3.2 PCI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3.3 EMI/MPX interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.4 I/O devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.4.1 Mailbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.5 Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.5.1 Development systems and software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.5.2 Software compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chapter 5 System configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
5.1 System addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1.1 System address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2 System identifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.3 Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3.1 ST40 core interrupt allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3.2 ST40 standard system interrupt allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3.3 ST40RA I/O device interrupt allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.4 GPDMA channel mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.5 EMI DACK mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.7 EMI pin to function relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.8 Memory bridge control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.8.1 Memory bridge control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.8.2 Memory bridge status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.8.3 Changing control of a memory bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.9 System configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.9.1 EMI.GENCFG EMI general configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.9.2 LMI.COC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.9.3 LMI.CIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.9.4 SYSCONF registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.9.5 SYSCONF.SYS_CON2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.9.6 PIO alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.9.7 PCI.PERF register definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Chapter 6 Clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
6.1 Clock domains and sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.2 Recommended operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.3 Clocks and registers at start up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.3.1 CLOCKGENA_2x PCI (PCI_DIV_BYPASS = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.3.2 Division ratios on CLOCKGENA_2x. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.4 Setting clock frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.4.1 Programming the PLL output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.4.2 Changing clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.4.3 Changing the core PLL frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.4.4 Changing the frequency division ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.5 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.5.1 CPU low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.5.2 Module low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.6 Clock generation registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.6.1 CLOCKGENB.CLK_SELCR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.6.2 CPG.STBCR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.6.3 CLOCKGENA.STBREQCR and CLOCKGENB.STBREQCR registers . . . . . . . . . . . . . . . . . . . . . . 41
6.6.4 CLOCKGENA.STBREQCR_SET and CLOCKGENB.STBREQCR_SET registers . . . . . . . . . . . . . 41
6.6.5 CLOCKGENA.STBREQCR_CLR and CLOCKGENB.STBREQCR_CLR register . . . . . . . . . . . . 41
6.6.6 CLOCKGENA.STBACKCR and CLOCKGENB.STBACKCR register . . . . . . . . . . . . . . . . . . . . . . 42
Chapter 7 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
7.1 DC absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.1.1 Fmax clock domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.1.2 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.1.3 Pad specific output AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.2 Rise and fall times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.3 PCI interface AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.4 LMI interface (SDRAM) AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7.5 LMI interface (DDR-SDRAM) AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
7.6 DDR bus termination (SSTL_2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
7.7 General purpose peripheral bus (EMI) AC specifications . . . . . . . . . . . . . . . . . . . . . . . 54
7.8 PIO AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
7.9 System CLKIN AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
7.10 Low power CLKIN AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
7.11 UDI and IEEE 1149.1 TAP AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Chapter 8 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
8.1 Function pin use selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
8.2 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
8.3 PBGA 27 x 27 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
8.4 Pin states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Chapter 9 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Appendix A Interconnect architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
A.1 Arbitration schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
A.1.1 PCI arbiter: (CPU, GPDMA, PCI, EMPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
A.1.2 EMI arbiter: (CPU buffer, GPDMA, PCI, EMPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
A.1.3 LMI 1 arbiter: (CPU, GPDMA, PCI, EMPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
A.1.4 PER arbiter: (CPU, GPDMA, PCI, EMPI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
A.1.5 LMI2 arbiter: (CPU, GPDMA, PCI, EMPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
A.1.6 Return arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
A.2 Interconnect registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
A.2.1 LMI1 arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
A.2.2 LMI2 arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
A.2.3 EMI arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
A.2.4 PCI arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
A.2.5 Peripheral arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
B.1 ST40 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
B.1.1 tas.b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
B.1.2 Store queue power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
B.1.3 UBC power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
B.1.4 System standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
B.2 PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
B.2.1 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
B.2.2 Type 2 configuration accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
B.2.3 Software visible changes between STB1HC7 and ST40RAH8D . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
B.2.4 Error behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
B.2.5 Master abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
B.3 EMI/EMPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
B.3.1 EMPI burst mode operation: ST40RA MPX target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
B.3.2 SDRAM initialization during boot from flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
B.3.3 MPX boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
B.4 Mailbox. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
B.4.1 Test and set functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
B.5 Power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
B.5.1 Module power-down sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
B.5.2 Accesses to modules in power-down state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
B.6 PIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
B.6.1 PIO default functionality following reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
B.6.2 PCI/PIO alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
B.7 Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
B.7.1 Memory bridge functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
B.7.2 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
B.7.3 Pad drive control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
B.8 GPDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
B.8.1 Linked list support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
B.8.2 2-D transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
B.8.3 Protocol signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Scope of this documentThis document describes only those areas of the ST40RA that are device specific, for example the
system address map. Information that is generic to the ST40 family of devices is contained in the
ST40 documentation suite.
2 ST40 documentation suite
This document references a number of other generic ST40 documents that combined together form
a complete datasheet.
CPU documentation
The SH-4 CPU core and its instruction set are documented in the SH-4 CPU Core Architecture
Manual.
System documentation
Devices listed in the system address map, Figure 2 on page 13 are documented in the ST40
System Architecture Manual: Volume 1: System, details the ST40 CPU and standard peripherals, Volume 2: Bus Interfaces, details the standard PCI, LMI and EMI bus interfaces. ST40RA devices
Table 1: ST40RA device types
4 Architecture
4.1 Overview
The ST40RA combines an SH-4, 32-bit microprocessor with a wide range of interfaces to external
peripherals. This section briefly describes each of the features of the ST40RA.
4.2 ST40 system
4.2.1 SuperH ST40 SH-4 core
Figure 1 illustrates the system architecture of the ST40 SH-4 core. The following section briefly
describes the features and performance of the core.
Central processing unit
The central processing unit is built around a 32-bit RISC, two-way superscalar architecture.
Operating at 166 MHz it runs with high code density using fixed length 16-bit instructions. It has a
load/store architecture, delayed branch instruction capability and an on-chip multiplier. It uses a
five-stage pipeline.
Figure 1: ST40 SH-4 core architecture
Floating point unit/multiply and accumulate
The on-chip, floating point coprocessor executes single precision (32-bit) and double precision
(64-bit) operations. It has a five-stage pipeline and supports IEEE754-compliant data types and
exceptions. It has rounding modes: (round-to-nearest) and (round-to-zero), and handles
denormalized numbers (truncation-to-zero) or interrupt generation for compliance with IEEE754.
The floating point unit performs the following functions: fmac (multiply-and-accumulate), fdiv (divide), fsqrt (square root) instructions, 3-D graphics instructions (single-precision): 4-dimensional vector conversion and matrix operations (ftrv): 4 cycles (pitch), 7 cycles
(latency), 4-dimensional vector (fipr) inner product: 1 cycle (pitch), 4 cycles (latency).
MMU configuration
There is 4 Gbytes virtual address space with 256 address space identifiers (8-bit ASIDs),
supporting single virtual and multiple virtual memory modes. Page sizes are 1 Kbyte, 4 Kbytes, 64
Kbytes or 1 Mbyte. The MMU supports four-entry, fully associative ITLB for instructions and
64-entry fully associative UTLB for instructions and operands. Software-controlled replacement and
random-counter replacement algorithms are also supported. The physical address space is 512
Mbytes (29-bit), see Figure 2: System address organization on page 12.
Cache
8 Kbytes of direct-mapped instruction cache are organized as 256 32-byte lines, and 16 Kbytes of
direct-mapped operand cache are organized as 512 32-byte lines. RAM mode (8-Kbyte cache plus
8-Kbyte RAM) with selectable write method (copy back or write through) is supported. A single
stage buffer for copy-back and a single stage buffer for write-through are available. The cache
contents can be address mapped and there is a 32-byte two-entry store queue.
4.2.2 SuperHyway internal interconnect
The ST40RA uses the SuperHyway memory mapped packet router for on-chip intermodule
communication. The interconnect supports a split transaction system allowing a nonblocking high
throughput, low latency system to be built. There are separate request and response packet
routers.
The ST40RA SuperHyway implementation is show in Section 5.8: Memory bridge control on
page 21. The interconnect allows simultaneous requests between multiple modules and is able to
ensure a very high data throughput with in many cases zero routing, arbitration and decode
latencies.
4.2.3 Standard ST40 peripherals
Synchronous serial channel
There are two ST40 compatible full duplex communication channels (SCIF1, SCIF2).
Asynchronous mode is supported. A separate 16-byte FIFO is provided for the transmitter and
receiver.
Interrupt controller
The interrupt controller supports all of the on-chip peripheral module interrupts, and five external
interrupts (NMI and IRL0 to IRL3). The priority can be set for each on-chip peripheral module
interrupt. IRL0 to IRL3 are configured as four independent interrupts or encoded to provide 15
Debug controller
Debugging is performed by break interrupts. There are two break channels. The address, data
value, access type, and data size can all be set as break conditions. Sequential break functions are
supported.
The user debug interface (UDI) contains a five-pin serial interface conforming to JTAG, IEEE
Standard TAP and boundary scan architecture. The interface provides host access to the 1 Kbyte
ASERAM for emulator firmware (accessible only in ASE mode).
Timers
The three-channel, auto-reload, 32-bit timer has an input capture function and a choice of seven
counter input clocks.
Real-time clock
The built-in 32-kHz crystal oscillator has a maximum 1/256 second resolution. It has dynamically
programmable operating frequencies and on-chip clock and calendar functions. It has two sleep
modes and one standby mode.
Watchdog timer
The ST40RA has an 8-bit watchdog timer (WDT) with programmable clock ratio. The WDT is able
to generate a power-on reset or a manual reset.
Programmable PLLs
The ST40RA has three programmable PLLs. The PLLs are configured by MODE pins at reset and
then reconfigured by software to optimize system performance or reduce system power
consumption.
General-purpose DMA controller
The five-channel physical address GPDMA controller has four general-purpose channels for
memory-to-memory or memory-to-peripheral transfers, and one buffered multiplexed channel. Both
2-D block moves and linked lists are supported. Two sets of DMA handshake pins are available for
use by external devices to support efficient transfer interdevice transfers via external interfaces
such as the EMI MPX.
Parallel I/O module
24 bits of parallel I/O are provided from the ST40 compatible PIO. Each bit is programmable as an
output or an input. “Input compare” generates an interrupt on any change of any input bit.
4.3 Bus interfaces
4.3.1 Local memory interface
The LMI supports 16-, 32- and 64-bit wide bus SDRAM and DDR SDRAM, at up to 100 MHz with a
maximum address space of 112 Mbytes. Devices supported include two and four bank 16-, 64-,
128- and 256-Mbit technologies in x4, x8, x16 and x32 packages. The LMI pads are dual mode
pads electrically compatible with LVTTL (for standard SDRAM) and SSTL_2 (for DDR SDRAM). For
full detail of the configuration options of the LMI please see ST40 System Architecture Manual,
Volume 2: Bus Interfaces.
4.3.2 PCI interface
The PCI interface complies to the PCI v2.1 and Power Management Interface V1.0 specifications. It
is 32 bits wide and operates at 33or 66 MHz. Master and target mode are supported. A PCI arbiter
and clock generator is provided inside the ST40RA. For details on the configuration options for the
PCI interface please see ST40 System Architecture Manual, Volume 2: Bus Interfaces.
4.3.3 EMI/MPX interface
The EMI/MPX interface contains the following blocks. For full details of the configuration options of
the EMI please see the ST40 System Architecture Manual, Volume 2: Bus Interfaces.
EMI memory interface initiator
The EMI provides access to ROMs, SDRAM, memory mapped asynchronous external peripherals
and synchronous MPX bus peripherals. The EMI supports burst mode flash ROM and MPX for
memory-mapped device coupling. The ST40RA GPDMA unit accesses external devices and two
sets of DMA channels control signals are provided for this purpose.
EMPI memory interface target
The EMPI is a synchronous MPX target that allows for an external MPX initiator to access the
ST40RA internal memory space. The EMPI contains a general purpose control channel and four
high performance channels each of which implements a write buffer and a pair of 32-byte read-
ahead buffers able to optimize external device burst access to and from the ST40RA internal
memory. These buffers can be associated with memory regions within the ST40RA and external
DMA channels. Four sets of DMA handshake signals are provided to the EMPI to optimize long
burst transfers between the ST40RA and external initiators like the STi5514.
MPX bus arbiter
The ST40RA has an internal programmable bus arbiter to optimize utilization of the MPX bus. The
ST40RA MPX arbiter supports one external initiator and has programmable bus priority (ST40RA or
external device), bus parking (ST40RA, external, idle or last user) and latency timers. The internal
arbiter can be bypassed if an external arbiter supporting more initiators is required.
4.4 I/O devices
4.4.1 Mailbox
The ST40 and the external microprocessor communicate with each other and synchronize their
activities using the memory-mapped mailbox. Processes generate interrupts to either CPU, and
send and receive messages between the two CPUs. There are buffers for message queueing in
both directions and interrupt bits can be set in each direction. Access to the mailbox from external
devices is through the ST40RA EMPI or the PCI target interface.
4.5 Software
4.5.1 Development systems and software
The ST40RA supports application development, with a full range of debug features and an
emulation mode (ASE). The ASE mode has a dedicated 1-Kbyte buffer for emulator firmware,
supporting performance counters and branch trace. The ST40RA, with its memory management
unit, supports standard operating systems including WindowsCE and Linux. The ST40 has a wide
range of development support from ST and third parties, and efficiently runs applications written in
ST’s own tools include: C/C++ compilers, debugger, proprietary OS.
Third parties include: Microsoft: WindowsCE, Sun: JavaOS for consumers, WindRiver: VxWorks, T ornado tools, Linux, Insignia JVM, ANT browser.
4.5.2 Software compatibility
SH-4 core software
The ST40RA SH-4 core is binary code compatible with the Hitachi SH775x family.
Standard peripheral driver
The ST40 standard SCIF, timer, real-time clock and PIO are compatible with the ST40 SOC range
of devices and the Hitachi SH775x family.
Bus interface driver
The PCI, LMI, and EMI interfaces are register compatible with the ST40 SOC range of devices.
The ST40RA contains an EMPI and MPX arbiter and MPX clock control unit which are additional to
the bus interface components of the ST40 SOC range of devices.
I/O device driver
The Mailbox is a module with no ST legacy software. System configuration
The ST40RA system address map has been designed to maintain compatibility with existing ST40
family devices and other STMicroelectronics devices.
The SH-4 core and core peripherals maintain compatibility with the ST40 SOC range of devices and
Hitachi SH7750 wherever possible.
Devices listed in Table 2: ST40RA system address map on page 13, are documented in the ST40
System Architecture Manual as described in Chapter 2: ST40 documentation suite on page6.
Coherency between the cache and external memory is assured by software. The ST40 CPU has
cache control instructions which enable software to do this. Details of these instructions are given in
the ST40 CPU Core Architecture Manual.
The ST40RA power on configuration is controlled by the MODE pins as defined in Table 34: Mode
selection pins for ST40RA on page 59.
Subsystem configuration registers are usually found with the module register space. Other system
level functions and the software register locations are shown in Table 11: System configuration
registers on page 23.
5.1 System addresses
The ST40 family system address organization is shown in Figure2.
Figure 2: System address organization
5.1.1 System address map
Table 2: ST40RA system address map
5.2 System identifiers SH-4 core processor identity: 0x0100. SH-4 core processor version: 0x0541D. ST40RA-HC8 TAP identity: 05141041. ST40RA-HC8 PCI identity: Vendor: 104A, Device: 4000, Revision ID: 0x01, Class: 0x4 0000, Subsystem ID: 0x0000. For information about which address region to access for each module, see SH-4 32-bit CPU Core
Architecture, sections 2.5 and 3.4.
When operating in privilege mode, these registers should be accessed via the P2 region by adding
an offset of 0xA000 0000, when operating in user mode, access should be via the U0 address.
Table 2: ST40RA system address map
5.3 Interrupt mapping
For full details on the interrupt controller see ST40 System Architecture Manual Volume 1:System.
The mapping of the CPU interrupts is described in Section 5.3.1, Section 5.3.2 and Section 5.3.3.
Note: Some INTEVT codes are shown as reserved in Table 3 and therefore cannot be generated by this
device.
5.3.1 ST40 core interrupt allocation
The allocation of core interrupts is as shown in Table3.
Table 3: ST40 core interrupt allocation (page 1 of 2)
5.3.2 ST40 standard system interrupt allocation
Standard ST40 family interrupts are mapped as shown in Table4.
Table 3: ST40 core interrupt allocation (page 2 of 2)
5.3.3 ST40RA I/O device interrupt allocation
5.4 GPDMA channel mapping
For full details of the GPDMA controller see ST40 System Architecture Manual Volume 1: System.
The ST40RA general purpose DMA controller channel map is shown in Table6.
Table 5: Mailbox and EMPI interrupt allocation
Table 6: GPDMA request number allocation
5.5 EMI DACK mapping
For full details of the EMI bank address and bank type mappings refer to ST40 System Architecture
Manual Volume 2: Bus Interfaces.
Two DACK strobes are supported in this implementation and are mapped as follows: DACK[0]: asserted when a transfer from GPDMA channel[1] occurs to an EMI bank configured
as a MPX device, DACK[1]: asserted when a transfer from GPDMA channel[2] occurs to an EMI bank configured
as a MPX device.
5.6 EMI address pin mapping
The data width of a connected device is 8, 16 or 32 bits wide. The 16-bit bank must use EDQM3 as
address 1, the LSB address for the device and the 8-bit bank must use EDQM3 as address 1 and
EDQM2 as address 0.
See the ST40 System Architecture Manual, Volume 2: Bus Interfaces for details of setting the
device type and port size using the EMI configuration registers.
Table 7: Mapping the internal address lines of a connected device
5.7 EMI pin to function relationship
Table 8: EMI pin functions
When the EMI is configured in master mode (MODE9 = H), and an external slave DMA asks for access to the bus (using NOTMACK or NOTMREQ), RFSH_PENDING and ACC_PENDING are
used to signal that, while the external DMA request has been granted and the DMA is using the bus,
a refresh time out occurred, or that the EMI has been asked for a new access. A bus arbiter, if
present, can use this information to give back the bus to the EMI to allow a refresh operation, or
improve bandwidth. When the EMI is in slave mode (MODE9 = L), RFSH_PENDING is always
deasserted (so EPENDING = ACC_PENDING), and the pin is used to signal to the external bus
arbiter that the EMI needs to use the bus. NOTFBAA is an output of the ST40RA, and an input to the memory device. The pin must be left
unconnected from the ST40RA side and tied low at the memory device side if the memory is an Intel
or an STM part. It needs to be connected if the SFlash is an AMD.
Table 8: EMI pin functions
5.8 Memory bridge control
The architecture of the SuperHyway interconnect is shown in Figure 3. Initiators are shown on the
left, and targets are shown on the right of the interconnect. The bit width of the initiator and target
ports are shown in the diagram.
The ST40RA architecture requires seven memory bridges on clock change boundaries.
Figure 3: ST40RA interconnect architecture
Table 9: Memory bridges
5.8.1 Memory bridge control signals
Each memory bridge has seven control signals as defined in Table 10.
5.8.2 Memory bridge status
The memory bridge control signals are looped back to the ST40RA comms subsystem SYS_STAT1
register for test purposes. The format of this read-only register is shown in Section 5.9.4.1:
SYSCONF.SYS_STAT1. on page 26.
5.8.3 Changing control of a memory bridge
At reset all these bridges are set to be synchronous. After reset and boot the function of these
memory bridges can be changed. See Section 5.9.4: SYSCONF registers on page 26. The
procedure for changing the control of a memory bridge is given below. Ensure no initiators are accessing the subsystem the bridge is connected to and ensure the
subsystem cannot initiate any requests to the SuperHyway. Stop the clock to the subsystem. Change the memory bridge configuration using the SYS_CONF.SYS_CON1 register as
detailed in Table 10. Restart the clock to the subsystem and reinitialize the system.
Table 10: Memory bridge control signals
5.9 System configuration registers
Table 11 outlines the ST40RA system configuration registers.
Table 11: System configuration registers
5.9.1 EMI.GENCFG EMI general configuration If the EWAIT signal is set at the beginning of an access, and the data is to be set after the EWAIT
is cleared, the parameters ACCESSTIMEREAD and LATCHPOINT in the EMI configuration
registers must be set as follows:
ACCESSTIME > LATCHPOINT + 3.
See the ST40 System Architecture Manual, Volume 2: Bus Interfaces for details of setting the EMI
configuration registers.
5.9.2 LMI.COC
5.9.3 LMI.CIC
5.9.4 SYSCONF registers
All ST40 systems contain a number of general purpose configuration registers which may be used
to configure system logic.
The definition of the general registers and their access functions is defined in the ST40 System
Architecture Manual.
For ST40RA the bits within these registers have the following function.
5.9.4.1 SYSCONF.SYS_STAT1.
5.9.4.2 SYSCONF.SYS_CON1.
Where the two clocks are sourced from independent PLLs the bridge must be put in asynchronous
mode.
5.9.5 SYSCONF.SYS_CON2.

5.9.6 PIO alternate functions
The function of pads with PIO alternate functions are controlled by the PIO.PC0, PIO.PC1 and
PIO.PC2 registers.
In the ST40RA device, the operational modes for these registers differ from the standard
architecture definition and are shown in Table 12. State following reset
Table 12: PIO alternate function registers
5.9.7 PCI.PERF register definition. Clock generation
The ST40 clock architecture has been organized to maintain compatibility across the ST40 family
and allow additional flexibility to increase system performance where required. It includes a more
diverse range of peripherals and provides low power use.
6.1 Clock domains and sources
Figure 4 shows possible clock domains for ST40RA clocks. The ST40RA implementation includes
two CLOCKGEN macros, which supply up to three independent clock domains across the chip
Each PLL may be independently programmed to produce a clock at a specific frequency which is
used to derive a series of related clocks which may be used by the system.
The clock domains mapping is shown in Table 13. The architecture of the ST40RA CLOCKGEN
subsystem consists of two standard (ST40 family) CLOCKGEN units (CLOCKGENA and
CLOCKGENB) and a CLOCKCON block. Figure 5 shows the architecture of the ST40RA
CLOCKGEN subsystem.
Figure 4: ST40RA clock domains
The sources for PCI_SS_CLK and EMI_SS_CLK, can be set using the PCI_SEL and EMI_SEL bits
in the CLOCKGENB.CLK_SELCR register. See Section 6.6.1: CLOCKGENB.CLK_SELCR register
on page 39.
If CLOCKGEN_A13 is used as PCI_SS_CLK source then the memory bridges 6 and 7 must be
enabled. If CLOCKGEN_A12 is used, then the bridges may be placed in bypass mode. This is the
recommended mode of operation.
If either CLOCKGEN_B12 or CLOCKGEN_A14 are used as the EMI_CLK, the memory bridges 1, 2
and 3 must be enabled. If CLOCKGEN_A12 is used, then the bridges may be placed in bypass.
This is the recommended mode of operation.
See Chapter 5.8: Memory bridge control on page 21.
Table 13: Clock domains Clock naming: CLOCKGEN_[CLOCKGEN label][PLL number][clock number]
Figure 5: ST40RA CLOCKGEN subsystem
6.2 Recommended operating modes
6.3 Clocks and registers at start up
Table 14: Supported operating frequencies
Table 15: CLOCKGENA PLL1 reset values
6.3.1 CLOCKGENA_2x PCI (PCI_DIV_BYPASS = 0)
6.3.2 Division ratios on CLOCKGENA_2x
Table 16: CLOCKGENA PLL2 reset values (PCI_DIV_BYPASS = 0)
Table 17: CLOCKGENA_PLL2 PCI reset division ratios.
6.4 Setting clock frequencies
Table 18 shows valid FRQCR ratios and the associated clock frequencies for derived clocks.
Table 18: Valid FRQCR values and their ratios
6.4.1 Programming the PLL output frequency
The three dividers used within the PLL are referred to as M (predivider), N (feedback divider) and P
(postdivider) for brevity. Note that there is a divide-by-2 fixed prescaler before the feedback divider.
The binary values applied to the programmable dividers, and the frequency of CLOCKIN controls
the output frequency of the PLL macrocell:
where the values of M, N and P must satisfy the following constraints: Divider limits: , Phase comparator limits: , VCO limit: , M divider limit:
For example, if 300 MHz from an input clock of 33 MHz is to be generated, the values of M, N and
P are worked out as below. The phase comparator must operate between 1 MHz and 2 MHz, so choose M = 22 (for
1.5 MHz operation). The VCO needs to run between 200 MHz and 622 MHz. It could be run at 300 MHz directly
(which takes a little less current), or at 600 MHz then divide by 2 to ensure an exact 50% duty
cycle. In this example 600 MHz is chosen so N = 200. The postdivider then needs to be a divide by 2. This is programmed in powers of 2, so P = 1.
The P divider changes value without glitching of the output clock.
6.4.2 Changing clock frequency
The clock frequencies are changed in two ways. Change the core PLL frequencies.
The PLL must be stopped, the control register reconfigured with the new settings, and the PLL
restarted at the new frequency. Change the frequency division ratio of the clock domains.
The control registers are changed dynamically and the new frequencies are effective
immediately.
6.4.3 Changing the core PLL frequencies
This procedure applies to either CLOCKGENA or CLOCKGENB and to PLL1 or PLL2. Stop the PLL. The CLOCKGENA.PLL1CR2.STBPLLENSEL register selects whether the PLL
is enabled by the CLOCKGENA.PLL1CR2.STBPLLEN or the CPG.FRQCR.PLL1EN register. Reconfigure the PLL. Set the CLOCKGENA.PLL1CR1 register to one of the supported
configurations on the datasheet. Restart the PLL, following the procedure described in the ST40 System Architecture Volume 1:
System. clockout() 2N×P×----------------- F clockin()×= M 2551 N 2550 P 5≤≤,≤≤,≤≤
1MHz F clockin()----------------------------- 2MHz≤≤
200MHz 2N×------------- F clockin()× 622MHz≤≤
6.4.4 Changing the frequency division ratio
The frequency division ratio is selected by changing the CPG.FRQCR register for PLL1 or the
CLOCKGENA.PLL2_MUXCR register for PLL2. This change is immediately effective.
6.5 Power management
The power management unit (PMU) is responsible for clock startup and shutdown for each of the
on-chip modules. Power is conserved by powering down those modules which are not in use, or
even the CPU itself.
The PMU is operated using three banks of registers as follows: CPG: controls the power-down mode of the CPU and the power-down states of the legacy
on-chip peripherals, CLOCKGENA and CLOCKGENB: control the power-down states of the other on-chip peripherals.
6.5.1 CPU low-power modes
The CPU can be put into sleep or standby modes. In sleep mode the CPU is halted while the
on-chip peripherals continue to operate. In standby mode all the on-chip peripherals are stopped
along with the CPU. In addition, the on-chip peripherals can be independently stopped.
Power down is initiated with the sleep instruction and the power down mode is selected with bit 7 of
the CPG.STBCR register. If the bit is set, the CPU enters standby mode on the next sleep
instruction, and if unset it enters sleep mode.
6.5.2 Module low-power modes
Modules are powered down in two ways, depending on whether the module is a ST40 legacy
peripheral (controlled by the CPG register bank) or a ST40RA peripheral (controlled by the
CLOCKGEN register banks).
A module controlled by the CPG register bank has its clock stopped when the corresponding bit in
the CPG.STBCR or CPG.STBCR2 register is set. The clock is started again when the bit is cleared.
To request the power down of a module controlled by the CLOCKGENA or CLOCKGENB register
bank, 1 is written to the corresponding bit in the STBREQCR_SET register. When the module has
completed its power down sequence and its clock has been stopped, the corresponding bit in the
STBACKCR register is set. To restart the module, 1 is written to the corresponding bit in the
STBREQCR_CLR register.
Note: The modules governed by the CLOCKGENB register bank do not support hardware-only power down
and require software interaction to maintain data coherency before making a request to stop the
module clock.
6.6 Clock generation registers
6.6.1 CLOCKGENB.CLK_SELCR register
6.6.2 CPG.STBCR register
6.6.3 CLOCKGENA.STBREQCR and CLOCKGENB.STBREQCR registers
6.6.4 CLOCKGENA.STBREQCR_SET and CLOCKGENB.STBREQCR_SET registers
6.6.5 CLOCKGENA.STBREQCR_CLR and CLOCKGENB.STBREQCR_CLR register
6.6.6 CLOCKGENA.STBACKCR and CLOCKGENB.STBACKCR register
Table 19 defines the mapping of modules to bits in the STBREQ and STBACK registers.
Table 19: STBREQ and STBACK mapping for modules
7 Electrical specifications
7.1 DC absolute maximum ratings
7.1.1 Fmax clock domains Stresses greater than those listed under Table 20: Absolute maximum ratings may cause
permanent damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the operating sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended period may effect
reliability. All I/O pins are 3.3 V tolerant except CLKIN, LPCLKIN, CLKOSC and LPCLKOSC.
Table 20: Absolute maximum ratings
Table 21: Fmax clock domains
7.1.2 Operating conditions Either the I/O ring (VDDIO) or the core (VDDCORE) may be powered up first. VDDCORE - VDDRTC When in SDRAM mode When in DDR-SDRAM mode For specified output loads see Table 24. 0 <= VI <= VDD
Table 22: Operating conditions
7.1.3 Pad specific output AC characteristics
Table 23: Power dissipation CPU 166 MHz (Mode 3) The SL pads are fully LVTTL and SSTL_2 compliant at maximum 35 pf load.
Table 24: I/O maximum capacitive and DC loading
Note: 1.The SL pad type graph represents the maximum drive strength in the LVTTL mode.
Figure 6: Pads characteristics
7.2 Rise and fall times
Figure 7: Timings for C2A, C2B, E4 and C4 pad types

Partno	Mfg	Dc	Qty	Available	Descript
ST40RA200XH6	ST	N/a	800	avai	32-bit Embedded SuperH Device