ST26C31BD ,CMOS QUAD TRI-STATE DIFFERENTIAL LINE DRIVERST26C31CMOS QUAD TRI-STATEDIFFERENTIAL LINE DRIVER■ TTL INPUT COMPATIBLE■ TYPICAL PROPAGATION DELAY ..
ST26C31BDR ,CMOS QUAD TRI-STATE DIFFERENTIAL LINE DRIVERPIN CONFIGURATIONPIN DESCRIPTIONPlN N° SYMBOL NAME AND FUNCTIONA INPUT A1INA Channel A Output2OUTA ..
ST26C31BN ,CMOS QUAD TRI-STATE DIFFERENTIAL LINE DRIVERABSOLUTE MAXIMUM RATINGS (Note 1, 2)Symbol Parameter Value UnitV Supply Voltage-0.5 to 7 VCCV DC In ..
ST26C31BTR ,CMOS QUAD TRI-STATE DIFFERENTIAL LINE DRIVERelectrical characteristics provide conditions for actual device operation.Note 2: Unless otherwise ..
ST26C32AB ,CMOS QUAD 3-STATE DIFFERENTIAL LINE RECEIVERST26C32ACMOS QUAD TRI-STATEDIFFERENTIAL LINE RECEIVER■ CMOS DESIGN FOR LOW POWER■ ±0.2V SENSITIVITY ..
ST26C32ABD ,CMOS QUAD 3-STATE DIFFERENTIAL LINE RECEIVERelectrical characteristics provide conditions for actual device operation.Note 2: Unless otherwise ..
STM1001SWX6F ,Reset CircuitFEATURES SUMMARY■ PRECISION MONITORING OF 3V, 3.3V, and Figure 2. Package5V SUPPLY VOLTAGES■ OPEN D ..
STM1001TWX6F ,Reset CircuitSTM1001Reset Circuit
STM1061N17WX6F ,Low power voltage detectorAbsolute Maximum Ratings 13Table 4. Operating and AC Measurement Conditions . . . 14Table ..
STM1061N19WX6F ,Low power voltage detectorBlock Diagram . . . 6Figure 6. STM1061N Active-Low, Open Drain Hardware Hookup . . . . 6Figur ..
STM1061N21WX6F ,Low power voltage detectorLogic Diagram . . . . 5Figure 3. SOT23-3 Connections . . . . . 5Figure 4. SOT323-3 (SC7 ..
STM1061N23WX6F ,Low power voltage detectorapplications and is available in space-saving SOT23-3 and SOT323-3 (SC70-3) packages.Figure 2.
ST26C31BD-ST26C31BDR-ST26C31BN-ST26C31BTR
CMOS QUAD TRI-STATE DIFFERENTIAL LINE DRIVER
1/10December 2002 TTL INPUT COMPATIBLE TYPICAL PROPAGATION DELAY: 6ns TYPICAL OUTPUT SKEW: 0.5ns OUTPUT WILL NOT LOAD LINE WHEN
VCC=0V MEETS THE REQUIREMENTS OF EIA
STANDARD RS-422 OPERATION FROM SINGLE 5V SUPPLY 3-STATE OUTPUTS FOR CONNECTION TO
SYSTEM BUSES LOW QUIESCENT CURRENT AVAILABLEIN SURFACE MOUNT
DESCRIPTIONTheST26C31is aquaddifferential linedriver
designed for digital data transmission over
balanced lines and meetsall the requirementsof
EIA standard RS-422 while retaining the low
power characteristicsof CMOS.
The ST26C31 accepts TTLor CMOS input levels
and translates theseto RS-422 output levels. This
part uses special outputs circuitry commontoall
four drivers. All outputs are protected against
damage dueto electrostatic dischargeby diodeto
VCC and ground.
ORDERING CODES
ST26C31CMOS QUAD TRI-STATE
DIFFERENTIAL LINE DRIVER
ST26C312/10
PIN CONFIGURATION
PIN DESCRIPTION
TRUTH TABLE= Low Voltage StateH= High Logic StateX= Don’t CareZ= High Impedance
ST26C313/10
ABSOLUTE MAXIMUM RATINGS (Note1,2)
Note1: Absolute Maximum Ratingsare those values beyond whichthe safetyofthe device cannotbe guaranteed. Theyarenot meanttoimplythatthe device shouldbe operatedat these limits. The tableof electrical characteristics provide conditionsfor actualdevice operation.
Note2: Unless otherwise specified,all voltageare referencedto ground.All currentsintothe device pinsare positive;all currentsoutofthedevice pinsare negative.
RECOMMENDED OPERATING CONDITIONS
ST26C314/10
ELECTRICAL CHARACTERISTICS(VCC =5V ± 10%, unless otherwise specified, See Note1)
Note1: Unlessotherwisespecified, min/max limits applyacrossthe recommended operating temperature range.All typical aregiven forVCC=5V andTa= 25°C
Note2: SeeEIA Specification RS422for exacttest conditions.Note3: Measuredperpin input.All other inputat VCCor GND.
Note4: Thisisthe current sourced whena high outputis shortedto ground. Only one outputat time shouldbe shorted.
SWITCHING CHARACTERISTICS (VCC =5V ± 10%,tr =tf≤ 6ns, See Note1)
Note1: Unless otherwise specified, min/max limits apply acrossthe recommended operating temperature range.All typicalare givenforVCC=5V andTa= 25°C
Note2: Skewis definedasthe differencein propagation delays between complementary outputsatthe 50% point.
Note3: Output disable timeisthe delay fromthe control input being switchedtothe output transistors tumingoff. The actual disable timesare less than indicated duetothe delay addedbyRC time constantofthe load.Note4: CPDdeterminestheno load dynamicpowerconsumption,PD =CPDV2 CCf= ICCVCC, andthe noload dynamic current consumption, =CPD VCCf+ICC
