ST24c01 Fast Delivery |IC PHOENIX CO.,LIMITED

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ST24c01
SERIAL 1K 128 x 8 EEPROM
ST24/25C01, ST24C01R
ST24/25W01
SERIAL 1K (128 x 8) EEPROM
NOT FOR NEW DESIGN
November 1997 1/16
Figure 1. Logic Diagram
1 MILLION ERASE/WRITE CYCLES with
40 YEARS DATA RETENTION
SINGLE SUPPLY VOLTAGE: 3V to 5.5V for ST24x01 versions 2.5V to 5.5V for ST25x01 versions 1.8V to 5.5V for ST24C01R version only
HARDWARE WRITE CONTROL VERSIONS:
ST24W01 and ST25W01
TWO WIRE SERIAL INTERFACE, FULLY I2C
BUS COMPATIBLE
BYTE and MULTIBYTE WRITE (up to 4
BYTES)
PAGE WRITE (up to 8 BYTES)
BYTE, RANDOM and SEQUENTIAL READ
MODES
SELF TIMED PROGRAMMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH UP
PERFORMANCES
ST24C/W01 are replaced by the M24C01
ST25C/W01 are replaced by the M24C01-W
ST24C01R is replaced by the M24C01-R
DESCRIPTION
This specification covers a range of 1K bits I2 C bus
EEPROM products, the ST24/25C01, the
ST24C01R and the ST24/25W01. In the text, prod-
ucts are referred to as ST24/25x01, where "x" is:
"C" for Standard version and "W" for hardware
Write Control version.
Table 1. Signal Names
Note: WC signal is only available for ST24/25W01 products.
The ST24/25x01 are 1K bit electrically erasable
programmable memories (EEPROM), organized
as 128 x 8 bits. They are manufactured in SGS-
THOMSON’s Hi-Endurance Advanced CMOS
technology which guarantees an endurance of one
million erase/write cycles with a data retention of
40 years. The memories operate with a power
supply value as low as 1.8V for the ST24C01R only.
Both Plastic Dual-in-Line and Plastic Small Outline
packages are available.
The memories are compatible with the I2 C stand-
ard, two wire serial interface which uses a bi-direc-
tional data bus and serial clock. The memories
carry a built-in 4 bit, unique device identification
code (1010) corresponding to the I2 C bus defini-
tion. This is used together with 3 chip enable inputs
(E2, E1, E0) so that up to 8 x 1K devices may be
attached to the I2 C bus and selected individually.
The memories behave as a slave device in the I2C
protocol with all memory operations synchronized
by the serial clock. Read and write operations are
initiated by a START condition generated by the
bus master. The START condition is followed by a
stream of 7 bits (identification code 1010), plus one
read/write bit and terminated by an acknowledge
bit.
Figure 2A. DIP Pin Connections
Figure 2B. SO Pin Connections
DESCRIPTION (cont’d)
Notes:1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other
relevant quality documents. MIL-STD-883C, 3015.7 (100pF, 1500 Ω). EIAJ IC-121 (Condition C) (200pF, 0 Ω).
Table 2. Absolute Maximum Ratings (1)
2/16
ST24/25C01, ST24C01R, ST24/25W01
Notes:1. X = VIH or VIL Multibyte Write not available in ST24/25W01 versions.
Table 4. Operating Modes (1)
Note: The MSB b7 is sent first.
Table 3. Device Select Code
When writing data to the memory it responds to the
8 bits received by asserting an acknowledge bit
during the 9th bit time. When data is read by the
bus master, it acknowledges the receipt of the data
bytes in the same way. Data transfers are termi-
nated with a STOP condition.
Power On Reset: VCC lock out write protect. In
order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is implemented. Until the VCC
voltage has reached the POR threshold value, the
internal reset is active, all operations are disabled
and the device will not respond to any command.
In the same way, when VCC drops down from the
operating voltage to below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable VCC
must be applied before applying any logic signal.
SIGNAL DESCRIPTIONS
Serial Clock (SCL). The SCL input pin is used to
synchronize all data in and out of the memory. A
resistor can be connected from the SCL line to VCC
to act as a pull up (see Figure 3).
Serial Data (SDA). The SDA pin is bi-directional
and is used to transfer data in or out of the memory.
It is an open drain output that may be wire-OR’ed
with other open drain or open collector signals on
the bus. A resistor must be connected from the SDA
bus line to VCC to act as pull up (see Figure 3).
Chip Enable (E0 - E2). These chip enable inputs
are used to set the 3 least significant bits (b3, b2,
b1) of the 7 bit device select code. These inputs
may be driven dynamically or tied to VCC or VSS to
establish the device select code.
Mode (MODE). The MODE input is available on pin
7 (see also WC feature) and may be driven dynami-
cally. It must be at VIL or VIH for the Byte Write
mode, VIH for Multibyte Write mode or VIL for Page
Write mode. When unconnected, the MODE input
is internally read as VIH (Multibyte Write mode).
Write Control (WC). An hardware Write Control
feature (WC) is offered only for ST24W01 and
ST25W01 versions on pin 7. This feature is usefull
to protect the contents of the memory from any
erroneous erase/write cycle. The Write Control sig-
nal is used to enable (WC = VIH) or disable (WC =
VIL) the internal write protection. When uncon-
nected, the WC input is internally read as VIL and
the memory area is not write protected.
3/16
ST24/25C01, ST24C01R, ST24/25W01
Figure 3. Maximum RL Value versus Bus Capacitance (CBUS) for an I2 C Bus
The devices with this Write Control feature no
longer support the Multibyte Write mode of opera-
tion, however all other write modes are fully sup-
ported.
Refer to the AN404 Application Note for more de-
tailed information about Write Control feature.
DEVICE OPERATION2 C Bus Background
The ST24/25x01 support the I2 C protocol. This
protocol defines any device that sends data onto
the bus as a transmitter and any device that reads
the data as a receiver. The device that controls the
data transfer is known as the master and the other
as the slave. The master will always initiate a data
transfer and will provide the serial clock for syn-
chronisation. The ST24/25x01 are always slave
devices in all communications.
Start Condition. START is identified by a high to
low transition of the SDA line while the clock SCL
is stable in the high state. A START condition must
precede any command for data transfer. Except
during a programming cycle, the ST24/25x01 con-
tinuously monitor the SDA and SCL signals for a
START condition and will not respond unless one
is given.
Stop Condition. STOP is identified by a low to high
transition of the SDA line while the clock SCL is
stable in the high state. A STOP condition termi-
nates communication between the ST24/25x01
and the bus master. A STOP condition at the end
of a Read command, after and only after a No
Acknowledge, forces the standby state. A STOP
condition at the end of a Write command triggers
the internal EEPROM write cycle.
Acknowledge Bit (ACK). An acknowledge signal
is used to indicate a successfull data transfer. The
bus transmitter, either master or slave, will release
the SDA bus after sending 8 bits of data. During the
9th clock pulse period the receiver pulls the SDA
bus low to acknowledge the receipt of the 8 bits of
data.
Data Input. During data input the ST24/25x01
sample the SDA bus signal on the rising edge of
the clock SCL. Note that for correct device opera-
tion the SDA signal must be stable during the clock
low to high transition and the data must change
ONLY when the SCL line is low.
Memory Addressing. To start communication be-
tween the bus master and the slave ST24/25x01,
the master must initiate a START condition. Follow-
ing this, the master sends onto the SDA bus line 8
bits (MSB first) corresponding to the device select
code (7 bits) and a READ or WRITE bit.
SIGNAL DESCRIPTION (cont’d)
4/16
ST24/25C01, ST24C01R, ST24/25W01
Note: 1. Sampled only, not 100% tested.
Table 5. Input Parameters (1) (TA = 25 °C, f = 100 kHz )
Table 6. DC Characteristics
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 3V to 5.5V, 2.5V to 5.5V or 1.8V to 5.5V)
5/16
ST24/25C01, ST24C01R, ST24/25W01
Notes:1. For a reSTART condition, or following a write cycle. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP
conditions. In the Multibyte Write mode only, if accessed bytes are on two consecutive 8 bytes rows (6 address MSB are not constant) the
maximum programming time is doubled to 20ms.
Table 7. AC Characteristics
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 3V to 5.5V, 2.5V to 5.5V or 1.8V to 5.5V)
The 4 most significant bits of the device select code
are the device type identifier, corresponding to the2 C bus definition. For these memories the 4 bits
are fixed as 1010b. The following 3 bits identify the
specific memory on the bus. They are matched to
the chip enable signals E2, E1, E0. Thus up to 8 x
1K memories can be connected on the same bus
giving a memory capacity total of 8K bits. After a
START condition any memory on the bus will iden-
tify the device code and compare the following 3
bits to its chip enable inputs E2, E1, E0.
The 8th bit sent is the read or write bit (RW), this
bit is set to ’1’ for read and ’0’ for write operations.
If a match is found, the corresponding memory will
acknowledge the identification on the SDA bus
during the 9th bit time.
DEVICE OPERATION (cont’d)
Input Rise and Fall Times ≤ 50ns
Input Pulse Voltages 0.2VCC to 0.8VCC
Input and Output Timing Ref. Voltages 0.3VCC to 0.7VCC
AC MEASUREMENT CONDITIONS
Figure 4. AC Testing Input Output Waveforms
6/16
ST24/25C01, ST24C01R, ST24/25W01
Figure 5. AC Waveforms
7/16
ST24/25C01, ST24C01R, ST24/25W01
Figure 6. I2 C Bus Protocol
Write Operations
The Multibyte Write mode (only available on the
ST24/25C01 and the ST24C01R versions) is se-
lected when the MODE pin is at VIH and the Page
Write mode when MODE pin is at VIL. The MODE
pin may be driven dynamically with CMOS input
levels.
Following a START condition the master sends a
device select code with the RW bit reset to ’0’. The
memory acknowledges this and waits for a byte
address. The byte address of 7 bits (the Most
Significant Bit is ignored) provides access to any of
the 128 bytes of the memory. After receipt of the
byte address the device again responds with an
acknowledge.
For the ST24/25W01 versions, any write command
with WC = 1 (during a period of time from the
START condition untill the end of the Byte Address)
will not modify data and will NOT be acknowledged
on data bytes, as in Figure 9.
Byte Write. In the Byte Write mode the master
sends one data byte, which is acknowledged by the
memory. The master then terminates the transfer
by generating a STOP condition. The Write mode
is independant of the state of the MODE pin which
could be left floating if only this mode was to be
used. However it is not a recommended operating
mode, as this pin has to be connected to either VIH
or VIL, to minimize the stand-by current.
8/16
ST24/25C01, ST24C01R, ST24/25W01

Partno	Mfg	Dc	Qty	Available	Descript
ST24c01	ST	N/a	10000	avai	SERIAL 1K 128 x 8 EEPROM
ST24C01		N/a	50	avai	SERIAL 1K 128 x 8 EEPROM