ST24W16M1TR-ST24W16M6TR Fast Delivery |IC PHOENIX CO.,LIMITED

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ST24W16M1TR-ST24W16M6TR
16 Kbit Serial I2C Bus EEPROM with User-Defined Block Write Protection
ST24C16, ST25C16
ST24W16, ST25W16
16 Kbit Serial I2 C Bus EEPROM
with User-Defined Block Write Protection
February 1999 1/17
Figure 1. Logic Diagram
1 MILLION ERASE/WRITE CYCLES, with
40 YEARS DATA RETENTION
SINGLE SUPPLY VOLTAGE: 4.5V to 5.5V for ST24x16 versions 2.5V to 5.5V for ST25x16 versions
HARDWARE WRITE CONTROL VERSIONS:
ST24W16 and ST25W16
TWO WIRE SERIAL INTERFACE, FULLY I2C
BUS COMPATIBLE
BYTE and MULTIBYTE WRITE (up to 8
BYTES) for the ST24C16
PAGE WRITE (up to 16 BYTES)
BYTE, RANDOM and SEQUENTIAL READ
MODES
SELF TIMED PROGRAMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH UP
PERFORMANCES
DESCRIPTION
This specification covers a range of 16 Kbit I2 C bus
EEPROM products, the ST24/25C16 and the
ST24/25W16. In the text, products are referred to
as ST24/25x16 where "x" is: "C" for Standard ver-
sion and "W" for hardware Write Control version.
The ST24/25x16 are 16 Kbit electrically erasable
programmable memories (EEPROM), organized
as 8 blocks of 256 x8 bits. These are manufactured
in STMicroelectronics’s Hi-Endurance Advanced
CMOS technology which guarantees an endur-
Table 1. Signal Names
Note: WC signal is only available for ST24/25W16 products.
Figure 2A. DIP Pin Connections
Figure 2B. SO8 Pin Connections
ance of one million erase/write cycles with a data
retention of 40 years. The ST25x16 operates with
a power supply value as low as 2.5V. Both Plastic
Dual-in-Line and Plastic Small Outline packages
are available.
The memories are compatible with the I2 C stand-
ard, two wire serial interface which uses a bi-direc-
tional data bus and serial clock. The memories
DESCRIPTION (cont’d) carry a built-in 4 bit, unique device identification
code (1010) corresponding to the I2 C bus defini-
tion. The memories behave as slave devices in the2 C protocol with all memory operations synchro-
nized by the serial clock. Read and write operations
are initiated by a START condition generated by the
bus master. The START condition is followed by a
stream of 4 bits (identification code 1010), 3 block
select bits, plus one read/write bit and terminated
by an acknowledge bit. When writing data to the
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and
other relevant quality documents. 100pF through 1500Ω; MIL-STD-883C, 3015.7 200pF through 0Ω; EIAJ IC-121 (condition C)
Table 2. Absolute Maximum Ratings (1)
2/17
ST24/25C16, ST24/25W16
Note: X = VIH or VIL.
Table 4. Operating Modes
Note: The MSB b7 is sent first.
Table 3. Device Select Code
memory it responds to the 8 bits received by as-
serting an acknowledge bit during the 9th bit time.
When data is read by the bus master, it acknow-
ledges the receipt of the data bytes in the same
way. Data transfers are terminated with a STOP
condition.
Data in the 4 upper blocks of the memory may be
write protected. The protected area is programma-
ble to start on any 16 byte boundary. The block in
which the protection starts is selected by the input
pins PB0, PB1. Protection is enabled by setting a
Protect Flag bit when the PRE input pin is driven
High.
Power On Reset: VCC lock out write protect. In
order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is implemented. Untill the VCC
voltage has reached the POR threshold value, the
internal reset is active: all operations are disabled
and the device will not respond to any command.
In the same way, when VCC drops down from the
operating voltage to below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable VCC
must be applied before applying any logic signal.
3/17
ST24/25C16, ST24/25W16
Figure 3. Maximum RL Value versus Bus Capacitance (CBUS) for an I2 C Bus
SIGNALS DESCRIPTION
Serial Clock (SCL). The SCL input signal is used
to synchronise all data in and out of the memory. A
resistor can be connected from the SCL line to VCC
to act as a pull up (see Figure 3).
Serial Data (SDA). The SDA signal is bi-directional
and is used to transfer data in or out of the memory.
It is an open drain output that may be wire-OR’ed
with other open drain or open collector signals on
the bus. A resistor must be connected from the SDA
bus line to VCC to act as pull up (see Figure 3).
Protected Block Select (PB0, PB1). PB0 and PB1
input signals select the block in the upper part of
the memory where write protection starts. These
inputs have a CMOS compatible input level.
Protect Enable (PRE). The PRE input signal, in
addition to the status of the Block Address Pointer
bit (b2, location 7FFh as in Figure 7), sets the PRE
write protection active.
Mode (MODE). The MODE input is available on pin
7 (see also WC feature) and may be driven dynami-
cally. It must be at VIL or VIH for the Byte Write
mode, VIH for Multibyte Write mode or VIL for Page
Write mode. When unconnected, the MODE input
is internally read as VIH (Multibyte Write mode).
Write Control (WC). An hardware Write Control
feature is offered only for ST24W16 and ST25W16
versions on pin 7. This feature is usefull to protect
the contents of the memory from any erroneous
erase/write cycle. The Write Control signal is used
to enable (WC at VIH) or disable (WC at VIL) the
internal write protection. When unconnected, the
WC input is internally read as VIL. The devices with
this Write Control feature no longer supports the
Multibyte Write mode of operation, however all
other write modes are fully supported.
Refer to the AN404 Application Note for more de-
tailed information about Write Control feature.
4/17
ST24/25C16, ST24/25W16
Note: 1. Sampled only, not 100% tested.
Table 5. Input Parameters (1) (TA = 25 °C, f = 100 kHz )
Table 6. DC Characteristics
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.5V to 5.5V or 2.5V to 5.5V)
5/17
ST24/25C16, ST24/25W16
Notes:1. For a reSTART condition, or following a write cycle. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP
conditions. In the Multibyte Write mode only, if accessed bytes are on two consecutive 8 bytes rows (5 address MSB are not constant) the maximum programming time is doubled to 20ms.
Table 7. AC Characteristics
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.5V to 5.5V or 2.5V to 5.5V)
DEVICE OPERATION2 C Bus Background
The ST24/25x16 support the I2 C protocol. This
protocol defines any device that sends data onto
the bus as a transmitter and any device that reads
the data as a receiver. The device that controls the
data transfer is known as the master and the other
as the slave. The master will always initiate a data
transfer and will provide the serial clock for syn-
chronisation. The ST24/25x16 are always slave
devices in all communications.
Start Condition. START is identified by a high to
low transition of the SDA line while the clock SCL
is stable in the high state. A START condition must
precede any command for data transfer. Except
during a programming cycle, the ST24/25x16 con-
tinuously monitor the SDA and SCL signals for a
START condition and will not respond unless one
is given.
Figure 4. AC Testing Input Output Waveforms
Table 8. AC Measurement Conditions
6/17
ST24/25C16, ST24/25W16
Figure 5. AC Waveforms
7/17
ST24/25C16, ST24/25W16
Stop Condition. STOP is identified by a low to high
transition of the SDA line while the clock SCL is
stable in the high state. A STOP condition termi-
nates communication between the ST24/25x16
and the bus master. A STOP condition at the end
of a Read command forces the standby state. A
STOP condition at the end of a Write command
triggers the internal EEPROM write cycle.
Acknowledge Bit (ACK). An acknowledge signal
is used to indicate a successful data transfer. The
bus transmitter, either master or slave, will release
the SDA bus after sending 8 bits of data. During the
9th clock pulse period the receiver pulls the SDA
bus low to acknowledge the receipt of the 8 bits of
data.
Figure 6. I2 C Bus Protocol
Data Input. During data input the ST24/25x16
samples the SDA bus signal on the rising edge of
the clock SCL. Note that for correct device opera-
tion the SDA signal must be stable during the clock
low to high transition and the data must change
ONLY when the SCL line is low.
Memory Addressing. To start communication be-
tween the bus master and the slave ST24/25x16,
the master must initiate a START condition. The 8
bits sent after a START condition are made up of a
device select of 4 bits that identifie the device type
(1010), 3 Block select bits and one bit for a READ
(RW = 1) or WRITE (RW = 0) operation.
There are three modes both for read and write.
They are summarised in T able 4 and described
hereafter. A communication between the master
and the slave is ended with a STOP condition.
8/17
ST24/25C16, ST24/25W16
Write Operations
The Multibyte Write mode (only available on the
ST24/25C16 versions) is selected when the MODE
pin is at VIH and the Page Write mode when MODE
pin is at VIL. The MODE pin may be driven dynami-
cally with CMOS input levels.
Following a START condition the master sends a
device select code with the RW bit reset to ’0’. The
memory acknowledges this and waits for a byte
address. The byte address of 8 bits provides ac-
cess to any of the 256 bytes of one memory block.
After receipt of the byte address the device again
responds with an acknowledge.
For the ST24/25W16 versions, any write command
with WC = ’1’ (during a period of time from the
START condition untill the end of the Byte Address)
will not modify data and will NOT be acknowledged
on data bytes, as in Figure 10.
Byte Write. In the Byte Write mode the master
sends one data byte, which is acknowledged by the
memory. The master then terminates the transfer
by generating a STOP condition. The Write mode
is independant of the state of the MODE pin which
could be left floating if only this mode was to be
used. However it is not a recommended operating
mode, as this pin has to be connected to either VIH
or VIL, to minimize the stand-by current.
Multibyte Write (ST24/25C16 only). For the Mul-
tibyte Write mode, the MODE pin must be at VIH.
The Multibyte Write mode can be started from any
address in the memory. The master sends from one
up to 8 bytes of data, which are each acknowledged
by the memory. The transfer is terminated by the
master generating a STOP condition. The duration
of the write cycle is tW = 10ms maximum except
when bytes are accessed on 2 contiguous rows
(one row is 16 bytes), the programming time is then
doubled to a maximum of 20ms. Writing more than
8 bytes in the Multibyte Write mode may modify
data bytes in an adjacent row (one row is 16 bytes
long). However, the Multibyte Write can properly
write up to 16 consecutive bytes only if the first
address of these 16 bytes is the first address of the
row, the 15 following bytes being written in the 15
following bytes of this same row.
Figure 7. Memory Protection
9/17
ST24/25C16, ST24/25W16

Partno	Mfg	Dc	Qty	Available	Descript
ST24W16M1TR	ST	N/a	735	avai	16 Kbit Serial I2C Bus EEPROM with User-Defined Block Write Protection
ST24W16M6TR	ST	N/a	980	avai	16 Kbit Serial I2C Bus EEPROM with User-Defined Block Write Protection