ST24FC21BM1TR Fast Delivery |IC PHOENIX CO.,LIMITED

ST24FC21BM1TR ,1 Kbit x8 Dual Mode Serial EEPROM for VESA PLUG & PLAYLogic DiagramENHANCED ESD/LATCH UPPERFORMANCESERROR RECOVERY MECHANISM(ST24FC21 and ST24FW21) VESA ..
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ST24FC21BM1TR
1 Kbit x8 Dual Mode Serial EEPROM for VESA PLUG & PLAY
ST24LC21B, ST24LW21
ST24FC21, ST24FC21B, ST24FW21
1 Kbit (x8) Dual Mode Serial EEPROM
for VESA PLUG & PLAY
June 2002 1/22
Figure 1. Logic Diagram
1 MILLION ERASE/WRITE CYCLES
40 YEARS DATA RETENTION
3.6V to 5.5V or 2.5V to 5.5V SINGLE SUPPLY
VOLTAGE
HARDWARE WRITE CONTROL (ST24LW21
and ST24FW21)
TTL SCHMITT-TRIGGER on VCLK INPUT
100k / 400k Hz COMPATIBILITY with the I2C
BUS BIT TRANSFER RANGE
TWO WIRE SERIAL INTERFACE I2 C BUS
COMPATIBLE 2 C PAGE WRITE (up to 8 Bytes)2 C BYTE, RANDOM and SEQUENTIAL READ
MODES
SELF TIMED PROGRAMMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH UP
PERFORMANCES
ERROR RECOVERY MECHANISM
(ST24FC21 and ST24FW21) VESA 2
COMPATIBLE
DESCRIPTION
The ST24LC21B, ST24LW21, ST24FC21,
ST24FC21B and ST24FW21 are 1K bit electrically
erasable programmable memory (EEPROM), or-
ganized in 128x8 bits. In the text, products are
referred as ST24xy21, where "x" is either "L" for
VESA 1 or "F" for VESA 2 compatible memories
and where "y" indicates the Write Control pin con-
nection: "C" means WC on pin 7 and "W" means
WC on pin 3.
Table 1. Signal Names
Note: WC signal is only available for ST24LW21 and ST24FW21
products.
Figure 2A. DIP Pin Connections
Figure 2B. SO Pin Connections
Warning: NC = Not Connected. Warning: NC = Not Connected.
Figure 2C. DIP Pin Connections
Figure 2D. SO Pin Connections
Warning: NC = Not Connected. DU = Don’t Use, must
be left open or connected to VCC or VSS.
Figure 2E. DIP Pin Connections
Figure 2F. SO Pin Connections
Warning: NC = Not Connected. Warning: NC = Not Connected.
Warning: NC = Not Connected. DU = Don’t Use, must
be left open or connected to VCC or VSS.
2/22
ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
Notes:1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not i mplied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents. MIL-STD-883C, 3015.7 (100pF, 1500 Ω). EIAJ IC-121 (Condition C) (200pF, 0 Ω).
Table 2. Absolute Maximum Ratings (1)
Note: The MSB b7 is sent first.
X = 0 or 1.
Table 3A. Device Select Code (ST24LC21B, ST24LW21, ST24FC21 and ST24FW21)
The ST24xy21 can operate in two modes: Trans-
mit-Only mode and I2 C bidirectional mode. When
powered, the device is in Transmit-Only mode with
EEPROM data clocked out from the rising edge of
the signal applied on VCLK.
The device will switch to the I2 C bidirectional mode
upon the falling edge of the signal applied on SCL
pin. When in I2 C mode, the ST24LC21B (or the
ST24LW21) cannot switch back to the Transmit
Only mode (except when the power supply is re-
moved). For the ST24FC21, ST24FC21B (or the
ST24FW21), after the falling edge of SCL, the
memory enter in a transition state which allowed to
switch back to the Transmit-Only mode if no valid2 C activity is observed. Both Plastic Dual-in-Line
and Plastic Small Outline packages are available.
Transmit Only Mode
After a Power-up, the ST24xy21 is in the Transmit
Only mode. A proper initialization sequence (see
Figure 3) must supply nine clock pulses on the
VCLK pin (in order to internally synchronize the
device). During this initialization sequence, the
SDA pin is in high impedance. On the rising edge
of the tenth pulse applied on VCLK pin, the device
will output the first bit of byte located at address 00h
(most significant bit first).
DESCRIPTION (cont’d)
Note: The MSB b7 is sent first.
X = 0 or 1.
Table 3B. Device Select Code (ST24FC21B)
3/22
ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
Figure 3. Transmit Only Mode Waveforms
Note: X = VIH or VIL
Table 4. I2 C Operating Modes
4/22
ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
A byte is clocked out (on SDA pin) with nine clock
pulses on VCLK: 8 clock pulses for the data byte
and one extra clock pulse for a Don’t Care bit.
As long as the SCL pin is held high, each byte of
the memory array is transmitted serially on the SDA
pin with an automatic address increment.
When the last byte is transmitted, the address
counter will roll-over to location 00h.2 C Bidirectional Mode
The ST24xy21 can be switched from Transmit Only
mode to I2 C Bidirectional mode by applying a valid
high to low transition on the SCL pin (see Figure 4). When the ST24LC21B (or the ST24FC21 or
the ST24FC21B) is in the I2 C Bidirectional
mode, the VCLK input (pin 7) enables (or inhib-
its) the execution of any write instruction: if
VCLK = 1, write instructions are executed; if
VCLK = 0, write instructions are not executed. When the ST24LW21 (or the ST24FW21) is in
the I2 C Bidirectional mode, the Write Control
(WC on pin 3) input enables (or inhibits) the
execution of any write instruction: if WC = 1,
write instructions are executed;if WC = 0,
write instructions are not executed.
The ST24xy21 is compatible with the I2 C standard,
two wire serial interface which uses a bidirectional
data bus and serial clock. The ST24xy21 carries a
built-in 4 bit, unique device identification code
(1010) named Device Select code corresponding
to the I2 C bus definition. The ST24LC21B carries a
unique device identification code (1010.0000 RW)
named Device Select code corresponding to the2 C bus definition.
The ST24xy21 behaves as a slave device in the2 C protocol with all memory operations synchro-
nized by the serial clock SCL. Read and write
operations are initiated by a START condition gen-
erated by the bus master. The START condition is
followed by a stream of 7 bits, plus one read/write
bit and terminated by an acknowledge bit.
When data is written into the memory, the
ST24xy21 responds to the 8 bits received by as-
serting an acknowledge bit during the 9th bit time.
When data is read by the bus master, it must
acknowledge the receipt of the data bytes in the
same way. Data transfers are terminated with a
STOP condition (see READ and WRITE descrip-
tions in the following pages).
Power On Reset: VCC lock out write protect
In order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is implemented. Until the VCC
voltage has reached the POR threshold value, the
internal reset is active, all operations are disabled
and the device will not respond to any command.
In the same way, when VCC drops down from the
operating voltage to below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable VCC
must be applied before applying any logic signal.
Error Recovery Modes available in the
ST24FC21, ST24FC21B and the ST24FW21
Figure 4. Transition from Transmit Only (DDC1) to Bi-directional (DDC2B) Mode Waveforms
5/22
ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
Figure 5. Error Recovery Mechanism Flowchart for the ST24FC21, ST24FC21B and ST24FW21
products
6/22
ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
Figure 6. Maximum RL Value versus Bus Capacitance (CBUS) for an I2 C Bus
When the ST24FC21 (or the ST24FC21B or the
ST24FW21) first switches to the I2 C mode (VESA
DDC2B mode), it enters a transition state which is
functionally identical to I2 C operation. But, if the
ST24FC21 (or the ST24FC21B or the ST24FW21)
does not receive a valid I2 C sequence, that is a
START condition followed by a valid Device Select
code (1010XXX RW f or ST24FC21 and
ST24FW21; 1010000 RW for ST24FC21B), within
either 128 VCLK periods or a period of time of
tRECOVERY (approximately 2 seconds), the
ST24FC21 (or the ST24FC21B or the ST24FW21)
will revert to the Transmit-Only mode (VESA DDC1
mode).
If the ST24FC21 (or the ST24FC21B or the
ST24FW21) decodes a valid I2 C Device Select
code, it will lock into I2 C mode. Under this condition,
signals applied on the VCLK input will not disturb
READ access from the ST24FC21 (or the
ST24FC21B or the ST24FW21). For WRITE ac-
cess, refer to the Signal Description paragraph.
When in the transition state, the count of VCLK
pulses and the internal 2 seconds timer are reset
by any activity on the SCL line. This means that,
after each high to low transition on SCL, the mem-
ory will re-initialise its transition state and will switch
back to Transmit-Only mode only after 128 more
VCLK pulses or after a new tRECOVERY delay.
SIGNAL DESCRIPTIONS2 C Serial Clock (SCL). The SCL input pin is used
to synchronize all data in and out of the memory. A
resistor can be connected from the SCL line to VCC
to act as a pull up (see Figure 6).
Serial Data (SDA). The SDA pin is bi-directional
and is used to transfer data in or out of the memory.
It is an open drain output that may be wire-OR’ed
with other open drain or open collector signals on
the bus. A resistor must be connected from the SDA
bus line to VCC to act as pull up (see Figure 6).
Transmit Only Clock (VCLK). The VCLK input pin
is used to synchronize data out when the ST24xy21
is in Transmit Only mode.
For the ST24LC21B and the ST24FC21 or
ST24FC21B Only, the VCLK offers also a Write
Enable (active high) function when the ST24LC21B
and the ST24FC21 or ST24FC21B are in I2 C bidi-
rectional mode.
Write Control (WC). An hardware Write Control
feature (WC) is offered only on ST24LW21 and
ST24FW21 on pin 3. This feature is usefull to
protect the contents of the memory from any erro-
neous erase/write cycle. The Write Control signal
is used to enable (WC = VIL) or disable (WC = VIH)
the internal write protection. When unconnected,
the WC input is internally tied to VSS by a 100k ohm
pull-down resistor and the memory is write pro-
tected.
DEVICE OPERATION
7/22
ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
Note: 1. Sampled only, not 100% tested.
Table 5. Input Parameters (1) (TA = 25 °C, f = 100 kHz )
Table 6A. DC Characteristics (ST24LC21B, ST24LW21, ST24FC21 and ST24FW21)
(TA = –40 to 85 °C; VCC = 3.6V to 5.5V)
8/22
ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
Note 1: Preliminary results.
Table 6B. DC Characteristics (ST24FC21B)
(TA = –40 to 85 °C; VCC = 2.5 to 5.5V)
9/22
ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
Notes:1. Sampled only, not 100% tested. For a reSTART condition, or following a write cycle.
Table 7. AC Characteristics, I2 C Bidirectional Mode for Clock Frequency = 400kHz
(TA = –40 to 85 °C; VCC = 3.6 to 5.5V or VCC = 2.5 to 5.5V)2 C Bus Background
The ST24xy21 supports the I2 C protocol. This pro-
tocol defines any device that sends data onto the
bus as a transmitter and any device that reads the
data as a receiver. The device that controls the data
transfer is known as the master and the other as
the slave. The master will always initiate a data
transfer and will provide the serial clock for syn-
chronisation. The ST24xy21 are always slave de-
vices in all communications.
Start Condition. START is identified by a high to
low transition of the SDA line while the clock SCL
is stable in the high state. A START condition must
precede any command for data transfer. Except
during a programming cycle, the ST24xy21 con-
tinuously monitor the SDA and SCL signals for a
START condition and will not respond unless one
is given.
The ST24LC21B, ST24LW21, ST24FC21 and
ST24FW21 are not executing a START condition if
this START condition happens at any time inside a
byte. The ST24FC21B executes a START condi-
tion when this START condition happens at any
time inside a byte.
Stop Condition. STOP is identified by a low to high
transition of the SDA line while the clock SCL is
stable in the high state. A STOP condition termi-
nates communication between the ST24xy21 and
the bus master. A STOP condition at the end of a
Read command (after the No ACK) forces the
standby state. A STOP condition at the end of a
Write command triggers the internal EEPROM
write cycle.
The ST24LC21B, ST24LW21, ST24FC21 and
ST24FW21 are not executing a STOP condition if
this STOP condition happens at any time inside a
byte. The ST24FC21B executes a STOP condition
when this STOP condition happens at any time
inside a byte.
Acknowledge Bit (ACK). An acknowledge signal
is used to indicate a successfull data transfer. The
bus transmitter, either master or slave, will release
the SDA bus after sending 8 bits of data. During the
9th clock pulse period the receiver pulls the SDA
bus low to acknowledge the receipt of the 8 bits of
data.
Data Input. During data input, the ST24xy21 sam-
ple the SDA bus signal on the rising edge of the
clock SCL. Note that for correct device operation
10/22
ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
Notes:1. For a reSTART condition, or following a write cycle. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP
conditions.
Table 8. AC Characteristics, I2 C Bidirectional Mode for Clock Frequency = 100kHz
(TA = –40 to 85 °C; VCC = 3.6V to 5.5V)
Notes:1. Refer to Figure 3. Sampled only, not 100% tested.
Table 9. AC Characteristics, Transmit-only Mode
(TA = –40 to 85 °C; VCC = 3.6V to 5.5V)
11/22
ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21

Partno	Mfg	Dc	Qty	Available	Descript
ST24FC21BM1TR	ST	N/a	680000	avai	1 Kbit x8 Dual Mode Serial EEPROM for VESA PLUG & PLAY