ST20GP6CX33S ,GPS PROCESSORAPPLICATIONS■ Technology■ Global Positioning System (GPS) receivers• Static clocked 50 MHz design■ ..
ST2189QTR ,8-bit dual supply level translator without direction control pinApplicationswhich provides the level shifting capability to allow data transfer in a multi-voltage ..
ST21S07ACW ,SCSI TERMINATORPIN CONFIGURATION SO-16L TSSOP20 PIN DESCRIPTION PlN N° PlN N° SYMBOL NA ..
ST2221C , 16 BIT CONSTANT CURRENT LED DRIVERS
ST2226A , PWM-Controlled Constant Current Driver for LED Displays
ST230C ,PHASE CONTROL THYRISTORS Hockey Puk VersionApplicationsDC motor controlsControlled DC power suppliesAC controllerscase style TO-200AB (A-PUK)M ..
STK800 , N-channel 30V - 0.006Ω - 20A - PolarPAK-R STripFET-TM Power MOSFET
STK8250 ,50W MIN AF POWER AMP
STK8260 , OUTPUT STAGE OF AF POWER AMP
STK8270 , OUTPUT STAGE OF AF POWER AMP
STK8280 , 80W MIN AF POWER AMP, OUTPUT STAGE (DUAL SUPPLIES) WITH BUILT-IN QUASI CLASS A BIAS CIRCUIT
STK830F , Advanced Power MOSFET
ST20GP6CX33S
GPS PROCESSOR
GPS PROCESSOR
ST20-GP6
FEATURES Application specific features12 channel GPS correlation DSP hardware,
ST20 CPU (for control and position
calculations) and memory on one chipno TCXO requiredRTCA-SC159 / WAAS / EGNOS supported GPS performanceaccuracy- stand alone with SA on <100m, SA off <30m- differential <1m- surveying <1cmtime to first fix- autonomous start 90s- cold start 45s- warm start 7s- obscuration 1s Enhanced 32-bit VL-RISC CPU - C2 core16/33/50 MHz processor clock25 MIPS at 33 MHzfast integer/bit operations 64 Kbytes on-chip SRAM 128 Kbytes on-chip ROM Programmable memory interface4 separately configurable regions8/16-bits widesupport for mixed memory2 cycle external access Programmable UART (ASC) Parallel I/O Vectored interrupt subsystem Diagnostic control unit Power managementlow power operationpower down modes Professional toolset supportANSI C compiler/link driver and librariesDebugging/profiling and simulation tools TechnologyStatic clocked 50 MHz design3.3 V, sub micron technology 100 pin PQFP package JTAG Test Access Port
APPLICATIONSGlobal Positioning System (GPS) receiversCar navigation systemsFleet management systemsTime reference for telecom systems
ST20GP6X33S PQFP100
Contents
ST20-GP6Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ST20-GP6 architecture overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Digital signal processing module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.1 DSP module registers........................................................................................................ ...................13
Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194.1 Registers................................................................................................................... ............................19
4.2 Processes and concurrency................................................................................................... ..............20
4.3 Priority.................................................................................................................... ...............................22
4.4 Process communications...................................................................................................... ................23
4.5 Timers...................................................................................................................... .............................23
4.6 Traps and exceptions........................................................................................................ ...................24
Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305.1 Interrupt vector table...................................................................................................... .......................31
5.2 Interrupt handlers.......................................................................................................... ........................31
5.3 Interrupt latency........................................................................................................... .........................32
5.4 Preemption and interrupt priority........................................................................................... ...............32
5.5 Restrictions on interrupt handlers.......................................................................................... ...............33
5.6 Interrupt configuration registers........................................................................................... .................33
Interrupt level controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376.1 Interrupt assignments....................................................................................................... ....................37
6.2 Interrupt level controller registers........................................................................................ .................37
Instruction set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407.1 Instruction cycles.......................................................................................................... ........................40
7.2 Instruction characteristics................................................................................................. ....................41
7.3 Instruction set tables...................................................................................................... .......................42
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518.1 System memory use........................................................................................................... ..................51
8.2 Boot ROM.................................................................................................................... .........................52
8.3 Internal peripheral space................................................................................................... ...................52
Memory subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559.1 SRAM........................................................................................................................ ...........................55
9.2 ROM......................................................................................................................... ............................55
ST20-GP6Programmable memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5610.1 EMI signal descriptions.................................................................................................... .....................58
10.2 External accesses.......................................................................................................... .......................59
10.3 MemWait.................................................................................................................... ...........................60
10.4 EMI configuration registers................................................................................................ ...................62
10.5 Boot source................................................................................................................ ...........................65
10.6 Default configuration...................................................................................................... .......................65
Low power controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6611.1 Low power control.......................................................................................................... .......................66
11.2 Low power configuration registers.......................................................................................... ..............67
Real time clock and watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7012.1 Power supplies............................................................................................................. ........................70
12.2 Real time clock............................................................................................................ .........................70
12.3 Watchdog timer............................................................................................................. ........................70
12.4 RTC/WDT configuration registers............................................................................................ .............71
System services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7313.1 Reset, initialization and debug............................................................................................ ..................73
13.2 Bootstrap.................................................................................................................. ............................73
13.3 Clocks..................................................................................................................... ..............................73
Diagnostic controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7514.1 Diagnostic hardware........................................................................................................ .....................75
14.2 Access features............................................................................................................ ........................76
14.3 Software debugging features................................................................................................ ................77
14.4 Controlling the diagnostic controller...................................................................................... ................79
14.5 Peeking and poking the host from the target................................................................................ ........80
14.6 Abortable instructions..................................................................................................... ......................80
UART interface (ASC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 215.1 Functionality.............................................................................................................. ............................82
15.2 Timeout mechanism.......................................................................................................... ...................85
15.3 Baud rate generation....................................................................................................... .....................85
15.4 Interrupt control.......................................................................................................... ..........................86
15.5 ASC configuration registers................................................................................................ ..................88
Parallel input/output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9416.1 PIO Ports0-1............................................................................................................... ..........................94
Configuration register addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
ST20-GP6Electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102GPS Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
19.1 Accuracy................................................................................................................... ............................106
19.2 Time to first fix.......................................................................................................... ............................107Timing specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
20.1 EMI timings................................................................................................................ ...........................108
20.2 Reset timings.............................................................................................................. ..........................110
20.3 PIO timings................................................................................................................ ...........................111
20.4 ClockIn timings............................................................................................................ .........................112
20.5 JTAG IEEE 1149.1 timings................................................................................................... ................113Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114Package specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6
22.1 ST20-GP6 package pinout.................................................................................................... ...............116
22.2 100 pin PQFP package dimensions............................................................................................ .........119
Test access port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
ST20-GP6 Introduction
TheST20-GP6isanapplication-specificsinglechipmicrousingtheST20CPUwithmicroprocessorstyleperipheralsaddedon-chip.ItincorporatesDSPhardwareforprocessingthesignals from GPS (Global Positioning System) satellites.
ThetwelvechannelGPScorrelationDSPhardwareisdesignedtohandletwelvesatellites,twoofwhichcanbeinitializedtosupporttheRTCA-SC159specificationforWAAS(WideAreaAugmentationService)andEGNOS(EuropeanGeostationaryNavigationOverlaySystem)services.
TheST20-GP6hasbeendesignedtominimizesystemcostsandreducethecomplexityofGPS
systems.ItoffersallhardwareDSPandmicroprocessorfunctionsononechipandprovidessufficienton-chipRAMandROM.Theentireanaloguesection,RFandclockgenerationareavailableonacompanionchip.Thus,acompleteGPSsystemispossibleusingjusttwochips,seeFigure1.1.
Figure 1.1 GPS system
TheST20-GP6supportslargevaluesoffrequencyoffset,allowingtheuseofaverylowcostoscillator, thus saving the cost of a Temperature Controlled Crystal Oscillator (TCXO).
TheCPUandsoftwarehaveaccesstothepart-processedsignaltoenableacceleratedacquisitiontime.
ST20-GP6
TheST20-GP6canimplementtheGPSdigitalsignalprocessingalgorithmsusinglessthan50%oftheavailableCPUprocessingpower.ThisleavestherestavailableforintegratingOEMapplicationfunctionssuchasroute-finding,mapdisplayandtelemetry.AhardwaremicrokernelintheST20CPUsupportsthesharingofCPUtimebetweentaskswithoutanoperatingsystemorexecutiveoverhead.
ThearchitectureisbasedontheST20CPUcoreandsupportingmacrocellsdevelopedbySTMicroelectronics.TheST20micro-corefamilyprovidesthetoolsandbuildingblockstoenablethedevelopmentofhighlyintegratedapplicationspecific32-bitdevicesatthelowestcostand
fastesttimetomarket.TheST20macrocelllibraryincludestheST20Cxfamilyof32-bitVL-RISC(variablelengthreducedinstructionsetcomputer)micro-cores,embeddedmemories,standardperipherals, I/O, controllers and ASICs.
TheST20-GP6usestheST20macrocelllibrarytoprovidethehardwaremodulesrequiredinaGPS system. These include: DSP hardware Dual channel UART for serial communicationsTwo parallel I/O modules providing 16 bits of parallel I/O Interrupt controller Real time clock/calendar and watchdog timer 128 Kbytes of on-chip ROM for application code 64 Kbytes of on-chip RAM, of which 16 Kbytes is battery backed Diagnostic control unit and test access port for development support
TheST20-GP6issupportedbyarangeofsoftwareandhardwaredevelopmenttoolsforPCandUNIXhostsincludinganANSI-CST20softwaretoolsetandtheST20INQUESTwindowbaseddebugging toolkit.
ST20-GP6 ST20-GP6 architecture overview
TheST20-GP6consistsofanST20CPUplusapplicationspecificDSPhardwareforhandlingGPSsignals,plusadualchannelUART,ROMandRAMmemory,parallelIO,realtimeclockandwatchdog functions.
Figure2.1showsthesubsystemmodulesthatcomprisetheST20-GP6.Thesemodulesareoutlined below and more detailed information is given in the following chapters.
DSP
TheST20-GP6includesDSPhardwareforprocessingsignalsfromtheGPSsatellites.TheDSPmodule generates the pseudo-random noise (prn) signals, and de-spreads the incoming signal.consistsofadownconversionstagethattakesthe4MHzinputsignaldowntonominallyzerofrequencybothin-phaseandquadrature(I&Q).Thisisfollowedby12parallelhardwarechannelsforsatellitetracking,whoseoutputispassedtotheCPUforfurthersoftwareprocessingataprogrammable interval, nominally every millisecond.
CPU
TheCentralProcessingUnit(CPU)ontheST20-GP6istheST2032-bitprocessorcore.Itcontainsinstructionprocessinglogic,instructionanddatapointers,andanoperandregister.Itdirectlyaccessesthehighspeedon-chipmemory,whichcanstoredataorprograms.Theprocessorcanaccess up to 4 Mbytes of memory via the programmable memory interface.
ST20-GP6
Figure 2.1 ST20-GP6 architectural block diagram
Memory subsystem
TheST20-GP6on-chipmemorysystemprovides60Mbytes/sinternaldatabandwidth,supportingpipelined2-cycleinternalmemoryaccessat30nscycletimes.TheST20-GP6memorysystemconsists of SRAM, ROM and a programmable external memory interface (EMI).
ST20-GP6
TheST20-GP6canuse8or16-bitexternalRAM,8or16-bitexternalROM,andhasa20-bitaddress bus.
TheST20-GP6producthas64Kbytesofon-chipSRAM.Thisisin4banksof16Kbytes.Oneofthesebanksispoweredfromtheback-upbatterysupply.TheST20-GP6has128KbytesofROMfor application code.
TheST20-GP6memoryinterfacecontrolsthemovementofdatabetweentheST20-GP6andoff-chipmemory.Itisdesignedtosupportmemorysubsystemswithoutanyexternalsupportlogicandisprogrammabletosupportawiderangeofmemorytypes.Memoryisdividedinto4bankswhich
caneachhavedifferentmemorycharacteristicsandeachbankcanaccessupto1Mbyteofexternal memory.
ThenormalmemoryprovisioninasimpleGPSreceiverisasingle64Kx16-bitROMorFlashROM(70,90or100nsaccesstime).Theinternal64KbyteRAMissufficientforapplicationuse,howeverfordevelopmentpurposesexternalRAMmaybeadded.TheST20-GP6cansupportupto1 Mbyte of SRAM plus 1 Mbyte of ROM, enabling additional functions to be added if required.
Low power controller, real time clock and watchdog timer
TheST20-GP6haspower-downcapabilitiesconfigurableinsoftware.Whenpowereddown,atimercanbeusedasanalarm,re-activatingtheCPUafteraprogrammeddelay.Thisissuitableforultralowpowerorsolarpoweredapplicationssuchascontainertracking,railwaytrucktracking,ormarine navigation buoys that must check they are on station at intervals.
Thereisalsoawatchdogtimer(WDT),resettingthesystemifittimesout.Thewatchdogtimerfunctionisenabledbyanexternalpin( WdEnable ).TheWDThasacounter,clockedtogiveanominal2seconddelay.Astatusflag( notWdReset )issetbyawatchdogreset.Thiscanbeusedto indicate to application code that the system was reset by the watchdog timer.
Therealtimeclock(RTC)providesasetofcontinuouslyrunningcounterstoprovideaclock-calendarfunction.Thecountervaluescanbewrittentosetthecurrenttime/data.TheRTCisclockedbya32,768Hzcrystaloscillatorandhasaseparatepowersupplysothatitcancontinuetorun when the rest of the chip is powered down.
TheRTCcontainstwocounters:a30-bit‘milliseconds’counteranda16-bit‘weeks’counter.Thisallowslargetimevaluestoberepresentedtohighaccuracy.Notethatthemillisecondscounterisactually clocked at 1.024KHz and this must be handled by software.
TheST20-GP6isdesignedfor0.35micron,3.3VCMOStechnologyandrunsatspeedsofupto50MHz.3.3Voperationprovidesreducedpowerconsumptioninternallyandallowstheuseoflowpower peripherals. In addition, a power-down mode is available on the ST20-GP6.
The different power levels of the ST20-GP6 are listed below. Operating power — power consumed during functional operation. Stand-bypower—powerconsumedduringlittleornoactivity.TheCPUisidlebutreadytoimmediately respond to an interrupt/reschedule.Power-down—clocksarestoppedandpowerconsumptionissignificantlyreduced.Func-tionaloperationisstalled.Normalfunctionaloperationcanberesumedfrompreviousstateassoonastheclocksarestable.Noinformationislostduringpowerdownasallinternallogic is static.
ST20-GP6Power to most of the chip removed — only the real time clock supply ( RTCVDD ) power on.power-downmodetheprocessorandallperipheralsarestopped,includingtheexternalmemorycontrollerandoptionallythePLL.Effectivelytheinternalclockisstoppedandfunctionaloperationis stalled. On restart the clock is restarted and the chip resumes normal functional operation.
Serial communications
TheST20-GP6hastwoUARTs(AsynchronousSerialControllers(ASCs))forserialcommunication.TheUARTsprovideanasynchronousserialinterfaceandcanbeprogrammedtosupport a range of baud rates and data formats, for example, data size, stop bits and parity.
Interrupt subsystem
TheST20-GP6interruptsubsystemsupportseightprioritizedinterrupts.Fourinterruptsareconnectedtoon-chipperipherals(2fortheUARTs,2fortheprogrammableIO),twoareavailableas external interrupt pins and two are spare.
Eachinterruptlevelhasahigherprioritythanthepreviousandeachlevelsupportsonlyonesoftware handler process.
NotethatinterrupthandlersmustnotpreventtheGPSDSPdatatrafficfrombeinghandled.Duringcontinuousoperationthishas1mslatencyandisnotaproblem,butduringinitialacquisitionithasa 32 μs rate and thus all interrupts must be disabled except if used to stop GPS operation.
Parallel IO module
SixteenbitsofparallelIOareprovided.Eachbitisprogrammableasanoutputoraninput.Edgedetection logic is provided which can generate an interrupt on any change of an input bit.
JTAG Test Access Port
The Test Access Port (TAP) supports the IEEE 1149.1 JTAG test standard.
Diagnostic controller
ThediagnosticcontrollerisaprogrammablemodulewhichconnectsdirectlyintotheCPU.ItcanbeaccessedbytheTAP.ThisallowsdebuggingsystemstobeusedwhichdonotaffectCPUperformance or intrude into application code. Debugging support includes: hardware breakpoint and watchpoint real time trace external LSA triggering support
It is also used to provide system services, including booting the CPU.
System services module
The ST20-GP6 system services module includes: reset and initialization port. phaselockedloop(PLL)—accepts16.368MHzinputandgeneratesalltheinternalhighfrequency clocks needed for the CPU.
ST20-GP6 Digital signal processing module
TheST20-GP6chipincludes12channelGPScorrelationDSPhardware.Itisdesignedtohandletwelve satellites, two of which can be initialized to support the RTCA-SC159 specification.
Thedigitalsignalprocessing(DSP)moduleextractsGPSdatafromtheincomingIF(IntermediateFrequency)data.Thereareanumberofstagesofprocessinginvolved;thesearesummarizedbelowandinFigure3.1.Afterthe12pairsofhardwarecorrelators,thedataforallchannelsaretimedivisionmultiplexedontotheappropriateinternalbuses(i.e.valuesforeachchannelarepassed in sequence, for example: I 1, Q 1, I2, Q 2 ... I 12, Q 12, I1, Q 1).
Figure3.1 DSP module block diagram
The main stages of processing are as follows:
Data sampling
Thisstageremovesanymeta-stabilitycausedbytheasynchronousinputdatacomingfromananaloguesource(theradioreceiver).Thedataatthispointconsistsofacarrierofnominally4.092MHz with a bandwidth of approximately ±1MHz.
This stage is common to all 12 channels.
ST20-GP6
Frequency conversion (A)
ThefirstfrequencyconvertermixesthesampledIFdatawiththe(nominal)4.092MHzsignal.ThisisdonetwicewithaquartercycleoffsettoproduceIandQ(In-phaseandQuadrature)versionsofthedataatnominalzerocentrefrequency(thiscanactuallybeupto ±132KHzduetoerrorssuchasdopplershift,crystalaccuracy,etc.).Thesumfrequency(~8MHz)isremovedbylow-passfilter-ing in the correlator.
This stage is common to all 12 channels.
Correlation against pseudo-random sequence
TheGPSdataistransmittedasaspread-spectrumsignal(withabandwidthofabout2MHz).InordertorecoverthedataitisnecessarytocorrelateagainstthesamePseudo-RandomNoise(PRN)signalthatwasusedtotransmitthedata.Theoutputofthecorrelatoraccumulatorissam-pled at 264KHz. The PRN sequences come from the PRN generator.
ThereisacorrelatorfortheIandQsignalsforeachofthe12channels.Theoutputsignalisnownarrowband.
Frequency conversion (B)
ThesecondstageoffrequencyconversionmixesthedatawiththelocaloscillatorsignalgeneratedbytheNumericallyControlledOscillator(NCO).Thissignalislocked,undersoftwarecontrol,totheSpaceVehicle(SV)frequencyandphasetoremovetheerrorsandtakethefrequencyandband-widthofthedatadownto0and ±50Hzrespectively.Filteringto500Hzisachievedinhardware,to50 Hz in software.
Thisstageissharedbytimedivisionmultiplexingbetweenall12channels.Thisisloss-freeasthestage supports 12 channels x 264 KHz, approximately 3 MHz, well within its 16 MHz clock rate.
Result integration
ThefinalstagesumstheIandQvaluesforeachchanneloverauserdefinedperiod.Innormaloperation,thesamplingperiodisslightlylessthanthe1mslengthofthePRNsequence.Thisensuresthatnodataislost,althoughitmaymeanthatsomedatasamplesareseentwice—thisishandled (mainly) in software.
Thesamplingperiodcanalsobeprogrammedtobemuchshorter(i.e.ahighercut-offfrequencyfor the filter) when the system is trying to find new satellites (‘acquisition mode’).
Therearetwofurtherstagesofbufferingfortheaccumulated16-bitIandQvaluesforeachchan-nel. These allow for the slightly different time domains involved 1.
Theresultsafterhardwareprocessingofthesignal,usingtheparameterssetintheDSPregisters,refertoSection3.1,aredeliveredtotheCPUviaaDMAengineinpacketformat.TheCPUshouldperforman in (input)instructionontheappropriatechannel(seeaddressmap,Figure8.1onpage53) in order to read a packet.
Theformatofthe62-bytepacketsisgiveninFigure3.2.Theserepresentatwobyteheader,fol-lowedbythe16-bitI-valuesfor12channels,thenthe16-bitQ-valuesfor12channels,thenthe8-bittimestampvaluesforthe12channels.TheIandQvaluesaresentleastsignificantbytefirst.The2Data sampled in SV time, data transmitted to the CPU at fixed intervals.
ST20-GP6
byteheadercontains:a‘sync’bytewiththevalue#1B,anda‘samplerate’bytewhichcontainsthetwo SampleRate bits from the DSPControl register, see Table3.1.
Packetsaredeliveredattherateselectedbythe DSPControl register,evenifnewdataisnotavail-able.Inthiscase,thedatavalueforthefieldissetto#8000.Thisguaranteesthatsynchronismismaintainedbetweenthesatelliteone-millisecondepochsandthereceiver,despitetime-of-recep-tion variations due to the varying path length from the satellite.
Figure3.2 DSP packet format
3.1 DSP module registers
The GPS hardware channels of the ST20-GP6 are controlled by three sets of registers: DSPControl register PRNcode0-11 and PRNphase0-11 registers NCOfrequency0-11 and NCOphase0-11 registers
The base addresses for the DSP registers are given in the Memory Map chapter.
DSPControl register
The DSPControl registerdetermineswhetherthePRNgeneratorsareon(normaluse)ordisabled(forbuilt-in-self-testofasystem),whetherthesystemisintrackingmode(840/970 μsoutputrate)orinitialacquisitionmode(31/62 μs),andselectswhichofthetworatesforeachmode.Italso
ST20-GP6
determineswhethertheaccumulatedcarrierphaseintheNCOareresettozeroautomaticallyorcontinue from their existing value. The bit allocations are given in Table3.1.
PRNcode0-11 registers
The PRNcode0-11 registerschoosethecodefortheparticularsatellite,andwritingthesecausesaresettotheaccumulatedcarrierphaseintheNCOforthecorrespondingchannel,ifenabledbytheDSPControl register.
The bit-fields for selecting particular GPS satellites are given in Table3.3.able3.1 DSPControl register formatable3.2 PRNcode0-11 register format
ST20-GP6
Forchannels0and1,RTCA-SC159satellitecodescanalsobeselected.Thisisachievedbyset-tingthe PRNcode0-11 registerappropriatelyandalsowritingtheinitialvalueforthesatellitetothe
Table3.3 PRNcode0-11 register valueRefer to the US DoD document ICD-GPS-200.It is the responsibility of the software to ensure that when this value is selected, a suitable
valuehasbeenwrittenintothe PRNinitialVal0-1 register.Ifthischannelislaterusedfora
standard GPS satellite, the PRNinitialVal0-1 must be set to all ones (#3FF).
ST20-GP6
PRNinitialVal0-1 register,seeTable3.8.Ifuninitializedbythesoftware,the PRNinitialVal registerdefaults to 11 1111 1111 (#3FF) as required for GPS satellites.
The PRNcode0-11 and PRNinitialVal0-1 registersarenormallywrittenonlywhenthesatelliteisfirst chosen.
PRNphase0-11 registers
The PRN0-11phase registersdeterminetherelativedelaybetweenthereceivermasterclock,andthestartoftheonemillisecondrepetitivecodesequence.Thecodesequencestartswhenthereceiverclockcounter(invisibletothesoftwareexceptthroughmessagetimestamps)reachesthe
valuewrittentothe PRNphase0-11 register.The PRNphase0-11 registermustonlybewrittenoncepersatellitemilliseconds-epoch,whichvariesfromthereceiverepochdynamicallyduetosat-ellitemotion.Synchronismwiththesoftwareisachievedbyreadingtheregister,whenawriteenable flag is returned. If not enabled, the write operation is abandoned by the software.
The19-bitvaluecomprisesthreefields.The3leastsignificantbitsrepresentthefractional-delayineighthsofacode-chip.Themiddle10bitsrepresenttheintegerdelayincode-chips,0-1022,withthevalue1023illegal.Theupper6mostsignificantbitsrepresentthedelayinintegermilliseconds.
Notealsothattheeighth-chipresolutionofthecodegeneratorisnotsufficientforpositioning.At125nsitrepresentsapproximately40mofrange,over100mofposition.Thesoftwaremustmain-taintherangemeasurementsaroundthe1nsresolutionlevelina32-bitfield,andsendanappro-priate19-bitsub-fieldtotheregister.Note,caremustbetakenwhencalculatingthisfieldfromacomputeddelay,orviceversa,toallowforthemissingvalue1023.Theoverallregisterbit-fieldcan-not be used mathematically as a single binary number.
PRNphase0-11WrEn registers
The PRNphase0-11WrEn flagsareactivelowflagsthatrecordwhenthe PRNphase0-11 registercanbeupdated.The PRNphaseWrEn flagforachannelissethighwhenthecorresponding PRN-phase registeriswritten.TheflagisresetagainwhenthevaluewrittenisloadedintothePRNgen-
Table3.4 PRNphase0-11 register format
ST20-GP6
erator.Note,the PRNphase0-11 registershouldonlybeupdatedwhenthe PRNphase0-11WrEnregister has been cleared by the hardware.
NCOfrequency0-11 registers
The NCOfrequency0-11 registersholdasigned18-bitvaluethatisaddedrepetitively,ignoringoverflows,totheaccumulatedNCOphasefromwhichtheNCOsineandcosinewaveformsaregenerated.Theadditionisperformedata264KHzrate(16.368MHz/62).TheaccumulatedNCOphaseisnotaccessibletothesoftware,butcanbeclearedwheninitialisingthechannelifenabledby the DSPControl register.
Eachunitvalueinthe NCOfrequency0-11 registerrepresents264KHz/(2 18),i.e.1.007080078125Hz.theextremevaluesarewritten,#1FFFFand#20000,thesinewavegeneratedwillbeatapproxi-mately +132 KHz, and precisely -132 KHz respectively.
NCOphase0-11 registers
The NCOphase0-11 registerscontentsareaddedtotheaccumulatedphasetocorrectthecarrierforthefinal1HzthatcannotberesolvedbytheNCOfrequency.Thisadditionisnotcumulative,andthevaluemustbeupdatedregularlybythesoftwareasaresultofcarrierphaseerrorsmea-suredonthesatellitesignal.Theregisterholdsasigned7-bitfieldrepresenting+/-180degreestotal in steps of 2.8125 degrees (360/128).able3.5 PRNphase0-11WrEn register format
Table3.6 NCOfrequency0-11 register formatable3.7 NCOphase0-11 register format
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PRNinitialVal0-1 registers
TheinitialvalueforthetwoRTCA-SC159capablesatelliteschannelsshouldbewrittentothePRNinitialVal0-1 registers. The value can be found in the RTCA-SC159 Specification .
Note :ThevaluewrittentotheregisteristheInitialValuedefinedbyRTCA-SC159forthePRNrequired.Theconversionfrom‘big-endian’asusedinthespecificationto‘little-endian’asconven-tionally used in ST20 architectures has been implemented in the hardware.uninitializedbythesoftware,thisregisterdefaultsto1111111111(#3FF)asrequiredforGPSsatellites.able3.8 PRNinitialVal0-1 register format
ST20-GP6 Central processing unit
TheCentralProcessingUnit(CPU)istheST2032-bitprocessorcore.Itcontainsinstructionpro-cessinglogic,instructionanddatapointers,andanoperandregister.Itcandirectlyaccessthehighspeedon-chipmemory,whichcanstoredataorprograms.Wherelargeramountsofmemoryarerequired, the processor can access memory via the External Memory Interface (EMI).
The processor provides high performance: Fast integer multiply - 4 cycle multiply Fast bit shift - single cycle barrel shifter Byte and part-word handling Scheduling and interrupt support 64-bit integer arithmetic support.
Theschedulerprovidesasinglelevelofpre-emption.Inaddition,multi-levelpre-emptionispro-videdbytheinterruptsubsystem,seeChapter5fordetails.Additionally,thereisaper-prioritytraphandler to improve the support for arithmetic errors and illegal instructions, refer to section 4.6.
4.1 Registers
TheCPUcontainssixregisterswhichareusedintheexecutionofasequentialintegerprocess.The six registers are: The workspace pointer ( Wptr ) which points to an area of store where local data is kept. The instruction pointer ( Iptr ) which points to the next instruction to be executed. The status register ( Status ). The Areg , Breg and Creg registers which form an evaluation stack.
The Areg ,Breg and Creg registersarethesourcesanddestinationsformostarithmeticandlogi-caloperations.Loadingavalueintothestackpushes Breg into Creg ,and Areg into Breg ,before
loading Areg .Storingavaluefrom Areg ,pops Breg into Areg and Creg into Breg .Creg isleftundefined.
Figure4.1 Registers used in sequential integer processes
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Expressionsareevaluatedontheevaluationstack,andinstructionsrefertothestackimplicitly.Forexample,the add instructionaddsthetoptwovaluesinthestackandplacestheresultonthetopofthestack.Theuseofastackremovestheneedforinstructionstoexplicitlyspecifythelocationoftheiroperands.Nohardwaremechanismisprovidedtodetectthatmorethanthreevalueshavebeen loaded onto the stack; it is easy for the compiler to ensure that this never happens.
Notethatalocationinmemorycanbeaccessedrelativetotheworkspacepointer,enablingtheworkspace to be of any size.
The use of shadow registers provides fast, simple and clean context switching.
4.2 Processes and concurrency
Thefollowingsectiondescribes‘default’behavioroftheCPUanditshouldbenotedthattheusercan alter this behavior, for example, by disabling timeslicing, installing a user scheduler, etc.processstarts,performsanumberofactions,andtheneitherstopswithoutcompletingortermi-natescomplete.Typically,aprocessisasequenceofinstructions.TheCPUcanrunseveralpro-cessesinparallel(concurrently).Processesmaybeassignedeitherhighorlowpriority,andtheremay be any number of each.
Theprocessorhasamicrocodedschedulerwhichenablesanynumberofconcurrentprocessestobeexecutedtogether,sharingtheprocessortime.Thisremovestheneedforasoftwarekernel,
although kernels can still be written if desired.
At any time, a process may be
active -being executed,-interrupted by a higher priority process,-on a list waiting to be executed.
inactive -waiting to input,-waiting to output,-waiting until a specified time.
Thescheduleroperatesinsuchawaythatinactiveprocessesdonotconsumeanyprocessortime.Eachactivehighpriorityprocessexecutesuntilitbecomesinactive.Theschedulerallocatesapor-tionoftheprocessor’stimetoeachactivelowpriorityprocessinturn(seesection4.3).Activepro-cesseswaitingtobeexecutedareheldintwolinkedlistsofprocessworkspaces,oneofhighpriorityprocessesandoneoflowpriorityprocesses.Eachlistisimplementedusingtworegisters,
oneofwhichpointstothefirstprocessinthelist,theothertothelast.InthelinkedprocesslistshowninFigure4.2,process Sisexecutingand P,Qand Rareactive,awaitingexecution.Onlythelowpriorityprocessqueueregistersareshown;thehighpriorityprocessonesbehaveinasimilarmanner.
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Figure4.2 Linked process list
Eachprocessrunsuntilithascompleteditsactionorisdescheduled.Inorderforseveralpro-cessestooperateinparallel,alowpriorityprocessisonlypermittedtoexecuteforamaximumoftwotimesliceperiods.Afterthis,themachinedeschedulesthecurrentprocessatthenexttimeslic-ingpoint,addsittotheendofthelowpriorityschedulinglistandinsteadexecutesthenextactiveprocess. The timeslice period is 1ms.
Thereareonlycertaininstructionsatwhichaprocessmaybedescheduled.Theseareknownasdeschedulingpoints.Aprocessmayonlybetimeslicedatcertaindeschedulingpoints.Theseareknownastimeslicingpointsandaredefinedinsuchawaythattheoperandstackisalwaysempty.Thisremovestheneedforsavingtheoperandstackwhentimeslicing.Asaresult,anexpressionevaluation can be guaranteed to execute without the process being timesliced part way through.
Wheneveraprocessisunabletoproceed,itsinstructionpointerissavedintheprocessworkspaceand the next process taken from the list.
Theprocessorcoreprovidesanumberofspecialinstructionstosupporttheprocessmodel,includ-ing startp (startprocess)and endp (endprocess).Whenamainprocessexecutesaparallelcon-struct, startp isusedtocreatethenecessaryadditionalconcurrentprocesses.A startp instructioncreatesanewprocessbyaddinganewworkspacetotheendoftheschedulinglist,enablingthenewconcurrentprocesstobeexecutedtogetherwiththeonesalreadybeingexecuted.Whenaprocessismadeactiveitisalwaysaddedtotheendofthelist,andthuscannotpre-emptpro-cesses already on the same list.
Thecorrectterminationofaparallelconstructisassuredbyuseofthe endp instruction.Thisusesadatastructurethatincludesacounteroftheparallelconstructcomponentswhichhavestilltoter-
Table4.1 Priority queue control registers
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minate.Thecounterisinitializedtothenumberofcomponentsbeforetheprocessesarestarted.Eachcomponentendswithan endp instructionwhichdecrementsandteststhecounter.Forallbutthelastcomponent,thecounterisnonzeroandthecomponentisdescheduled.Forthelastcom-ponent, the counter is zero and the main process continues.
4.3 Priority
Thefollowingsectiondescribes‘default’behavioroftheCPUanditshouldbenotedthattheusercan alter this behavior, for example, by disabling timeslicing and priority interrupts.
Theprocessorcanexecuteprocessesatoneoftwoprioritylevels,onelevelforurgent(highprior-ity)processes,oneforlessurgent(lowpriority)processes.Ahighpriorityprocesswillalwaysexe-cute in preference to a low priority process if both are able to do so.
Highpriorityprocessesareexpectedtoexecuteforashorttime.Ifoneormorehighprioritypro-cessesareactive,thenthefirstonthequeueisselectedandexecutesuntilithastowaitforacom-munication, a timer input, or until it completes processing.noprocessathighpriorityisactive,butoneormoreprocessesatlowpriorityareactive,thenoneisselected.Lowpriorityprocessesareperiodicallytimeslicedtoprovideanevendistributionofpro-cessor time between tasks which use a lot of computation.thereare nlowpriorityprocesses,thenthemaximumlatencyfromthetimeatwhichalowpriorityprocessbecomesactivetothetimewhenitstartsprocessingistheorderof2 ntimesliceperiods.Itisthenabletoexecuteforbetweenoneandtwotimesliceperiods,lessanytimetakenbyhighpri-orityprocesses.ThisassumesthatnoprocessmonopolizesthetimeoftheCPU;i.e.ithasfre-quent timeslicing points.
ThespecificconditionforahighpriorityprocesstostartexecutionisthattheCPUisidleorrunningat low priority and the high priority queue is non-empty.ahighpriorityprocessbecomesabletorunwhilealowpriorityprocessisexecuting,thelowpri-orityprocessistemporarilystoppedandthehighpriorityprocessisexecuted.Thestateofthelow
priorityprocessissavedinto‘shadow’registersandthehighpriorityprocessisexecuted.Whennofurtherhighpriorityprocessesareabletorun,thestateoftheinterruptedlowpriorityprocessisre-loadedfromtheshadowregistersandtheinterruptedlowpriorityprocesscontinuesexecuting.Instructionsareprovidedontheprocessorcoretoallowahighpriorityprocesstostoretheshadowregisterstomemoryandtoloadthemfrommemory.Instructionsarealsoprovidedtoallowapro-cesstoexchangeanalternativeprocessqueueforeitherpriorityprocessqueue(seeTable7.21onpage49).Theseinstructionsallowextensionstobemadetotheschedulerforcustomrun-timeker-nels.lowpriorityprocessmaybeinterruptedafterithascompletedexecutionofanyinstruction.Inaddition,tominimizethetimetakenforaninterruptinghighpriorityprocesstostartexecuting,thepotentiallytimeconsuminginstructionsareinterruptible.Alsosomeinstructionsmaybeaborted,and are restarted when the process next becomes active (refer to the Instruction Set chapter).
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4.4 Process communications
Communicationbetweenprocessestakesplaceoverchannels,andisimplementedinhardware.Communicationispoint-to-point,synchronizedandunbuffered.Asaresult,achannelneedsnoprocess queue, no message queue and no message buffer.channelbetweentwoprocessesexecutingonthesameCPUisimplementedbyasinglewordinmemory;achannelbetweenprocessesexecutingondifferentprocessorsisimplementedbypoint-to-pointlinks.Theprocessorprovidesanumberofoperationstosupportmessagepassing,themost important being in(input message) and out (output message).
The inand out instructionsusetheaddressofthechanneltodeterminewhetherthechannelisinternalorexternal.Thismeansthatthesameinstructionsequencecanbeusedforbothhardandsoftchannels,allowingaprocesstobewrittenandcompiledwithoutknowledgeofwhereitschan-nels are implemented.
Communicationtakesplacewhenboththeinputtingandoutputtingprocessesareready.Conse-quently,theprocesswhichfirstbecomesreadymustwaituntilthesecondoneisalsoready.Theinputting and outputting processes only become active when the communication has completed.processperformsaninputoroutputbyloadingtheevaluationstackwith,apointertoamessage,
theaddressofachannel,andacountofthenumberofbytestobetransferred,andthenexecutingan in or out instruction.
4.5 Timers
Therearetwo32-bithardwaretimerclockswhich‘tick’periodically.Theseareindependentofanyon-chipperipheralrealtimeclock.Thetimersprovideaccurateprocesstiming,allowingprocessesto deschedule themselves until a specific time.
Onetimerisaccessibleonlytohighpriorityprocessesandisincrementedapproximatelyeverymicrosecond,cyclingcompletelyinapproximately4295seconds.Theotherisaccessibleonlytolowpriorityprocessesandisincrementedapproximatelyevery64microseconds,giving15625tickspersecond.Ithasafullperiodofapproximately76hours.Timerfrequenciesareapproximate.
Thecurrentvalueoftheprocessorclockcanbereadbyexecutinga ldtimer (loadtimer)instruction.Aprocesscanarrangetoperforma tin (timerinput),inwhichcaseitwillbecomereadytoexecuteafteraspecifiedtimehasbeenreached.The tin instructionrequiresatimetobespecified.Ifthistimeisinthe‘past’thentheinstructionhasnoeffect.Ifthetimeisinthe‘future’thentheprocessisdescheduled.Whenthespecifiedtimeisreachedtheprocessbecomesactive.Inaddition,theable4.2 Timer registers
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ldclock (loadclock), stclock (storeclock)instructionsallowtotalcontrolovertheclockvalueandtheclockenb (clockenable), clockdis (clockdisable)instructionsalloweachclocktobeindividuallystopped and re-started.
Figure4.3showstwoprocesseswaitingonthetimerqueue,onewaitingfortime21,theotherfortime 31.
Figure4.3 Timer registers
4.6 Traps and exceptionssoftwareerror,suchasarithmeticoverfloworarrayboundsviolation,cancauseanerrorflagtobesetintheCPU.Theflagisdirectlyconnectedtothe ErrorOut pin.Boththeflagandthepincanbeignored,ortheCPUstopped.StoppingtheCPUonanerrormeansthattheerrorcannotcausefurthercorruption.AswellascontainingtheerrorinthiswayitispossibletodeterminethestateoftheCPUanditsmemoryatthetimetheerroroccurred.Thisisparticularlyusefulforpostmortemdebuggingwherethedebuggercanbeusedtoexaminethestateandhistoryoftheprocessorleading up to and causing the error condition.addition,ifatraphandlerprocessisinstalled,avarietyoftraps/exceptionscanbetrappedandhandledbysoftware.Ausersuppliedtraphandlerroutinecanbeprovidedforeachhigh/lowpro-cessprioritylevel.Thehandlerisstartedwhenatrapoccursandisgiventhereasonforthetrap.Thetraphandlerisnotre-entrantandmustnotcauseatrapitselfwithinthesamegroup.Alltraps
can be individually masked.
4.6.1Trap groups
Thetrapmechanismisarrangedonaperprioritybasis.Foreachprioritythereisahandlerforeachgroup of traps, as shown in Figure4.4.
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Figure4.4 Trap arrangement
There are four groups of traps, as detailed below. Breakpoint
Thisgroupconsistsofthe Breakpoint trap.Thebreakpointinstruction( j0)callsthebreak-point routine via the trap mechanism. Errors
Thetrapsinthisgroupare IntegerError and Overflow .Overflow representsarithmeticover-flow,suchasarithmeticresultswhichdonotfitintheresultword. IntegerError representserrorscausedwhendataiserroneous,forexamplewhenarangecheckinginstructionfindsthat data is out of range. System operations
Thisgroupconsistsofthe LoadTrap ,StoreTrap and IllegalOpcode traps.The IllegalOpcodetrapissignalledwhenanattemptismadetoexecuteanillegalinstruction.The LoadTrapand StoreTrap trapsallowakerneltointerceptattemptsbyamonitoredprocesstochangeorexaminetraphandlersortrappedprocessinformation.Itenablesauserprogramtosig-nal to a kernel that it wishes to install a new trap handler. Scheduler
Theschedulertrapgroupconsistsofthe ExternalChannel,InternalChannel,Timer,TimeSlice,Run,Signal,ProcessInterrupt and QueueEmpty traps.The ProcessInterrupttrapsignalsthatthemachinehasperformedapriorityinterruptfromlowtohigh.TheQueueEmpty trapindicatesthatthereisnofurtherexecutableworktoperform.Theothertrapsinthisgroupindicatethatthehardwareschedulerwantstoscheduleaprocessonaprocessqueue,withthedifferenttrapsenablingthedifferentsourcesofthistobemoni-tored.
Theschedulertrapsenableasoftwareschedulerkerneltousethehardwareschedulertoimplement a multi-priority software scheduler.
Notethatschedulertrapsaredifferentfromothertrapsastheyarecausedbythemicro-scheduler rather than by an executing process.rapgroupsencodingisshowninTable4.3below.Thesecodesareusedtoidentifytrapgroupstovarious instructions.
ST20-GP6additiontothetrapgroupsmentionedabove,the CauseError flaginthe Status registerisusedtosignalwhenatrapconditionhasbeenactivatedbythe causeerror instruction.Itcanbeusedtoindicatewhentrapconditionshaveoccurredduetotheusersettingthem,ratherthanbythesys-tem.
4.6.2Events that can cause trapsable4.4summarizestheeventsthatcancausetrapsandgivestheencodingofbitsinthetrapStatus and Enable words.
Table4.3 Trap group codesable4.4 Trap causes and Status /Enable codes
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4.6.3Trap handlers
Foreachtraphandlerthereisatraphandlerstructureandatrappedprocessstructure.Boththetraphandlerstructureandthetrappedprocessstructureareinmemoryandcanbeaccessedviainstructions, see section 4.6.4.
Thetraphandlerstructurespecifieswhatshouldhappenwhenatrapconditionispresent,seeTable4.5.
Thetrappedprocessstructuresavessomeofthestateoftheprocessthatwasrunningwhenthetrap was taken, see Table4.6.addition,foreachpriority,thereisan Enables registeranda Status register.The Enables regis-tercontainsflagstoenableeachcauseoftrap.The Status registercontainsflagstoindicatewhichtrapconditionshavebeendetected.The Enables and Status registerbitencodingsaregiveninTable4.4.trapwillbetakenataninterruptiblepointifatrapissetandthecorrespondingtrapenablebitissetinthe Enables register.Ifthetrapisnotenabledthennothingisdonewiththetrapcondition.Ifthetrapisenabledthenthecorrespondingbitissetinthe Status registertoindicatethetrapcon-dition has occurred.
Whenaprocesstakesatraptheprocessorsavestheexisting Iptr ,Wptr ,Status and Enables inthetrappedprocessstructure.Itthenloads Iptr ,Wptr and Status fromtheequivalenttraphandlerstructureandANDsthevaluein Enables withthevalueinthestructure.Thisallowstheusertodis-ablevariouseventswhileinthehandler,inparticularatraphandlermustdisableallthetrapsofitstrap group to avoid the possibility of a handler trapping to itself.
Thetraphandlerthenexecutes.Thevaluesinthetrappedprocessstructurecanbeexaminedusingthe ldtrapped instruction(seesection4.6.4).Whenthetraphandlerhascompleteditsopera-
Table4.5 Trap handler structure
Table4.6 Trapped process structure
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tionitreturnstothetrappedprocessviathe tret (trapreturn)instruction.Thisreloadsthevaluessaved in the trapped process structure and clears the trap flag in Status .
Notethatwhenatraphandlerisstarted, Areg ,Breg and Creg arenotsaved.Thetraphandlermust save the Areg ,Breg ,Creg registers using stl (store local).
4.6.4Trap instructionsraphandlersandtrappedprocessescanbesetupandexaminedviathe ldtraph ,sttraph ,ldtrapped and sttrapped instructions.Table4.7describestheinstructionsthatmaybeusedwhendealing with traps.
Thefirstfourinstructionstransferdatato/fromthetraphandlerstructuresortrappedprocessstruc-turesfrom/toanareainmemory.Intheseinstructions Areg containsthetrapgroupcode(seeTable4.3)and Breg pointstothe4wordareaofmemoryusedasthesourceordestinationofthetransfer.Inaddition Creg containsthepriorityofthehandlertobeinstalled/examinedinthecaseofldtraph or sttraph. ldtrapped and sttrapped apply only to the current priority.the LoadTrap trapisenabledthen ldtraph and ldtrapped donotperformthetransferbutsettheLoadTrap trapflag.Ifthe StoreTrap trapisenabledthen sttraph and sttrapped donotperformthetransfer but set the StoreTrap trap flag.
Thetrapenablemasksareencodedbyanarrayofbits(seeTable4.4)whicharesettoindicatewhichtrapsareenabled.Thisarrayofbitsisstoredinthelowerhalf-wordofthe Enables register.Thereisan Enables registerforeachpriority.TrapsareenabledordisabledbyloadingamaskintoAreg withbitssettoindicatewhichtrapsaretobeaffectedandtheprioritytoaffectin Breg .Exe-cuting trapenb ORsthemasksuppliedin Areg withthetrapenablesmaskinthe Enables registerforthepriorityin Breg .Executing trapdis negatesthemasksuppliedin Areg andANDsitwiththetrapenablesmaskinthe Enables registerforthepriorityin Breg .Bothinstructionsreturnthepre-vious value of the trap enables mask in Areg .able4.7 Instructions which may be used when dealing with traps
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4.6.5Restrictions on trap handlers
Therearevariousrestrictionsthatmustbeplacedontraphandlerstoensurethattheyworkcor-rectly.Traphandlersmustnotdescheduleortimeslice.Traphandlersalterthe Enables masks,therefore they must not allow other processes to execute until they have completed.Traphandlersmusthavetheir Enable maskssettomaskalltrapsintheirtrapgrouptoavoid the possibility of a trap handler trapping to itself.Traphandlersmustterminateviathe tret (trapreturn)instruction .Theonlyexceptiontothisis that a scheduler kernel may use restart to return to a previously shadowed process.
ST20-GP6 Interrupt controller
TheST20-GP6supportsexternalinterrupts,enablinganon-chipsubsystemorexternalinterruptpin to interrupt the currently running process in order to run an interrupt handling process
TheST20-GP6interruptsubsystemsupportseightprioritizedinterrupts.Thisallowsnestedpre-emptiveinterruptsforreal-timesystemdesign.Inaddition,thereisaninterruptlevelcontroller(refertoChapter6)whichmultiplexesincominginterruptsontotheeightprogrammableinterruptlevels.Thismultiplexingiscontrollablebysoftware.Thereare6sourcesofinterrupts.Fouroftheseare internal (2 for the UARTs, 2 for the programmable IO) and two are external.
Allinterruptsareahigherprioritythanthelowpriorityprocessqueue.Eachinterruptcanbepro-
grammedtobeatalowerpriorityorahigherprioritythanthehighpriorityprocessqueue,thisisdetermined by the Priority bit in the HandlerWptr0-7 registers, see Table5.1 on page33.
Note:Interrupts( Interrupt0-7 )whicharespecifiedashigherprioritymustbecontiguousfromthehighestnumberedinterruptdownwards,i.e.if4interruptsareprogrammedashigherpriorityand4aslowerprioritythehigherpriorityinterruptsmustbe Interrupt7:4 andthelowerpriorityinterruptsInterrupt3:0 .
NotethatinterrupthandlersmustnotpreventtheGPSDSPdatatrafficfrombeinghandled.Duringcontinuousoperationthishas1mslatencyandisnotaproblem,butduringinitialacquisitionithasa32 μsrateandthuscaremustbetakenwithinterruptprioritiesunlessusedtostopGPSopera-tion.
Figure5.1 Interrupt priority
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InterruptsontheST20-GP6areimplementedviaanon-chipinterruptcontrollerperipheral.Aninterrupt can be signalled to the controller by one of the following: a signal on an external Interrupt pin a signal from an internal peripheral or subsystem software asserting an interrupt in the Pending register
5.1 Interrupt vector table
Theinterruptcontrollercontainsatableofpointerstointerrupthandlers.Eachinterrupthandlerisrepresentedbyitsworkspacepointer( Wptr ).Thetablecontainsaworkspacepointerforeachlevelof interrupt.
The Wptr givesaccesstothecode,dataandinterruptsavespaceoftheinterrupthandler.Theposition of the Wptr in the interrupt table implies the priority of the interrupt.
Run-time library support is provided for setting and programming the vector table.
5.2 Interrupt handlersanyinterruptiblepointinitsexecutiontheCPUcanreceiveaninterruptrequestfromtheinter-rupt controller. The CPU immediately acknowledges the request.responsetoreceivinganinterrupttheCPUperformsaprocedurecalltotheprocessinthevec-tortable.Thestateoftheinterruptedprocessisstoredintheworkspaceoftheinterrupthandlerasshown in Figure5.2. Each interrupt level has its own workspace.
Figure5.2 State of interrupted process
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Theinterruptroutineisinitializedwithspacebelow Wptr .The Iptr and Status wordfortheroutinearestoredtherepermanently.Thisshouldbeprogrammedbeforethe Wptr iswrittenintothevectortable.ThebehavioroftheinterruptdiffersdependingonthepriorityoftheCPUwhentheinterruptoccurs.
WhenaninterruptoccurswhentheCPUwasrunningathighpriority,andtheinterruptissetatahigherprioritythanthehighpriorityprocessqueue,theCPUsavesthecurrentprocessstate(Areg ,Breg ,Creg ,Wptr ,Iptr and Status )intotheworkspaceoftheinterrupthandler.ThevalueHandlerWptr ,whichisstoredintheinterruptcontroller,pointstothetopofthisworkspace.The
valuesof Iptr and Status tobeusedbytheinterrupthandlerareloadedfromthisworkspaceandstarts executing the handler. The value of Wptr is then set to the bottom of this save area.
WhenaninterruptoccurswhentheCPUwasrunningathighpriority,andtheinterruptissetatalowerprioritythanthehighpriorityprocessqueue,noactionistakenandtheinterruptwaitsinaqueue until all higher priority interrupts have been serviced (see section 5.4).
Interruptsalwaystakepriorityoverlowpriorityprocesses.WhenaninterruptoccurswhentheCPUwasidleorrunningatlowpriority,the Status issaved.Thisindicatesthatnovalidprocessisrun-ning( NullStatus ).Theinterruptedprocesses(lowpriorityprocess)stateisstoredinshadowregis-ters.Thisstatecanbeaccessedviathe ldshadow (loadshadowregisters)and stshadow (storeshadow registers) instructions. The interrupt handler is then run at high priority.
Whentheinterruptroutinehascompleteditmustadjust Wptr tothevalueatthestartofthehan-dlercodeandthenexecutethe iret (interruptreturn)instruction.Thisrestorestheinterruptedstatefromtheinterrupthandlerstructureandsignalstotheinterruptcontrollerthattheinterrupthascompleted. The processor will then continue from where it was before being interrupted.
5.3 Interrupt latency
Theinterruptlatencyisdependentonthedatabeingaccessedandthepositionoftheinterrupthandlerandtheinterruptedprocess.Thisallowssystemstobedesignedwiththebesttrade-offuseof fast internal memory and interrupt latency.
5.4 Preemption and interrupt priority
Eachinterruptchannelhasanimpliedpriorityfixedbyitsplaceintheinterruptvectortable.Allinterruptswillcausescheduledprocessesoflowerprioritytobesuspendedandtheinterrupthan-dlerstarted.OnceaninterrupthasbeensentfromthecontrollertotheCPUthecontrollerkeepsarecordofthecurrentexecutinginterruptpriority.Thisisonlyclearedwhentheinterrupthandlerexecutesareturnfrominterrupt( iret )instruction.Interruptsofalowerpriorityarrivingwillbeblockedbytheinterruptcontrolleruntiltheinterruptpriorityhasdescendedtosuchalevelthattheroutinewillexecute.AninterruptofahigherprioritythanthecurrentlyexecutinghandlerwillbepassedtotheCPUandcausethecurrenthandlertobesuspendeduntilthehigherpriorityinterruptis serviced.thiswayinterruptscanbenestedandahigherpriorityinterruptwillalwayspre-emptalowerpri-orityone.DeepnestingandplacingfrequentinterruptsathighprioritycanresultinasystemwherelowpriorityinterruptsareneverservicedorthecontrollerandCPUtimeareconsumedinnesting
interrupt priorities and not executing the interrupt handlers.
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5.5 Restrictions on interrupt handlers
Therearevariousrestrictionsthatmustbeplacedoninterrupthandlerstoensurethattheyinteractcorrectly with the rest of the process model implemented in the CPU.Interrupt handlers must not deschedule.Interrupthandlersmustnotexecutecommunicationinstructions.Howevertheymaycom-municatewithotherprocessesthroughsharedvariablesusingthesemaphore signal tosynchronize.Interrupt handlers must not perform 2d block move instructions.Interrupthandlersmustnotcauseprogramtraps.Howevertheymaybetrappedbyascheduler trap.
5.6 Interrupt configuration registers
Theinterruptcontrollerisallocateda4kblockofmemoryintheinternalperipheraladdressspace.Informationoninterruptsisstoredinregistersasdetailedinthefollowingsection.Theregisterscanbeexaminedandsetbythe devlw (deviceloadword)and devsw (devicestoreword)instructions.Note, they can not be accessed using memory instructions.
HandlerWptr register
The HandlerWptr registers(1perinterrupt)containapointertotheworkspaceoftheinterrupthan-dler.Italsocontainsthe Priority bitwhichdetermineswhethertheinterruptisatahigherorlowerpriority than the high priority process queue.
Note,beforetheinterruptisenabled,bywritin ga1inthe Mask register,theuser(ortoolset)mustensure that there is a valid Wptr in the register.
Table5.1 HandlerWptr register format - one register per interrupt
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TriggerMode register
Eachinterruptchannelcanbeprogrammedtotriggeronrising/fallingedgesorhigh/lowlevelsonthe external Interrupt .
Note,leveltriggeringisdifferenttoedgetriggeringinthatiftheinputisheldatthetriggeringlevel,acontinuous stream of interrupts is generated.
Mask registerinterruptmaskregisterisprovidedintheinterruptcontrollertoselectivelyenableordisableexternalinterrupts.Thismaskregisteralsoincludesaglobalinterruptdisablebittodisableallexternal interrupts whatever the state of the individual interrupt mask bits.ocomplementthistheinterruptcontrolleralsoincludesaninterruptpendingregisterwhichcon-tainsapendingflagforeachinterruptchannel.The Mask registerperformsamaskingfunctiononthe Pending registertogivecontroloverwhatisallowedtointerrupttheCPUwhileretainingtheability to continually monitor external interrupts.start-up,the Mask registerisinitializedtozeros,thusallinterruptsaredisabled,bothgloballyandindividually.Whe na1iswr ittentothe GlobalEnable bit,theindividualinterruptbitsarestilldisabledandmustalsohavea1individuallywrittentothe InterruptEnable bittoenabletherespective interrupt.
The Mask registerismappedontotwoadditionaladdressessothatbitscanbesetorclearedindi-vidually.
Table5.2 TriggerMode register format - one register per interrupt
Table5.3 Mask register format
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Set_Mask (address‘interruptbaseaddress+#C4’)allowsbitstobesetindividually.Writinga‘1’inthis register sets the corresponding bit in the Mask register, a ‘0’ leaves the bit unchanged.
Clear_Mask (address‘interruptbaseaddress+#C8’)allowsbitstobeclearedindividually.Writinga‘1’inthisregisterresetsthecorrespondingbitinthe Mask register,a‘0’leavesthebitunchanged.
Pending register
The Pending registercontainsabitperinterruptwitheachbitcontrolledbythecorrespondinginterrupt.Areadcanbeusedtoexaminethestateoftheinterruptcontrollerwhileawritecanbe
used to explicitly trigger an interrupt.bitissetwhenthetriggeringconditionforaninterruptismet.Allbitsareindependentsothatsev-eralbitscanbesetinthesamecycle.Onceabitisset,afurthertriggeringconditionwillhavenoeffect. The triggering condition is independent of the Mask register.
Thehighestpriorityinterruptbitisresetoncetheinterruptcontrollerhasmadeaninterruptrequestto the CPU.
TheinterruptcontrollerreceivesexternalinterruptrequestsandmakesaninterruptrequesttotheCPUwhenithasapendinginterruptrequestofhigherprioritythanthecurrentlyexecutinginterrupthandler.
The Pending registerismappedontotwoadditionaladdressessothatbitscanbesetorclearedindividually.
Set_Pending (address‘interruptbaseaddress+#84’)allowsbitstobesetindividually.Writinga‘1’inthisregistersetsthecorrespondingbitinthe Pending register,a‘0’leavesthebitunchanged.
Clear_Pending (address‘interruptbaseaddress+#88’)allowsbitstobeclearedindividually.Writ-inga‘1’inthisregisterresetsthecorrespondingbitinthe Pending register,a‘0’leavesthebitunchanged.
Note,iftheCPUwantstowriteorclearsomebitsofthe Pending register,theinterruptsshouldbemasked(bywritingorclearingthe Mask register)beforewritingorclearingthe Pending register.The interrupts can then be unmasked.
Exec register
The Exec registerkeepstrackofthecurrentlyexecutingandpre-emptedinterrupts.AbitissetwhentheCPUstartsrunningcodeforthatinterrupt.Thehighestpriorityinterruptbitisresetoncethe interrupt handler executes a return from interrupt ( iret ).able5.4 Bit fields in the Pending register
Table5.5 Bit fields in the Exec register
ST20-GP6
The Exec registerismappedontotwoadditionaladdressessothatbitscanbesetorclearedindi-vidually.
Set_Exec (address‘interruptbaseaddress+#104’)allowsbitstobesetindividually.Writinga‘1’in this register sets the corresponding bit in the Exec register, a ‘0’ leaves the bit unchanged.
Clear_Exec (address‘interruptbaseaddress+#108’)allowsbitstobeclearedindividually.Writinga‘1’inthisregisterresetsthecorrespondingbitinthe Exec register,a‘0’leavesthebitunchanged.
ST20-GP6 Interrupt level controller
Thereare6interrupts(ofwhich2areexternal)generatedintheST20-GP6systemandeachoftheseisassignedtooneoftheinterruptcontroller’s8inputs.Thuseachoftheinterruptcontroller’sinputs responds to zero or more of the 8 system interrupts.interrupthandlerroutineisabletoascertainthesourceofaninterruptwheretwoormoresys-teminterruptsareassignedtoonehandlerbydoingadevicereadfromthe InputInterrupts regis-ter(seeTable6.3)andexaminingthebitsthatcorrespondtothesysteminterruptsassignedtothathandler.
Theinterruptlevelcontrollerhasadditionalfunctionalitytosupportthelowpowercontroller.The
externalinterruptsaremonitoredandasignalisgeneratedforthelowpowercontrollerwhichtellsitwhenanyofthemgoestoapre-determinedlevel.Thislevelisprogrammableforeachexternalinterrupt, and in addition each interrupt can be selectively masked.
6.1 Interrupt assignments
The interrupts from the peripherals on the ST20-GP6 are assigned as follows:
Theseinterruptsareinputstotheinterruptlevelcontroller.Thisallowstheseinterruptstobeassigned to any of eight interrupt priority levels and for multiple interrupts to share a priority level.
6.2 Interrupt level controller registers
Theinterruptlevelcontrollerisprogrammableviaconfigurationregisters.Theseregisterscanbeexamined and set by the devlw (device load word) and devsw (device store word) instructions.
IntPriority registers
The priority assigned to each of the input interrupts is programmable via the IntPriority registers.
Theinterruptlevelcontrollerassertsinterruptoutput Nwhenoneormoreoftheinputinterruptswithprogrammedpriorityequalto Narehigh.Itislevelsensitiveandre-timedattheinput,thusincurring one cycle of latency.able6.1 Interrupt assignments
ST20-GP6
InputInterrupts register
The InputInterrupts registerisareadonlyregister.Itcontainsavectorwhichshowsalloftheinputinterrupts, so bit 0 of the read data corresponds to InterruptIn0 , bit 1 corresponds to InterruptIn1 .
Low power controller support registers
Theinterruptlevelcontrollerhas2additionalregisterstosupportthelowpowercontroller(seeChapter11onpage66).Theexternalinterruptscanbeusedtoprovideawake-upfrompower-down mode.
The IntLPEnable registercanbeprogrammedforeachinterrupttocausetheinterrupttowake-uptheST20-GP6frompower-downmode.Thewake-upoccurswhentheinterruptgoeseitherhighorlow, depending on the setting of the respective bit in the IntActiveHigh register.
IntLPEnable
The IntLPEnable registercanbesettoenableawake-upfrompower-downmodewhentheinter-rupt occurs.able6.2 IntPriority register format - 1 register per interruptable6.3 InputInterrupts register format
ST20-GP6
IntActiveHigh
Thesettingofthe IntActiveHigh registerdetermineswhetherthewake-upoccurswhentheinter-ruptgoeshighorlow,assumingtheinterrupthasbeenenabledtocauseawake-upinthe IntL-PEnable register.able6.4 IntLPEnable register formatable6.5 IntActiveHigh register format
ST20-GP6 Instruction set
ThischapterprovidesinformationontheST20-C2instructionset.Itcontainstableslistingalltheinstructions,andwhereapplicableprovidesdetailsofthenumberofprocessorcyclestakenbyaninstruction.
Theinstructionsethasbeendesignedforsimpleandefficientcompilationofhigh-levellanguages.Allinstructionshavethesameformat,designedtogiveacompactrepresentationoftheoperationsoccurring most frequently in programs.
Eachinstructionconsistsofasinglebytedividedintotwo4-bitparts.Thefourmostsignificantbits(MSB)ofthebyteareafunctioncodeandthefourleastsignificantbits(LSB)areadatavalue,as
shown in Figure7.1.
Figure7.1 Instruction format
Forfurtherinformationontheinstructionsetrefertothe ST20C2/C4InstructionSetManual (docu-ment number 72-TRN-273).
7.1 Instruction cycles
Timinginformationisavailableforsomeinstructions.However,itshouldbenotedthatmanyinstructions have ranges of timings which are data dependent.
Whereincluded,timinginformationisbasedonthenumberofclockcyclesassuminganymemoryaccessesareto2cycleinternalmemoryandnoothersubsystemisusingmemory.Actualtimewillbe dependent on the speed of external memory and memory bus availability.
Note that the actual time can be increased by:theinstructionrequiringavalueontheregisterstackfromthefinalmemoryreadinthepre-vious instruction – the current instruction will stall until the value becomes available.thefirstmemoryoperationinthecurrentinstructioncanbedelayedwhileaprecedingmemoryoperationcompletes-anytwomemoryoperationscanbeinprogressatanytime,any further operation will stall until the first completes.memoryoperationsincurrentinstructionscanbedelayedbyaccessbyinstructionfetchorsubsystems to the memory interface.therecanbeadelaybetweeninstructionswhiletheinstructionfetchunitfetchesandpar-tiallydecodesthenextinstruction–thiswillbethecasewheneveraninstructioncausestheinstruction flow to jump.
Notethattheinstructiontimingsgivenreferto‘standard’behaviorandmaybedifferentif,forexam-ple, traps are set by the instruction.
ST20-GP6
7.2 Instruction characteristicsable7.3givesthebasicfunctioncodeofeachoftheprimaryinstructions.Wheretheoperandislessthan16,asinglebyteencodesthecompleteinstruction.Iftheoperandisgreaterthan15,oneprefixinstruction( pfix )isrequiredforeachadditionalfourbitsoftheoperand.Iftheoperandisneg-ative the first prefix instruction will be nfix . Examples of pfix and nfix coding are given in Table7.1.
Anyinstructionwhichisnotintheinstructionsettablesisaninvalidinstructionandisflaggedille-gal, returning an error code to the trap handler, if loaded and enabled.
The Notes column of the tables indicates the features of an instruction as described in Table7.2 .
Table7.1 Prefix codingable7.2 Instruction features
ST20-GP6
7.3 Instruction set tables
Table7.3 Primary functionsable7.4 Processor initialization operation codes
ST20-GP6able7.5 Arithmetic/logical operation codes
ST20-GP6
Table7.6 Long arithmetic operation codes
Table7.7 General operation codes
ST20-GP6able7.8 Indexing/array operation codesable7.9 Timer handling operation codes
ST20-GP6able7.10 Input and output operation codesable7.11 Control operation codes
Table7.12 Scheduling operation codes
ST20-GP6
Table7.13 Error handling operation codesable7.14 2D block move operation codes
Table7.15 CRC and bit operation codes
ST20-GP6
Table7.16 Floating point support operation codes
Table7.17 Range checking and conversion instructionsable7.18 Indexing/array instructions
ST20-GP6able7.19 Device access instructions
Table7.20 Semaphore instructionsable7.21 Scheduling support instructions
ST20-GP6
Table7.22 Trap handler instructionsable7.23 Processor initialization and no operation instructions
Table7.24 Clock instructions
ST20-GP6 Memory map
TheST20-GP6processormemoryhasa32-bitsignedaddressrange.Wordsareaddressedby30-bitwordaddressesanda2-bitbyte-selectoridentifiesthebytesintheword.Memoryisdividedinto4bankswhichcaneachhavedifferentmemorycharacteristicsandcanbeusedfordifferentpurposes.Inaddition,on-chipperipheralscanbeaccessedviathedeviceaccessinstructions(seeTable7.19).Thebottom16KbytesoftheinternalSRAMarepoweredfromthebatterybackupsupply.
Variousmemorylocationsatthebottomandtopofmemoryarereservedforspecialsystempurposes. There is also a default allocation of memory banks to different uses.
NotethattheST20-GP6uses30bitsofaddressinginternally,butaddressesA20-A29arenotbroughtouttoexternalpins.AddressbitsA30andA31aredecodedinternallyforuseasbankselects.
8.1 System memory use
TheST20-GP6hasasignedaddressspacewheretheaddressrangesfrom MinInt (#80000000)atthebottomto MaxInt (#7FFFFFFF)atthetop.TheST20-GP6hasanareaof64KbytesofSRAMatthebottomoftheaddressspaceprovidedbyonchipmemory.Thebottomofthisareaisusedtostorevariousitemsofsystemstate.Theseaddressesshouldnotbeaccesseddirectlybutvia the appropriate instructions.
Nearthebottomoftheaddressspacethereisaspecialaddress MemStart .Memoryabovethisaddressisforusebyuserprogramswhileaddressesbelowitareforprivateusebytheprocessorandusedforsubsystemchannelsandtraphandlers.Theaddressof MemStart canbeobtained
via the ldmemstartval instruction.
8.1.1Subsystem channels memory
EachDMAchannelbetweentheprocessorandasubsystemisallocatedawordofstoragebelowMemStart .Thisisusedbytheprocessortostoreinformationaboutthestateofthechannel.Thisinformationshouldnotnormallybeexamineddirectly,althoughdebuggingkernelsmayneedtodoso.
8.1.2Trap handlers memory
Theareaofmemoryreservedfortraphandlersisbrokendownhierarchically.Fulldetailsontrap
handlers is given in see Section4.6 on page23. Each high/low process priority has a set of trap handlers. Eachsetoftraphandlershasahandlerforeachofthefourtrapgroups(refertoSection4.6.1). Each trap group handler has a trap handler structure and a trapped process structure. Each of the structures contains four words, as detailed in Section 4.6.3.
ST20-GP6
Thecontentsoftheseaddressescanbeaccessedvia ldtraph ,sttraph ,ldtrapped and sttrappedinstructions.
8.2 Boot ROM
Thereis128KbytesofmaskROMon-chip.Thisismappedtotheupper128Kofbank3(addresses #7FFE0000 to #7FFFFFFF).
If mask ROM is not programmed, internal ROM is disabled and external ROM is used.
WhentheprocessorbootsfromROM,itjumpstoabootprogramheldinROMwithanentrypoint2bytesfromthetopofmemoryat#7FFFFFFE.These2bytesareusedtoencodeanegativejumpofupto256bytesdownintheROMprogram.ForlargeROMprogramsitmaythenbenecessaryto encode a longer negative jump to reach the start of the routine.
8.3 Internal peripheral space
On-chipperipheralsaremappedtoaddressesintheaddressrange#00000000to#3FFFFFFF).Theycanonlybeaccessedbythedeviceaccessinstructions(seeTable7.19).Whenusedwithaddressesinthisrange,thedeviceinstructionsaccesstheon-chipperipheralsratherthanexternalmemory.Forallotheraddressesthedeviceinstructionsaccessmemory.Standardload/storeinstructions to these addresses will access external memory.
Each on-chip peripheral occupies a 4K block, see the following memory map.
ST20-GP6
Figure 8.1 ST20-GP6 internal peripheral map
ST20-GP6
Figure 8.1 ST20-GP6 internal peripheral map
ST20-GP6 Memory subsystem
ThememorysystemconsistsofSRAMandaprogrammablememoryinterface.Thespecificdetailson the operation of the memory interface are described separately in Chapter10.
9.1 SRAM
Thereisaninternalmemorymoduleof64KbytesofSRAM.TheinternalSRAMismappedintothebase of the memory space from MinInt (#80000000) extending upwards.
This memory can be used to store on-chip data, stack or code for time critical routines.
Optional external RAM, if fitted, is addressed from #81000000.
9.2 ROM
There is 128 Kbytes of on-chip ROM for application code.
ST20-GP6Programmable memory interface
TheST20-GP6programmablememoryinterfacehasa16bitdatabusandprovidesgluelesssupportforuptofourbanksofSRAMmemory.SufficientconfigurationoptionsareprovidedtoenabletheinterfacetobeusedwithawidevarietyofSRAMspeeds,permittingsystemstobebuiltwith optimum price/performance trade-offs.
Theprogrammablememoryinterfaceisalsoreferredtoastheexternalmemoryinterface(EMI).TheEMIprovidesconfigurationinformationforfourindependentbanksofexternalmemorydevices.Theaddressesofthesebankboundariesarehardwiredtogiveeachbankonequarteroftheaddressspaceofthemachine.Bank0occupiesthelowestquarterofthe[signed]address
space, bank 3 is the highest, see Figure10.1.
TheconfigurationisheldinmemorymappedregisterswithintheEMI.Eachbankhas64bitstohold configuration data. This data is accessed as four 16-bit accesses.
TheEMIconfigurationsoftwareensuresthattheconfigurationofabankisconsistentandworkswith all devices in the bank before any access to that bank.
Defaultconfigurationsonstart-up(see“Defaultconfiguration”onpage65)allowtheslowestmemory to be accessed.
Fourconfigurationcontrolregisters(oneforeachbank)areprovidedwhichallowtheconfigurationdataregisterstobelocked.Thispreventsanaccidentaloverwritefromdestroyingtheemiconfiguration.Aconfigurationstatusregisterisalsoprovidedtoshowwhichbankshavebeenlocked and which banks have been configured.
ThememorymapfortheconfigurationregisterswithintheEMIcontains16x16-bitdataregisterseachlocatedatwordboundary,plusfourlockcontrolregistersandaglobalregisterforstatusinformation.
ST20-GP6
Figure 10.1 Memory allocation
ST20-GP6
10.1EMI signal descriptions
ThefollowingsectiondescribesthefunctionsoftheEMIpins.Notethatasignalnameprefixedbynot indicates active low.
MemAddr1-19
Externaladdressbus.TheST20-GP6uses30bitsofaddressinginternallybutonlythebottom18bitsarebroughtouttoexternalpins( MemAddr2-19 );MemAddr1 isgeneratedbytheEMI.MemAddr1-19 isvalidandconstantforthewholedurationofanexternalaccess.Thememorylocationsineachbankcanbeaccessedatmultipleaddresses,asbits20-29areignoredwhenmaking external accesses.
MemData0-15
Externaldatabus.Thedatabusmaybeconfiguredtobeeither8or16bitswideonaperbankbasis. MemData0 isalwaystheleastsignificantbit. MemData7 isthemostsignificantbitin8-bitmodeand MemData15 isthemostsignificantbitin16-bitmode.Whenperformingawriteaccesstoabankconfiguredtobe8-bitswide, MemData8-15 areheldinahigh-impedancestateforthedurationoftheaccess; MemData0-7 behaveaccordingtotheconfigurationparametersasspecifiedinSection10.4.Whenmakingawritetoabankconfiguredtobe16-bitswide,MemData0-15 behave according to the configuration parameters.
notMemCE0-3
Chipenablestrobes,oneperbank.The notMemCE0-3 strobecorrespondingtothebankbeingaccessed will be active on both reads and writes to that bank.
notMemOE0
Outputenablestrobe.Thisstrobeissharedbetweenallfourbanks.The notMemOE0 strobewillbe active only on reads to the bank.
notMemBE0-1
Byteenablestrobestoselectbyteswithina16-bithalf-word.Thesestrobesaresharedbetweenallfourbanks. notMemBE0 alwayscorrespondstodataon MemData0-7 whetherthebusiscurrently8or16bitswide.WhentheEMIisaccessingabankconfiguredtobe16bitswide, notMemBE1correspondsto MemData8-15 .WhentheEMIisaccessingabankconfiguredtobe8bitswide,notMemBE1 becomes address bit 0 and follows the timing of MemAddr1-19 for that bank.
MemWait
Haltexternalaccess.TheEMIsamples MemWait atorjustafterthemidpointofanaccess.IfMemWait issampledhigh,theaccessisstalled. MemWait willthencontinuetobesampledandtheaccessproceedswhen MemWait issampledlow.Theactionof MemWait maybedisabledbysoftware,seeSection10.3.Nomechanismisprovidedtoabortanaccess;if MemWait isheldhightoo long the EMI will become a contentious resource and may stall the ST20-GP6.
MemReadnotWrite
The MemReadnotWrite pin indicates if the current access is a read or a write.
BusWidth
Thissignalissampledimmediatelyafterresetanddeterminestheinitialbuswidthofallbanksafterreset.
ST20-GP6
10.2External accesses
Figure10.2showsthegenericEMIactivityduringanaccessandtheconfigurableparametersaregiven in Table10.2.
Table 10.1 BusWidth encoding
Figure 10.2 Generic access
AccessCycleTime
MemAddress
notMemCE
notMemOE
notMemBE
MemData(write)
MemData(read)
MemReadnotWrite
ST20-GP6
10.3MemWait
The MemWait pinissampledoneachprocessorclockcycleduringaccessestobanks.Incycleswhenitissampledhigh,theexternalaccessishaltedandthestrobestatedoesnotchange.MemWait suspendsthestateoftheEMIinthecycleafteritissampledhigh.Thestateremainssuspendeduntil MemWait issampledlow.AnystrobeedgesscheduledtooccurinthecycleafterMemWait issampledwillnotoccur.StrobeedgesscheduledtooccuronthesameedgeasMemWait issampledarenotaffected.Figure10.3andFigure10.4showtheextensionoftheexternalmemorycycleandthedelayingofstrobetransitions.Note,theclockshowninthefiguresistheinternalon-chipclockandisprovidedasaguidetoshowtheminimumsetuptimeof
MemWait relative to the strobes.
Note that MemWait is ignored if it is sampled high on the last cycle of the access.
Table 10.2 Parameters for generic access
ST20-GP6
Figure 10.3 Strobe activity without MemWait
Figure 10.4 Strobe activity with MemWait
Note, Strobe refers to the EMI strobe signals notMemOE ,notMemCE and notMemBE .
ST20-GP6
10.4EMI configuration registers
Thefollowingisasummaryoftheconfigurationregistersformat.Timesareprogrammedincyclesor phases: a cycle is one clock cycle, a phase is half a clock cycle.
Thereare4dataconfigurationregistersforeachoftheEMIbanks.ThebaseaddressesfortheEMIregisters is #00002000 .
EMIConfigData0Bank0-3
The EMIConfigData0Bank0-3 registerscontainconfigurationdataforeachoftheEMIbanks.Theformat of each of the EMIConfigData0 registers is shown in Table10.3.
Table 10.3 EMIConfigData0 register format - 1 per bankable 10.4 Strobe configuration
