ST20196 ,ADSL2+ UTOPIA DMT TRANSCEIVER FOR CPE APPLICATIONSFeaturesTone Equalization■ Standard Utopia level1 and 2 ATM interface■ ADSL2+ DMT modem with embedd ..
ST202BD ,5V POWERED MULTI-CHANNEL RS-232 DRIVERS AND RECEIVERSELECTRICAL CHARACTERISTICS (C - C = 0.1μF, V = 5V ± 10%, T = -40 to 85°C, unless otherwise specifie ..
ST202BDR ,5V POWERED MULTI-CHANNEL RS-232 DRIVERS AND RECEIVERSPIN CONFIGURATION PIN DESCRIPTION PlN N° SYMBOL NAME AND FUNCTIONC + Positive Terminal fo ..
ST202BN ,5V POWERED MULTI-CHANNEL RS-232 DRIVERS AND RECEIVERSST2025V POWERED MULTI-CHANNELRS-232 DRIVERS AND RECEIVERS ■ SUPPLY VOLTAGE RANGE: 4.5 TO 5.5V■ SUP ..
ST202BTR ,5V POWERED MULTI-CHANNEL RS-232 DRIVERS AND RECEIVERSAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
ST202C ,5V POWERED MULTI-CHANNEL RS-232 DRIVERS AND RECEIVERSapplicationswhere ± 12V is not available. The ST202 uses asingle 5V power supply and only four exte ..
STK7565 ,2 OUTPUT TYPE SECONDARY REGULATOR FOR OFFICE AUTOMATION EQUIPMENTA Under deve 10pmentMaximum RatingsMA'ii'tirDescription .a & Vin Tc max Tstg . Package(N) 7 " F;max ..
STK7573A , OUTPUT TYPE SECONDARY REGULATOR FOR OFFICE AUTOMATION EQIPMENT
STK7573B , OUTPUT TYPE SECONDARY REGULATOR FOR OFFICE AUTOMATION EQIPMENT
STK7575P , Advanced Power MOSFET
STK760 ,Intergrated Circuit VOLTAGE REGULATOR
STK792-110 ,Vertical Deflection Output Circuit for CTV and CRT DisplaysFeatures. Vertical deflection basic functions (output amplifier andsupply switching circuit) in a c ..
ST20196
ADSL2+ UTOPIA DMT TRANSCEIVER FOR CPE APPLICATIONS
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ST20196February 2005
1OverviewThe ST20196 is the digital component of the
ST20190 Utopia chipset. The chipset allows
equipment manufacturers to develop flexible plat-
forms showing high performance, fully leveraging
the ADSL2+ 24 Mbps wireline speed. These plat-
forms can quickly adapt to the rapidly changing re-
quirements of the emerging ADSL2+ Triple-play
market covering data, voice and video applica-
tions.
Features ADSL2+ DMT modem with embedded controller
allowing easy, straight forward integration with
external network processors Multi-standard support G.992.1 annexA,B,C (SBM/DBM) & I G.992.2 - g.lite G.992.3 annexA,B,I,J,L (extended reach),
M (double upstream) G.992.4 - g.lite.bis G.992.5 annexA,B,C,I,J,M ANSI T1.413 Issue2 ETSI TS 101 388 ADSL-over-ISDN DS bitrates above 24 Mbps and US bitrates upto
2.5 Mbps in annexM (1.2 in annexA) Designed to meet standardized and specific
operator requirements. CATII functionality with Echo canceling and
Trellis coding Advanced equalization techniques like Per
Tone Equalization Standard Utopia level1 and 2 ATM interface Parallel and serial modem control interface
(Ctrl-E) for glue-less connection to a
management entity. Supply Voltage : 3.3V and 1.2V Typical power consumption : 700mW Temperature range : I-range (-40°C to 85°C)
Applications Medium/high end routers Business routers with modular and/or multiple
WAN access Security applications Voice and data gateways Wireless access points Convergence of gateways and IP SetTopBox Home servers with storage capabilities, smart
card interfaces, unified mailboxes, …
Figure 2. Block DiagramADSL2+ UTOPIA DMT TRANSCEIVER
FOR CPE APPLICATIONS
Rev. 1
ST20196 General DescriptionThe new ADSL2+ standards will accelerate Broadband applications way beyond always-on data stream-
ing, mainly used for web-browsing and e-mailing. Internet Service Providers are exploring several ways
to increase their revenues by offering new services and applications and enlarging their customer base.
This can be realized using the large number of new features and different annexes of ADSL2+.
The ST20196 is designed in a main stream digital CMOS technology. The major building blocks are the
DMT engine including the PMD and TC layer, the ARM™ microcontroller and the different interfaces like
Utopia Level I&II, Ctrl-E, interfacing to the ST20184 and memory. The DMT engine is compliant with the
new ADSL2+ standards and supports features like diagnostics mode, enhanced power management (L2),
1 bit constellation, relocatable and modulated pilot, …
On top of the mandatory new features, the DMT engine includes several differentiating, advanced and
unique techniques like an innovative Per Tone Equalizer (PTEQ) optimizing short loop and bridge tap per-
formances and reducing the impact of RFI in ADSL2+ mode.
A highly performant echo canceller (EC) and a fully digital clock recovery scheme (TDI) further differen-
tiate the ST20190 ADSL2+ performances.
To be prepared for Triple-play applications a flexible TC-layer has been implemented.
The cached ARM™ micro-controller allows further improvement of the performances and allows fast and
easy integration with the major third party network processors. Data is exchanged over the Utopia level1
or 2 interface and the commands via the ST Ctrl-E modem control command protocol.
Processor Platform
Figure 3. Processor Platform diagram
5.1 Micro-controllerThe micro-controller is made of an ARM946™ microprocessor with 8Kbytes instruction and 8Kbytes data
caches. He is connected to 16Kbytes internal RAM and 512bytes ROM.
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ST20196
5.2 ROM and boot procedureThe ROM contains the boot sequence needed for code download at startup from UART or CTRL-E inter-
face. The use of the ROM by the ARM946™ microprocessor is defined by the state of the TROM pin dur-
ing reset.
TROM = '1': The processor boots directly from the external Flash.
TROM = '0': The processor boots from internal ROM. The communication settings for the UART are then
fixed to 38400 bauds, no parity, 8 data bits, 2 stop bits.
5.3 Memory InterfaceThe ST20196 implements a shared interface for external memories. The SDRAM and Flash I/O pins are
muxed by the EBI module
Table 2.
5.3.1 SDRAMST20196 supports SDRAM access through a SDRAM Controller, which supports 16 bit SDRAM access SDRAM sizes up to 512Mbits
The SDRAM Controller has a built in refresh timer. Refresh and access times can be modified through
firmware to support different SDRAM requirements.
All SDRAM actions are triggered at the rising edge of its clock. Timing diagrams for a burst of four 16-bit
accesses to 16-bit SDRAM show the basic behavior of the control signals.
Figure 4. SDRAM Read access (CAS Latency = 3 , Burst = 4)
ST20196
Figure 5. SDRAM Write access (CAS Latency = 3 , Burst = 4)
Figure 6. SDRAM Interface Timing
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ST20196
Table 3. Note:
- The timing values are given for best to worst case operating conditions.
- Setup and hold times for input signals are based 1.5 ns input transition time.
- The output delays are based on 25pF loading capacitance.
5.3.2 FlashST20196 Flash interface supports 8-bit Flash access Flash sizes up to 8Mbit (1M x 8bit)
Figure 7. Flash Read Timing
ST20196
Figure 8. Flash Write Timing
Figure 9. Flash Chip Select TimingFlash Timing parameters, programmable to some extent by steps of clock cycles (typically 35.328MHz).
Table 4. Flash Timing parameters
5.4 CTRL-EThe Ctrl-E interface controller is a generic mailbox system to exchange control and status messages be-
tween ST-20196 (over AHB bus) and an external controller (over Ctrl-E interface). It consists of a mailbox
and a physical interface. Although the two 8-bit command registers are intended for use in one direction
(ARM™ to Ctrl-E or Ctrl-E to ARM™) they are fully accessible in read and write from both sides. So it is
up to the software to guarantee consistency of register values. Two control registers only accessible by
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ST20196the ARM™ core allow configuration of the status update mechanism and of interrupt generation.
The Ctrl-E physical interface between the mailbox and an external controller is implemented as a generic
parallel bus interface. The Ctrl-E Mailbox and its interfaces are all running synchronous to the AHB clock.
Figure 10. CTRL-E Interface Controller principle
5.4.1 CTRL-E Mail Box The Ctrl-E Mailbox occupies a 512 byte memory map accessible by the Ctrl-E physical interface and by
the AHB bus. The mailbox memory map is given in the Table below. Two addresses are shown in the
memory map: CtrlE A[8:0] as generated by the Ctrl-E physical interface and the LSBs of the AHB address
bus AhbAddress[8:0]. The two configuration registers Ctrl-E Control and Ctrl-E Interrupt are only accessi-
ble by the AHB bus.
The Mailbox interrupt controller generates two interrupts: an internal interrupt towards the ARM™ interrupt
controller (Ctrl-E IntArm), and an external interrupt towards the external controller (Ctrl-E IntExt). Depend-
ing on the configuration an interrupt-based or polling-based communication protocol can be implemented.
Table 5. CTRL-E Mail Box Memory Map
ST20196
5.4.2 CTRL-E SemaphoreA simple semaphore mechanism is provided to allow control of the data consistency of the Ctrl-E Data
Buffer and Command registers. If there would be unlimited accesses to all mailbox addresses over the
two interfaces by the two independent controllers there would be no possibility to implement a semaphore
mechanism in software. Therefore one mailbox address is defined as a two-bit semaphore register pro-
tected by control logic to prevent illegal write accesses to this register.
Before a read/write access by one of the two interfaces (AHB or Ctrl-E) this interface should perform a 'P-
operation' on the semaphore. After a read or write of the data buffer, the interface should do a 'V-operation'
releasing the semaphore. P and V operations are performed by write and read accesses to the sema-
phore register. The semaphore will be updated as shown in Table 10.
Each semaphore operation (P or V) consists of two consecutive actions: Write the correct value to the semaphore address (see Table below) Read the value in the semaphore address.
If the value read is different from the value written the P or V operation was not successful and should be
tried again.
Table 6. Semaphore P and V operationsThe data buffers can be accessed without using the semaphore mechanism if data consistency is guar-
anteed in another way. If other values are written to the semaphore address than the values listed, the
write will not be performed.
5.4.3 CTRL-E PHYSICAL INTERFACEPhysical interface implements a generic parallel interface with 9 bit Address and 8 bit Data bus. Two par-
allel bus modes are defined to support both Motorola-compatible and Intel-compatible timing and control
signals.
This interface specification is compliant to ATM Forum Physical Layer Control Parallel interface.
The parallel bus mode section is done with the C_Mode input pin:
Table 7. The two parallel bus modes differ only in the definition of 3 control signals: Bus mode 0 provides a read/write selector, a data strobe and a ready acknowledge. Bus mode 1 provides a read strobe, a write strobe and a ready acknowledge.
The signal definition is shown in following table:
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ST20196
Table 8. All input signals are registered internally using the AHB clock. But there is no need to synchronize the in-
terface to the main clock. Due to this fact, the interface will behave faster in case of AHB higher clock
frequency. All timings are preliminary.
ST20196
5.4.4 CTRL-E Write Access
Figure 11. CTRL-E Write Access Timing diagram
Table 9. CTRL-E Write Access Timing (*): This is a minimal value. In case c_notDtAck(C_notRdy) is used to synchronize the process, one should wait until c_notDtAck(C_notRdy)
becomes low (t10)
(1): Timings fully defined by the CTRL-E Master: these timings are considered as necessary to make the interface work
(2): Timings fully dependable of the CTRL-E slave
(3): 10ns is added to the theoretical value in order to include the input and output delays
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ST20196
5.4.5 Ctrl-E Read access
Figure 12. Ctrl-E Read Access Timing diagram
Table 10. CTRL-E Read Access Timing(1): Timings fully defined by the CTRL-E Master: these timings are considered as necessary to make the interface work
(2): Timings fully dependable of the CTRL-E slave
(3): 10ns was added to the theoretical value in order to include the input and output delays.
ST20196
5.5 PeripheralsST20196 processor platform includes different peripherals located on a second level bus, connected to
the main AHB bus through a bridge.
5.5.1 Watchdog The watchdog is actually a 32-bit real-time counter configured as watchdog. It generates both an interrupt
signal sent to the interrupt controllers and a reset signal sent to the reset controller.
5.5.2 Real time countersThere are 2 general-purpose 32-bit real time counters. It consists of single 32-bit down-counters that gen-
erate interrupts if the counters reach zero.
5.5.3 Interrupt controllersThere are 2 interrupt controllers. One is connected with the ARM™ IRQ and one with the ARM™ FIQ. All
ST-20196 interrupts are connected at the same time to both controllers to allow SW to decide which ones
to handle as fast and which to handle as slow interrupts.
5.5.4 UARTThere is one UART for RS232 interfacing to external systems. The UART is capable of full-duplex data
transfer at user defined baud rates. Most common baud rates are supported. FIFOs with configurable
depth store the received and the data to be transmitted. The UART offers parity checking, stop bit length
control and hardware handshake.
When booting from the internal ROM, the communication settings are: 38400 bauds, no parity, 8 data bits,
2 stop bits.
5.5.5 GPIO controllerThere is 1 GPIO controller driving 8 external GPIO's.
Clocking scheme
Figure 13. Clocking schemeInternal clocks are derived from the MCLK input clock via a PLL.
DMT platformThe following section essentially describes the sequence of actions performed by the DMT platform.
7.1 DMT-AFE (ST20184)The DMT-AFE module is taking care of the interface with the analog front end device. The module is sup-
porting only the ST20184 device.
In the receive direction, the DMT-AFE module gets the signal multiplexed on 10 inputs and transmit it with
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ST20196a first decimation to the DMT-PMD module.
In the transmit direction, the DMT-AFE module transfers the signal multiplexed on 4 output signals.
The module includes test loop-backs.
7.1.1 DMT-AFE Interface signals
Figure 14.
Table 11.
7.1.2 DMT-AFE Interface timing
Figure 15. AFE Receive data bus
Figure 16. AFE Transmit data bus
ST20196
Figure 17. AFE Control Write protocolThe write protocol is composed of 5 parts, at the rate defined by CLWD: 1 leading start bit 4 bits representing an address, MSB first 1 logic zero bit to indicate it is a write access 12 bits of data, MSB first 16 stop bits
Figure 18. AFE Control Read protocolThe read protocol is composed of 5 parts, at the rate defined by CLWD: 1 leading start bit on AFE_CTR_OUT 4 bits representing an address, MSB first, on AFE_CTR_OUT 1 logic one bit to indicate it is a read access, on AFE_CTR_OUT 12 bits, listen state on AFE_CTR_OUT, data MSB first on AFE_CTR_IN 16 stop bits on AFE_CTR_OUT
Table 12. Note: The timing values are given for best to worst case operating conditions. Setup and hold times for input signals are based 1.5 ns input transition time. The output delays are based on 25pF loading capacitance.
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ST20196
7.2 DMT-PMD
Figure 19.
7.2.1 Time Domain Processing (TDP)The TDP contains in the receive direction: time domain interpolator (TDI), IIR filters, decimators and echo
suppression. The TDI receives 8.8 MHz (17.6 MHz for ADSL+) samples and performs a Lagrange inter-
polation. The Decimators receives then the interpolated samples and reduces this rate to 2.2 MHz (4.4
MHz in ADSL+).
In the transmit direction, the TDP includes: side-lobe filtering, clipping, delay equalization, interpolation
and time domain interpolation. The side-lobe filtering and delay equalization are implemented by IIR filters,
reducing the effect of echo in FDM systems. Clipping is a statistical process limiting the amplitude of the
output signal, optimizing the dynamic range of the AFE. The interpolator receives data at 2.2 MHz and
generates samples at a rate of 8.8 MHz. The transmitted samples are interpolated.
The echo is computed via a 256 taps FIR.
7.2.2 Frequency Domain Processing (FDP)In Rx path, the module is based on programmable DSP and FFT module working as a coprocessor.
The instruction set enables functions like FFT, per tone equalizer (PTEQ), Scaling, and frequency equal-
ization (FEQ). This block implements the core of the DMT algorithm as specified in ANSI T1.413.
The 512-points FFT (1024 points in ADSL+) transforms the time-domain DMT symbol into a frequency
domain representation which can be further decoded by the subsequent demapping stages. After FFT and
PTEQ blocks - an essentially ICI (Inter Carrier Interference) - free carrier information stream has been ob-
tained.
This stream is still affected by carrier specific channel distortion resulting in an attenuation of the signal
amplitude and a rotation of the signal phase. To compensate for these effects, the FFT+PTEQ is followed
by a frequency domain equalizer (FEQ). In case of Annex C mode, 2 different FEQ coefficient tables are
used for FEXT and NEXT.
In the TX path, the IFFT transforms the DMT symbol generated in the frequency domain by the Mapper
into a time domain representation. The IFFT block is preceded by a fine tune gain. In case of Annex C
mode, 2 different FTG coefficient tables are used for FEXT and NEXT.
7.2.3 Constellation Domain Processing (CDP): (De)Mapper, Monitor, Trellis (De)CodingThe Demapper converts the constellation points computed by the FDP to a list of bits. This essentially con-
sists in identifying a point in a 2D QAM constellation plane. The Demapper supports trellis coded demod-
ulation and provides a Viterbi maximum likelihood estimator. When the trellis is active, the Demapper
receives an indication for the most likely constellation subset to be used.
In the transmit direction, the Mapper performs the inverse operation, mapping a block of bits into one con-
stellation point (in a complex x+jy representation) which is passed to the IFFT block. The Trellis Encoder
ST20196 generates redundant bits to improve the robustness of the transmission, using a 4-Dimensional Trellis
Coded Modulation scheme.
The Monitor computes error parameters for carriers specified in the Demapper process. Those parame-
ters can be used for updates of adaptive filters coefficients, clock phase adjustments, error detection, etc.
A series of values is constantly monitored, such as signal power, pilot phase deviations, symbol erasures
generation, loss of frame, etc.
A special Reverb-Segue detector allows an easy detection of L2-exit sequence in ADSL2(+) applications.
In case of Annex C mode, 2 different (De)Mapper tables are used for FEXT and NEXT, as 2 different Mon-
itoring memories for FEXT and NEXT.
7.2.4 FIR coefficients training and trackingFEQ coefficients are trained and kept up-to-date by a specific block reading the carrier errors coming out
of the monitoring process.
The Echo-Canceller and PTEQ FIR coefficients are updates are in frequency domain via a dedicated DSP
based on a floating point data-path.
7.2.5 Clock recoveryA Digital PLL module receives a metric for the phase error of the pilot tone. In general, the clock frequen-
cies at CO and CPE do not match exactly. The phase error is filtered and integrated by a low pass filter,
yielding an estimation of the frequency offset. The phase error can be compensated in the time domain
by interpolating samples
7.2.6 DMT Symbol Timing Unit (DSTU)The DSTU interfaces with various modules. It consists of a real time and a scheduler module. The real
time unit generates a time base for the DMT symbols (sample counter), super-frames (symbol counter)
and hyper-frames (sync counter). The time bases can be modified by various control features. They are
continuously fine tuned by the DPLL module. The DSTU schedulers execute a program, controlled by pro-
gram op-codes and a set of variables, the most important of which are real time counters. The transmit
and receive sequencers are completely independent and run different programs. An independent set of
variables is assigned to each of them. The sequencer programs can be updated in real time.
In case of Annex C mode, the DSTU take care also of the hyper-frame synchronization, the table switch
for FEXT and NEXT period and the control of the dummy bits insertion/extraction.
7.3 DMT-TC
Figure 20.
