ST1S10BPHR ,Monolithic synchronous step-down regulatorFeatures■ Step-down current mode PWM regulator■ Output voltage adjustable from 0.8 V■ Input voltage ..
ST1S10PHR ,Monolithic synchronous step-down regulatorElectrical characteristics . . . . 8Table 6. Power SO-8 (exposed pad) mechanical data . . ..
ST1S10PUR ,Monolithic synchronous step-down regulatorST1S103 A, 900 kHz, monolithic synchronous step-down regulator ICDatasheet − production data
ST1S12GR ,Synchronous rectification with inhibit, 0.7 A, 1.7 MHz adjustable, step-down switching regulatorFeatures■ Step-down current mode PWM (1.7 MHz) DC-DC converter■ 3% DC output voltage tolerance■ Syn ..
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ST2001HI ,HIGH VOLTAGE FAST-SWITCHING NPN POWER TRANSISTORST2001HI®HIGH VOLTAGE FAST-SWITCHINGNPN POWER TRANSISTOR■ NEW SERIES, ENHANCED PERFORMANCE■ FULLY I ..
STK7561A , OUTPUT TYPE SECONDARY REGULATOR FOR OFFICE AUTOMATION EQIPMENT
STK7561F , OUTPUT TYPE SECONDARY REGULATOR FOR OFFICE AUTOMATION EQIPMENT
STK7562J , OUTPUT TYPE SECONDARY REGULATOR FOR OFFICE AUTOMATION EQIPMENT
STK7563 ,2 OUTPUT TYPE SECONDARY REGULATOR FOR OFFICE AUTOMATION EQUIPMENTA Under deve 10pmentMaximum RatingsMA'ii'tirDescription .a & Vin Tc max Tstg . Package(N) 7 " F;max ..
STK7563F , OUTPUT TYPE SECONDARY REGULATOR FOR OFFICE AUTOMATION EQIPMENT
STK7563G ,STK7563G
ST1S10-ST1S10BPHR-ST1S10PHR-ST1S10PUR
Monolithic synchronous step-down regulator
June 2012 Doc ID 13844 Rev 5 1/29
ST1S103 A, 900 kHz, monolithic synchronous step-down regulator IC
Datasheet − production data
Features Step-down current mode PWM regulator Output voltage adjustable from 0.8 V Input voltage from 2.5 V up to 18 V 2% DC output voltage tolerance Synchronous rectification Inhibit function Synchronizable switching frequency from 400
kHz up to 1.2 MHz Internal soft start Dynamic short circuit protection Typical efficiency: 90% 3 A output current capability Stand-by supply current: max 6 µA over
temperature range Operative junction temp: from - 40 °C to 125 °C
Applications Consumer STB, DVD, DVD recorders, TV , VCR, car
audio, LCD monitors Networking XDSL, modems, DC-DC modules Computer Optical storage, HD drivers, printers,
audio/graphic cards Industrial and security Battery chargers, DC-DC converters, PLD,
PLA, FPGA, LED drivers
DescriptionThe ST1S10 is a high efficiency step-down PWM
current mode switching regulator capable of
providing up to 3 A of output current. The device
operates with an input supply range from 2.5 V to
18 V and provides an adjustable output voltage
from 0.8 V (VFB ) to 0.85*V IN_SW [V OUT = FB *(1+R1/R2)]. It operates either at a 900 kHz
fixed frequency or can be synchronized to an
external clock (from 400 kHz to 1.2 MHz). The
high switching frequency allows the use of tiny
SMD external components, while the integrated
synchronous rectifier eliminates the need for a
Schottky diode. The ST1S10 provides excellent
transient response, and is fully protected against
thermal overheating, switching over-current and
output short circuit.
The ST1S10 is the ideal choice for point-of-load
regulators or LDO pre-regulation.
Table 1. Device summary
Contents ST1S102/29 Doc ID 13844 Rev 5
Contents Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.2 External components selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.2.1 Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.3 Output capacitor (V OUT > 2.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.4 Output capacitor (0.8 V < V OUT < 2.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.5 Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.6 Inductor (V OUT > 2.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.7 Inductor (0.8 V < V OUT < 2.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.8 Function operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.8.1 Sync operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.8.2 Inhibit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.8.3 OCP (overcurrent protection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.8.4 SCP (short circuit protection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.8.5 SCP and OCP operation with high capacitive load . . . . . . . . . . . . . . . . 14
Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166.1 Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
ST1S10 List of tables
Doc ID 13844 Rev 5 3/29
List of tables
Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Power SO-8 (exposed pad) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 7. Power SO-8 (exposed pad) tape and reel mechanical data . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 8. DFN8 (4X4) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 9. DFN8 (4x4)tape and reel mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 10. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
List of figures ST1S10
4/29 Doc ID 13844 Rev 5
List of figures
Figure 1. Typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Pin connections (top view for PowerSO-8, bottom view for DFN8) . . . . . . . . . . . . . . . . . . . 6
Figure 3. Application schematic for heavy capacitive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 4. Application schematic for low output voltage (VOUT < 2.5 V) and 2.5 V < VIN < 8 V . . . . . 15
Figure 5. Application schematic for low output voltage (VOUT < 2.5 V) and 8 V < VIN < 16 V . . . . . . 15
Figure 6. PCB layout suggestion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 7. PCB layout suggestion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 8. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 9. Voltage feedback vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 10. Oscillator frequency vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 11. Max duty cycle vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12. Inhibit threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13. Reference line regulation vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 14. Reference load regulation vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 15. ON mode quiescent current vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 16. Shutdown mode quiescent current vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 17. PMOS ON resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 18. NMOS ON resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 19. Efficiency vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 20. Efficiency vs. output current@Vout = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 21. Efficiency vs. output current@Vout = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 22. Efficiency vs. output current@Vout = 12 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 23. Power SO-8 (exposed pad) dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 24. Power SO-8 (exposed pad) recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 25. Power SO-8 (exposed pad) tape and reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 26. DFN8 (4x4) dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 27. DFN8 (4x4)tape and reel dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
ST1S10 Application circuit
Doc ID 13844 Rev 5 5/29
1 Application circuit
Figure 1. Typical application circuit
Pin configuration ST1S10
6/29 Doc ID 13844 Rev 5 Pin configuration
Figure 2. Pin connections (top view for PowerSO-8, bottom view for DFN8)
Table 2. Pin description
ST1S10 Maximum ratings
Doc ID 13844 Rev 5 7/29
3 Maximum ratings
Note: Absolute maximum ratings are the values beyond which damage to the device may occur.
Functional operation under these conditions is not implied.
Table 3. Absolute maximum ratings
Table 4. Thermal data
Electrical characteristics ST1S10
8/29 Doc ID 13844 Rev 5
4 Electrical characteristics
VIN = VIN_SW = VIN_A = VINH = 12 V, VSYNC = GND, VOUT = 5 V, IOUT = 10 mA, CIN = 4.7 µF
+0.1 µF , COUT = 22 µF , L1 = 3.3 µH, TJ = -40 to 125°C (Unless otherwise specified, refer to
the typical application circuit. Typical values assume TJ = 25°C).
Table 5. Electrical characteristics
ST1S10 Electrical characteristics
Doc ID 13844 Rev 5 9/29 Guaranteed by design, but not tested in production. See output voltage selection paragraph 5.5 for maximum duty cycle conditions.
Table 5. Electrical characteristics (continued)
Application information ST1S10
10/29 Doc ID 13844 Rev 5
5 Application information
5.1 Description
The ST1S10 is a high efficiency synchronous step-down DC-DC converter with inhibit
function. It provides up to 3 A over an input voltage range of 2.5 V to 18 V , and the output
voltage can be adjusted from 0.8 V up to 85% of the input voltage level. The synchronous
rectification removes the need for an external Schottky diode and allows higher efficiency
even at very low output voltages.
A high internal switching frequency (0.9 MHz) allows the use of tiny surface-mount
components, as well as a resistor divider to set the output voltage value. In typical
application conditions, only an inductor and 3 capacitors are required for proper operation.
The device can operate in PWM mode with a fixed frequency or synchronized to an external
frequency through the SYNC pin. The current mode PWM architecture and stable operation
with low ESR SMD ceramic capacitors results in low, predictable output ripple. No external
compensation is needed.
To maximize power conversion efficiency, the ST1S10 works in pulse skipping mode at light
load conditions and automatically switches to PWM mode when the output current
increases.
The ST1S10 is equipped with thermal shut down protection activated at 150 °C (typ.).
Cycle-by-cycle short circuit protection provides protection against shorted outputs for the
application and the regulator. An internal soft start for start-up current limiting and power ON
delay of 275 µs (typ.) helps to reduce inrush current during start-up.
5.2 External components selection
5.2.1 Input capacitor
The ST1S10 features two VIN pins: VIN_SW for the power supply input voltage where the
switching peak current is drawn, and VIN_A to supply the ST1S10 internal circuitry and
drivers.
The VIN_SW input capacitor reduces the current peaks drawn from the input power supply
and reduces switching noise in the IC. A high power supply source impedance requires
larger input capacitance.
For the VIN_SW input capacitor the RMS current rating is a critical parameter that must be
higher than the RMS input current. The maximum RMS input current can be calculated
using the following equation:
Equation 1
where η is the expected system efficiency, D is the duty cycle and IO is the output DC
current. The duty cycle can be derived using the equation:
ST1S10 Application information
Doc ID 13844 Rev 5 11/29
Equation 2
D = (VOUT + VF) / (VIN-VSW)
where VF is the voltage drop across the internal NMOS, and VSW represents the voltage
drop across the internal PDMOS. The minimum duty cycle (at VIN_max) and the maximum
duty cycle (at VIN_min) should be considered in order to determine the max IRMS flowing
through the input capacitor.
A minimum value of 4.7 µF for the VIN_SW and a 0.1 µF ceramic capacitor for the VIN_A are
suitable in most application conditions. A 10 µF or higher ceramic capacitor for the VIN_SW
and a 1 µF or higher for the VIN_A are recommended in cases of higher power supply source
impedance or where long wires are needed between the power supply source and the VIN
pins. The above higher input capacitor values are also recommended in cases where an
output capacitive load is present (47 µF < CLOAD < 100 µF), which could impact the
switching peak current drawn from the input capacitor during the start-up transient.
In cases of very high output capacitive loads (CLOAD > 100 µF), all input/output capacitor
values shall be modified as described in the OCP and SCP operation section 5.8.5 of this
document.
The input ceramic capacitors should have a voltage rating in the range of 1.5 times the
maximum input voltage and be located as close as possible to VIN pins.
5.3 Output capacitor (V OUT > 2.5 V)
The most important parameters for the output capacitor are the capacitance, the ESR and
the voltage rating. The capacitance and the ESR affect the control loop stability, the output
ripple voltage and transient response of the regulator.
The ripple due to the capacitance can be calculated with the following equation:
Equation 3
VRIPPLE(C) = (0.125 x ∆ISW) / (FS x COUT)
where FS is the PWM switching frequency and ∆ISW is the inductor peak-to-peak switching
current, which can be calculated as:
Equation 4
∆ISW = [(VIN - VOUT) / (FS x L)] x D
where D is the duty cycle.
The ripple due to the ESR is given by:
Equation 5
VRIPPLE(ESR) = ∆ISW x ESR
The equations above can be used to define the capacitor selection range, but final values
should be verified by testing an evaluation circuit.
Lower ESR ceramic capacitors are usually recommended to reduce the output ripple
voltage. Capacitors with higher voltage ratings have lower ESR values, resulting in lower
output ripple voltage.
Application information ST1S10
12/29 Doc ID 13844 Rev 5
Also, the capacitor ESL value impacts the output ripple voltage, but ceramic capacitors
usually have very low ESL, making ripple voltages due to the ESL negligible. In order to
reduce ripple voltages due to the parasitic inductive effect, the output capacitor connection
paths should be kept as short as possible.
The ST1S10 has been designed to perform best with ceramic capacitors. Under typical
application conditions a minimum ceramic capacitor value of 22 µF is recommended on the
output, but higher values are suitable considering that the control loop has been designed to
work properly with a natural output LC frequency provided by a 3.3 µH inductor and 22 µF
output capacitor. If the high capacitive load application circuit shown in Figure 3 is used, a
47 µF (or 2 x 22 µF capacitors in parallel) could be needed as described in the OCP and
SCP operation Section 5.8.5: SCP and OCP operation with high capacitive load. of this
document.
The use of ceramic capacitors with voltage ratings in the range of 1.5 times the maximum
output voltage is recommended.
5.4 Output capacitor (0.8 V < V OUT < 2.5 V)
For applications with lower output voltage levels (Vout < 2.5 V) the output capacitance and
inductor values should be selected in a way that improves the DC-DC control loop behavior.
In this output condition two cases must be considered: VIN > 8 V and VIN < 8 V.
For VIN < 8 V the use of 2 x 22 µF capacitors in parallel to the output is recommended, as
shown in Figure 4.
For VIN > 8 V, a 100 µF electrolytic capacitor with ESR < 0.1 Ω should be added in parallel to
the 2 x 22 µF output capacitors as shown in Figure 5.
5.5 Output voltage selection
The output voltage can be adjusted from 0.8 V up to 85% of the input voltage level by
connecting a resistor divider (see R1 and R2 in the typical application circuit) between the
output and the VFB pin. A resistor divider with R2 in the range of 20 kΩ is a suitable
compromise in terms of current consumption. Once the R2 value is selected, R1 can be
calculated using the following equation:
Equation 6
R1 = R2 x (VOUT - VFB) / VFB
where VFB = 0.8 V (typ.).
Lower values are suitable as well, but will increase current consumption. Be aware that duty
cycle must be kept below 85% at all application conditions, so that:
Equation 7
D = (VOUT + VF) / (VIN-VSW) < 0.85
where VF is the voltage drop across the internal NMOS, and VSW represents the voltage
drop across the internal PDMOS.
Note that once the output current is fixed, higher VOUT levels increase the power dissipation
of the device leading to an increase in the operating junction temperature. It is
ST1S10 Application information
Doc ID 13844 Rev 5 13/29
recommended to select a VOUT level which maintains the junction temperature below the
thermal shut-down protection threshold (150°C typ.) at the rated output current. The
following equation can be used to calculate the junction temperature (TJ):
Equation 8
TJ = {[VOUT x IOUT x RthJA x (1-η )] / η } +TAMB
where RthJA is the junction-to-ambient thermal resistance, η is the efficiency at the rated IOUT
current and TAMB is the ambient temperature.
To ensure safe operating conditions the application should be designed to keep TJ < 140°C.
5.6 Inductor (V OUT > 2.5 V)
The inductor value fixes the ripple current flowing through output capacitor and switching
peak current. The ripple current should be kept in the range of 20-40% of IOUT_MAX (for
example it is 0.6 - 1.2 A at IOUT = 3 A). The approximate inductor value can be obtained with
the following equation:
Equation 9
L = [(VIN - VOUT) / ∆ISW] x TON
where TON is the ON time of the internal switch, given by:
TON = D/FS
The inductor should be selected with saturation current (ISAT) equal to or higher than the
inductor peak current, which can be calculated with the following equation:
Equation 10
IPK = IO + (∆ISW/2), ISAT ≥ IPK
The inductor peak current must be designed so that it does not exceed the switching current
limit.
5.7 Inductor (0.8 V < V OUT < 2.5 V)
For applications with lower output voltage levels (Vout < 2.5 V) the description in the previous
section is still valid but it is recommended to keep the inductor values in a range from 1µH to
2.2 µH in order to improve the DC-DC control loop behavior, and increase the output
capacitance depending on the VIN level as shown in the Figure 4 and Figure 5. In most
application conditions a 2.2 µH inductor is the best compromise between DC-DC control
loop behavior and output voltage ripple.
5.8 Function operation
5.8.1 Sync operation
The ST1S10 operates at a fixed frequency or can be synchronized to an external frequency
with the SYNC pin. The ST1S10 switches at a frequency of 900 kHz when the SYNC pin is
connected to ground, and can synchronize the switching frequency between 400 kHz to 1.2
Application information ST1S10
14/29 Doc ID 13844 Rev 5
MHz from an external clock applied to the SYNC pin. When the SYNC feature is not used,
this pin must be connected to ground with a path as short as possible to avoid any possible
noise injected in the SYNC internal circuitry.
5.8.2 Inhibit function
The inhibit pin can be used to turn OFF the regulator when pulled down, thus drastically
reducing the current consumption down to less than 6 µA. When the inhibit feature is not
used, this pin must be tied to VIN to keep the regulator output ON at all times. T o ensure
proper operation, the signal source used to drive the inhibit pin must be able to swing above
and below the specified thresholds listed in the electrical characteristics section under VINH.
Any slew rate can be used to drive the inhibit pin.
5.8.3 OCP (overcurrent protection)
The ST1S10 DC-DC converter is equipped with a switch overcurrent protection. In order to
provide protection for the application and the internal power switches and bonding wires, the
device goes into a shutdown state if the switch current limit is reached and is kept in this
condition for the TOFF period (TOFF(OCP) = 135 µs typ.) and turns on again for the TON period
(TON(OCP) = 22 µs typ.) under typical application conditions. This operation is repeated cycle
by cycle. Normal operation is resumed when no over-current is detected.
5.8.4 SCP (short circuit protection)
In order to protect the entire application and reduce the total power dissipation during an
overload or an output short circuit condition, the device is equipped with dynamic short
circuit protection which works by internally monitoring the VFB (feedback voltage).
In the event of an overload or output short circuit, if the VOUT voltage is reduced causing the
feedback voltage (VFB) to drop below 0.3 V (typ.), the device goes into shutdown for the
TOFF time (TOFF(SCP) = 288 µs typ.) and turns on again for the TON period (TON(SCP) = 130
µs typ.). This operation is repeated cycle by cycle, and normal operation is resumed when
no overload is detected (VFB > 0.3 V typ.) for the full TON period.
This dynamic operation can greatly reduce the power dissipation in overload conditions,
while still ensuring excellent power-on startup in most conditions.
5.8.5 SCP and OCP operation with high capacitive load
Thanks to the OCP and SCP circuit, ST1S10 is strongly protected against damage from
short circuit and overload.
However, a highly capacitive load on the output may cause difficulties during start-up. This
can be resolved by using the modified application circuit shown in Figure 3, in which a
minimum of 10 µF for C1 and a 4.7 µF ceramic capacitor for C3 are used. Moreover, for
CLOAD > 100 µF, it is necessary to add the C4 capacitor in parallel to the upper voltage
divider resistor (R1) as shown in Figure 3. The recommended value for C4 is 4.7 nF.
Note that C4 may impact the control loop response and should be added only when a
capacitive load higher than 100 µF is continuously present. If the high capacitive load is
variable or not present at all times, in addition to C4 an increase in the output ceramic
capacitor C2 from 22 µF to 47 µF (or 2 x 22 µF capacitors in parallel) is recommended. Also
in this case it is suggested to further increase the input capacitors to a minimum of 10 µF for
C1 and a 4.7 µF ceramic capacitor for C3 as shown in Figure 3.
ST1S10 Application information
Doc ID 13844 Rev 5 15/29
(*) see OCP and SCP descriptions for C2 and C4 selection.
Figure 3. Application schematic for heavy capacitive load
Figure 4. Application schematic for low output voltage (V OUT < 2.5 V) and 2.5 V < VIN < 8 V
Figure 5. Application schematic for low output voltage (VOUT < 2.5 V) and 8 V < VIN < 16 V
