ST10F269 Fast Delivery |IC PHOENIX CO.,LIMITED

ST10F269 ,16-BIT MCU SINGLE VOLTAGE SUPPLYST10F26916-BIT MCU WITH MAC UNIT, 256K BYTE FLASH MEMORY AND 12K BYTE RAMPRELIMINARY DATA■HIGH PER ..
ST10F269-DP ,16-BIT MCU SINGLE VOLTAGE SUPPLYST10F26916-BIT MCU WITH MAC UNIT, 256K BYTE FLASH MEMORY AND 12K BYTE RAMPRELIMINARY DATA■HIGH PER ..
ST10F269-DP ,16-BIT MCU SINGLE VOLTAGE SUPPLYTABLE OF CONTENTS ..
ST10F269Z2Q3 ,16-BIT MCU WITH MAC UNIT, 256K BYTE FLASH MEMORY AND 12K BYTE RAMTABLE OF CONTENTS ..
ST10F273M-4Q3 ,16-bit MCU with 512 Kbyte Flash memory and 36 Kbyte RAMFunctional description . . . . . . . 275.2.1 Structure 275.2.2 Module structure . ..
ST10F273M-4T3 ,16-bit MCU with 512 Kbyte Flash memory and 36 Kbyte RAMFeatures■ High performance 16-bit CPU with DSP functions– 50ns instruction cycle time at 40 MHz max ..
STK460 , 2 POWER 2 CHANNEL 10 to 30W min AF POWER AMP
STK465 ,Thick Film Hybrid IC(2 Power 2 Channel 10 to 30 W, AF Power AMP)
STK465# ,Thick Film Hybrid IC(2 Power 2 Channel 10 to 30 W, AF Power AMP)
STK4773 ,2-Channel 10 to 50W Min AF Power AMPFeaturesI STK5321 STK5322 STK5324Output 1: 9.5i0.1V (1.6A) 9.5i0.1V (1.6A) 12.0iO.1V (1.6A) 1Output ..
STK4793 ,2-Channel 10 to 50W Min AF Power AMPFeaturesI STK5321Output 1: 9.5i0.1V (1.6A)Output 2: 12.0i0.3V (2.5A)STK5326Output l: 12.0i0.1V (1.6 ..
STK4843 ,2-Channel 10 To 50W Min AF Power AMP(Dual Supply)FeaturesI STK5321 STK5322 STK5324Output 1: 9.5i0.1V (1.6A) 9.5i0.1V (1.6A) 12.0iO.1V (1.6A) 1Output ..

ST10F269
16-BIT MCU SINGLE VOLTAGE SUPPLY
1/160
ST10F269
June 2002 HIGH PERFORMANCE 40MHz CPU WITH DSP
FUNCTION
– 16-BIT CPU WITH 4-STAGE PIPELINE
– 50ns INSTRUCTION CYCLE TIME AT 40MHz MAX
CPU CLOCK
– MULTIPLY/ACCUMULATE UNIT (MAC) 16 x 16-BIT
MULTIPLICATION, 40-BIT ACCUMULATOR
– REPEAT UNIT
– ENHANCED BOOLEAN BIT MANIPULATION FA-
CILITIES
– ADDITIONAL INSTRUCTIONS TO SUPPORT HLL
AND OPERATING SYSTEMS
– SINGLE-CYCLE CONTEXT SWITCHING SUP-
PORT MEMORY ORGANIZATION
– 256K BYTE ON-CHIP FLASH MEMORY SINGLE
VOLTAGE WITH ERASE/PROGRAM CONTROLLER.
– 100K ERASING/PROGRAMMING CYCLES.
– UP TO 16M BYTE LINEAR ADDRESS SPACE FOR
CODE AND DATA (5M BYTES WITH CAN)
– 2K BYTE ON-CHIP INTERNAL RAM (IRAM)
– 10K BYTE ON-CHIP EXTENSION RAM (XRAM) FAST AND FLEXIBLE BUS
– PROGRAMMABLE EXTERNAL BUS CHARACTE-
RISTICS FOR DIFFERENT ADDRESS RANGES
– 8-BIT OR 16-BIT EXTERNAL DATA BUS
– MULTIPLEXED OR DEMULTIPLEXED EXTERNAL
ADDRESS/DATA BUSES
– FIVE PROGRAMMABLE CHIP-SELECT SIGNALS
– HOLD-ACKNOWLEDGE BUS ARBITRATION SUP-
PORT INTERRUPT
– 8-CHANNEL PERIPHERAL EVENT CONTROLLER
FOR SINGLE CYCLE INTERRUPT DRIVEN DATA
TRANSFER
– 16-PRIORITY-LEVEL INTERRUPT SYSTEM WITH
56 SOURCES, SAMPLING RATE DOWN TO 25ns TIMERS
– TWO MULTI-FUNCTIONAL GENERAL PURPOSE
TIMER UNITS WITH 5 TIMERS TWO 16-CHANNEL CAPTURE / COMPARE UNITS A/D CONVERTER
– 16-CHANNEL 10-BIT
– 4.85μs CONVERSION TIME AT 40MHz CPU CLOCK 4-CHANNEL PWM UNIT SERIAL CHANNELS
– SYNCHRONOUS/ ASYNCHRONOUS SERIAL
CHANNEL
– HIGH-SPEED SYNCHRONOUS CHANNEL TWO CAN 2.0B INTERFACES OPERATING ON ONE
OR TWO CAN BUSSES (30 OR 2x15 MESSAGE
OBJECTS) FAIL-SAFE PROTECTION
– PROGRAMMABLE WATCHDOG TIMER
– OSCILLATOR WATCHDOG ON-CHIP BOOTSTRAP LOADER CLOCK GENERATION
– ON-CHIP PLL
– DIRECT OR PRESCALED CLOCK INPUT REAL TIME CLOCK UP TO 111 GENERAL PURPOSE I/O LINES
– INDIVIDUALLY PROGRAMMABLE AS INPUT,
OUTPUT OR SPECIAL FUNCTION
– PROGRAMMABLE THRESHOLD (HYSTERESIS) IDLE AND POWER DOWN MODES SINGLE VOLTAGE SUPPL Y: 5V ±10% (EMBEDDED
REGULATOR FOR 3.3 V CORE SUPPLY). TEMPERATURE RANGE: -40 +125°C 144-PIN PQFP PACKAGE
16-BIT MCU WITH MAC UNIT, 256K BYTE FLASH MEMORY AND 12K BYTE RAM
PRELIMINARY DATA
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TABLE OF CONTENTS PAGE
1 - INTRODUCTION ........................................................................................................ 6
2 - PIN DATA ................................................................................................................... 7
3 - FUNCTIONAL DESCRIPTION ................................................................................... 13
4 - MEMORY ORGANIZATION ....................................................................................... 14
5 - INTERNAL FLASH MEMORY ................................................................................... 17
5.1 - OVERVIEW ................................................................................................................ 17
5.2 - OPERATIONAL OVERVIEW ...................................................................................... 17
5.3 - ARCHITECTURAL DESCRIPTION ............................................................................ 19
5.3.1 - Read Mode ................................................................................................................. 19
5.3.2 - Command Mode ......................................................................................................... 19
5.3.3 - Ready/Busy Signal ..................................................................................................... 19
5.3.4 - Flash Status Register ................................................................................................. 19
5.3.5 - Flash Protection Register ........................................................................................... 21
5.3.6 - Instructions Description .............................................................................................. 21
5.3.7 - Reset Processing and Initial State .............................................................................. 25
5.4 - FLASH MEMORY CONFIGURATION ........................................................................ 25
5.5 - APPLICATION EXAMPLES ....................................................................................... 25
5.5.1 - Handling of Flash Addresses ...................................................................................... 25
5.5.2 - Basic Flash Access Control ........................................................................................ 26
5.5.3 - Programming Examples ............................................................................................. 27
5.6 - BOOTSTRAP LOADER ............................................................................................ 30
5.6.1 - Entering the Bootstrap Loader .................................................................................... 30
5.6.2 - Memory Configuration After Reset ............................................................................. 31
5.6.3 - Loading the Startup Code ........................................................................................... 32
5.6.4 - Exiting Bootstrap Loader Mode .................................................................................. 32
5.6.5 - Choosing the Baud Rate for the BSL ......................................................................... 33
6 - CENTRAL PROCESSING UNIT (CPU) ..................................................................... 34
6.1 - MULTIPLIER-ACCUMULATOR UNIT (MAC) ............................................................. 35
6.1.1 - Features ..................................................................................................................... 36
6.1.1.1 - Enhanced Addressing Capabilities .............................................................................. 36
6.1.1.2 - Multiply-Accumulate Unit ............................................................................................. 36
6.1.1.3 - Program Control .......................................................................................................... 36
6.2 - INSTRUCTION SET SUMMARY ................................................................................ 37
6.3 - MAC COPROCESSOR SPECIFIC INSTRUCTIONS ................................................. 38
7 - EXTERNAL BUS CONTROLLER .............................................................................. 42
7.1 - PROGRAMMABLE CHIP SELECT TIMING CONTROL ............................................ 42
7.2 - READY PROGRAMMABLE POLARITY ..................................................................... 42
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TABLE OF CONTENTS PAGE
8 - INTERRUPT SYSTEM ............................................................................................... 44
8.1 - EXTERNAL INTERRUPTS ......................................................................................... 44
8.2 - INTERRUPT REGISTERS AND VECTORS LOCATION LIST .................................. 45
8.3 - INTERRUPT CONTROL REGISTERS ....................................................................... 46
8.4 - EXCEPTION AND ERROR TRAPS LIST ................................................................... 47
9 - CAPTURE/COMPARE (CAPCOM) UNITS ................................................................ 48
10 - GENERAL PURPOSE TIMER UNIT .......................................................................... 51
10.1 - GPT1 .................................................................................................................... ...... 51
10.2 - GPT2 .......................................................................................................................... 52
11 - PWM MODULE .......................................................................................................... 54
12 - PARALLEL PORTS ................................................................................................... 55
12.1 - INTRODUCTION ........................................................................................................ 55
12.2 - I/O’S SPECIAL FEATURES ....................................................................................... 57
12.2.1 - Open Drain Mode ....................................................................................................... 57
12.2.2 - Input Threshold Control ............................................................................................ 57
12.2.3 - Output Driver Control ................................................................................................58
12.2.4 - Alternate Port Functions ............................................................................................. 60
12.3 - PORT0 ........................................................................................................................ 61
12.3.1 - Alternate Functions of PORT0 .................................................................................... 62
12.4 - PORT1 ........................................................................................................................ 64
12.4.1 - Alternate Functions of PORT1 .................................................................................... 64
12.5 - PORT 2 ....................................................................................................................... 66
12.5.1 - Alternate Functions of Port 2 ...................................................................................... 66
12.6 - PORT 3 ....................................................................................................................... 69
12.6.1 - Alternate Functions of Port 3 ...................................................................................... 70
12.7 - PORT 4 ....................................................................................................................... 73
12.7.1 - Alternate Functions of Port 4 ...................................................................................... 74
12.8 - PORT 5 ....................................................................................................................... 77
12.8.1 - Alternate Functions of Port 5 ...................................................................................... 78
12.8.2 - Port 5 Schmitt Trigger Analog Inputs .......................................................................... 79
12.9 - PORT 6 ....................................................................................................................... 79
12.9.1 - Alternate Functions of Port 6 ...................................................................................... 80
12.10 - PORT 7 ....................................................................................................................... 83
12.10.1 - Alternate Functions of Port 7 ...................................................................................... 84
12.11 - PORT 8 ....................................................................................................................... 87
12.11.1 - Alternate Functions of Port 8 ...................................................................................... 88
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TABLE OF CONTENTS PAGE
13 - A/D CONVERTER ...................................................................................................... 90
14 - SERIAL CHANNELS ................................................................................................. 91
14.1 - ASYNCHRONOUS / SYNCHRONOUS SERIAL INTERFACE (ASCO) .................... 91
14.1.1 - ASCO in Asynchronous Mode .................................................................................... 91
14.1.2 - ASCO in Synchronous Mode ...................................................................................... 93
14.2 - HIGH SPEED SYNCHRONOUS SERIAL CHANNEL (SSC) ..................................... 95
15 - CAN MODULES ......................................................................................................... 97
15.1 - CAN MODULES MEMORY MAPPING ...................................................................... 97
15.1.1 - CAN1 .......................................................................................................................... 97
15.1.2 - CAN2 .......................................................................................................................... 97
15.2 - CAN BUS CONFIGURATIONS .................................................................................. 97
16 - REAL TIME CLOCK .................................................................................................. 99
16.1 - RTC REGISTERS ...................................................................................................... 100
16.1.1 - RTCCON: RTC Control Register ................................................................................ 100
16.1.2 - RTCPH & RTCPL: RTC PRESCALER Registers ....................................................... 101
16.1.3 - RTCDH & RTCDL: RTC DIVIDER Counters .............................................................. 101
16.1.4 - RTCH & RTCL: RTC Programmable COUNTER Registers ....................................... 102
16.1.5 - RTCAH & RTCAL: RTC ALARM Registers ................................................................ 103
16.2 - PROGRAMMING THE RTC ....................................................................................... 103
17 - WATCHDOG TIMER .................................................................................................. 105
18 - SYSTEM RESET ........................................................................................................ 107
18.1 - LONG HARDWARE RESET ...................................................................................... 107
18.1.1 - Asynchronous Reset .................................................................................................. 107
18.1.2 - Synchronous Reset (RSTIN pulse > 1040TCL and RPD pin at high level) ................ 108
18.1.3 - Exit of Long Hardware Reset ...................................................................................... 109
18.2 - SHORT HARDWARE RESET .................................................................................... 109
18.3 - SOFTWARE RESET .................................................................................................. 110
18.4 - WATCHDOG TIMER RESET ..................................................................................... 110
18.5 - RSTOUT, RSTIN, BIDIRECTIONAL RESET ............................................................ 111
18.5.1 - RSTOUT Pin ............................................................................................................... 111
18.5.2 - Bidirectional Reset ...................................................................................................... 111
18.5.3 - RSTIN pin ................................................................................................................... 111
18.6 - RESET CIRCUITRY ................................................................................................... 111
19 - POWER REDUCTION MODES ................................................................................. 114
19.1 - IDLE MODE ................................................................................................................114
19.2 - POWER DOWN MODE .............................................................................................. 114
19.2.1 - Protected Power Down Mode ..................................................................................... 114
19.2.2 - Interruptable Power Down Mode ................................................................................ 114
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TABLE OF CONTENTS PAGE
20 - SPECIAL FUNCTION REGISTER OVERVIEW ......................................................... 117
20.1 - IDENTIFICATION REGISTERS ................................................................................. 123
20.2 - SYSTEM CONFIGURATION REGISTERS ................................................................ 124
21 - ELECTRICAL CHARACTERISTICS ......................................................................... 131
21.1 - ABSOLUTE MAXIMUM RATINGS ............................................................................. 131
21.2 - PARAMETER INTERPRETATION ............................................................................. 131
21.3 - DC CHARACTERISTICS ........................................................................................... 131
21.3.1 - A/D Converter Characteristics .................................................................................... 134
21.3.2 - Conversion Timing Control ....................................................................................... 135
21.4 - AC CHARACTERISTICS ............................................................................................ 136
21.4.1 - Test Waveforms .......................................................................................................136
21.4.2 - Definition of Internal Timing ........................................................................................ 136
21.4.3 - Clock Generation Modes ............................................................................................ 137
21.4.4 - Prescaler Operation ....................................................................................................138
21.4.5 - Direct Drive ................................................................................................................. 138
21.4.6 - Oscillator Watchdog (OWD) ....................................................................................... 138
21.4.7 - Phase Locked Loop .................................................................................................... 138
21.4.8 - External Clock Drive XTAL1 ....................................................................................... 139
21.4.9 - Memory Cycle Variables ............................................................................................. 140
21.4.10 - Multiplexed Bus .......................................................................................................... 141
21.4.11 - Demultiplexed Bus ...................................................................................................... 147
21.4.12 - CLKOUT and READY ................................................................................................. 153
21.4.13 - External Bus Arbitration ..............................................................................................155
21.4.14 - High-Speed Synchronous Serial Interface (SSC) Timing ........................................... 157
21.4.14.1 Master Mode................................................................................................................ 157
21.4.14.2 Slave mode.................................................................................................................. 158
22 - PACKAGE MECHANICAL DATA ........................................................................... 159
23 - ORDERING INFORMATION ...................................................................................... 159

Partno	Mfg	Dc	Qty	Available	Descript
ST10F269	ST	N/a	1477	avai	16-BIT MCU SINGLE VOLTAGE SUPPLY