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SSTUM32868ET ,1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applicationsApplicationsn 400 MT/s to 800 MT/s high-density (for example, 2 rank by 4) DDR2 registered DIMMsn D ..
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SSTUM32868ET
1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications
General descriptionThe SSTUM32868isa 1.8V 28-bit1:2 register speciﬁcally designedfor useon two rank four (2R×4) and similar high-density Double Data Rate2 (DDR2) memory modules.It
is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the
functionalityof the normally required two registersina single package, thereby freeingup
board real-estate and facilitating routing to accommodate high-density Dual In-line
Memory Module (DIMM) designs.
The SSTUM32868 also integrates a parity function, which accepts a parity bit from the
memory controller, compares it with the data received on the D-inputs and indicates
whether a parity error has occurred on its open-drain PTYERR pin (active LOW).
It further offers added features over the JEDEC standard register in that it is permanently
conﬁgured for high output drive strength. This allows use in high density designs with
heavier than normal net loading conditions. Furthermore, the SSTUM32868 features two
additional chip select inputs, which allow more versatile enabling and disablingin densely
populated memory modules. Both added features (drive strength and chip selects) are
fully backward compatible to the JEDEC standard register. Finally, the SSTUM32868 is
optimized for the fastest propagation delay in the SSTU family of registers.
The SSTUM32868 is packaged in a 176-ball, 8× 22 grid, 0.65 mm ball pitch, thin proﬁle
ﬁne-pitch ball grid array (TFBGA) package, which (while requiring a minimum
6mm×15 mm of board space) allows for adequate signal routing and escape using
conventional card technology. Features 28-bit data register supporting DDR2 Fully compliant to JEDEC standard for SSTUB32868 Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two
JEDEC-standard DDR2 registers (that is, 2× SSTUA32864 or 2× SSTUA32866) Parity checking function across 22 input data bits Parity out signal Controlled multi-impedance output impedance drivers enable optimal signal integrity
and speed Meets or exceeds SSTUB32868 JEDEC standard speed performance Supports up to 450 MHz clock frequency of operation Permanently conﬁgured for high output drive Optimized pinout for high-density DDR2 module design Chip-selects minimize power consumption by gating data outputs from changing state
SSTUM32868
1.8 V 28-bit 1 : 2 conﬁgurable registered buffer with parity for
DDR2-800 RDIMM applications
Rev. 02 — 2 March 2007 Product data sheet
NXP Semiconductors SSTUM32868
1.8 V DDR2-800 conﬁgurable registered buffer with parity Two additional chip select inputs allow optional ﬂexible enabling and disabling Supports Stub Series T erminated Logic SSTL_18 data inputs Differential clock (CK and CK) inputs Supports Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS)
switching levels on the control and RESET inputs Single 1.8 V supply operation (1.7 V to 2.0V) Available in 176-ball 6 mm×15 mm, 0.65 mm ball pitch TFBGA package Applications 400 MT/sto 800 MT/s high-density (for example,2 rankby4) DDR2 registered DIMMs DDR2 Registered DIMMs (RDIMM) desiring parity checking functionality Ordering information
4.1 Ordering options
Table 1. Ordering information
SSTUM32868ET/G Pb-free (SnAgCu solder ball
compound)
TFBGA176 plastic thin ﬁne-pitch ball grid array package;
176 balls; body 6×15× 0.7 mm
SOT932-1
SSTUM32868ET/S Pb-free (SnAgCu solder ball
compound)
TFBGA176 plastic thin ﬁne-pitch ball grid array package;
176 balls; body 6×15× 0.7 mm
SOT932-1
Table 2. Ordering options
SSTUM32868ET/G Tamb = 0 °C to +70°C
SSTUM32868ET/S Tamb = 0 °C to +85°C
NXP Semiconductors SSTUM32868
1.8 V DDR2-800 conﬁgurable registered buffer with parity Functional diagram
NXP Semiconductors SSTUM32868
1.8 V DDR2-800 conﬁgurable registered buffer with parity
NXP Semiconductors SSTUM32868
1.8 V DDR2-800 conﬁgurable registered buffer with parity Pinning information
6.1 Pinning
NXP Semiconductors SSTUM32868
1.8 V DDR2-800 conﬁgurable registered buffer with parity
NXP Semiconductors SSTUM32868
1.8 V DDR2-800 conﬁgurable registered buffer with parity
NXP Semiconductors SSTUM32868
1.8 V DDR2-800 conﬁgurable registered buffer with parity
6.2 Pin description
Table 3. Pin description
Ungated inputs
DCKE0 D1 W1 SSTL_18 The outputs of this register will not be
suspended by the DCS0 and DCS1
control.DCKE1 C1 Y1
DODT0 N1 K1 SSTL_18 The outputs of this register will not be
suspended by the DCS0 and DCS1
control.DODT1 P1 J1
Chip Select gated inputsto
D28
A2, A1, B2, B1, C2, C1,
D2, D1, E1, F1, G1, H1,
N1, P1, R1, T1, U1, V1,
W1, W2, Y1, Y2, AA1,
AA2, AB1, AB2
A2, A1, B2, B1, C2, C1,
D2, D1, E1, F1, G1, H1,J1,
K1, N1, P1, R1, T1, U1,
V1, W1, W2, Y1, Y2, AA1,
AA2, AB1, AB2
SSTL_18 Data inputs, clockedinon the crossingof
the rising edge of CD and the falling
edge of CK.
Chip Select inputs
DCS0 K1 N1 SSTL_18 Chip select inputs. These pins initiate
DRAM address/command decodes, and suchat least one willbe LOW whena
valid address/command is present. The
register can be programmed to re-drive
all D-inputs (CSGEN= HIGH) only when
at least one chip select input is LOW. If
CSGEN, DCS0 and DCS1 inputs are
HIGH, D1 to D28[1]
disabled.
DCS1 J1 P1
DCS2 K3 K3
DCS3 P3 P3
Conﬁguration control inputs A3 A3 LVCMOS
input
Conﬁguration control inputs; Register A
or RegisterB
Re-driven outputs
Q1Ato
Q28A
A7, B7, C7, D7, E7, E2, F7,
F2, G7, G2, H7, H2, N2,
P2, R2, R7, T2, T7, U2,
U7, V2, V7, W7, Y7, AA7,
AB7
A7, B7, C7, D7, E7, E2, F7,
F2, G7, G2, H7, H2, J2,
K2, N2, P2, R2, R7, T2, T7,
U2, U7, V2, V7, W7, Y7,
AA7, AB7
1.8V
CMOS
outputs
Data outputs[2]
the DCS0 and DCS1 control.
Q1Bto
Q28B
A8, B8, C8, D8, E8, F8,
G8, H8,J8,J7, K8, K7, L8,
L7, M7, M8, N7, N8, P7,
P8, R8, T8, V8, U8, W8,
Y8, AA8, AB8
A8, B8, C8, D8, E8, F8,
G8, H8,J8,J7, K8, K7, L8,
L7, M7, M8, N7, N8, P7,
P8, R8, T8, U8, V8, W8,
Y8, AA8, AB8
QCS0A K2 N2 1.8V
CMOS
outputs
Data outputs that will not be suspended
by the DCS0 and DCS1 control.QCS0B L7 M7
QCS1A J2 P2
QCS1B L8 M8
NXP Semiconductors SSTUM32868
1.8 V DDR2-800 conﬁgurable registered buffer with parity
QCKE0A F2 U2 1.8V
CMOS
outputs
Data outputs that will not be suspended
by the DCS0 and DCS1 control.QCKE0B H8 R8
QCKE1A E2 V2
QCKE1B F8 U8
QODT0A N2 K2 1.8V
CMOS
outputs
Data outputs that will not be suspended
by the DCS0 and DCS1 control.QODT0B M7 L7
QODT1A P2 J2
QODT1B M8 L8
Output error
QERR M3 M3 open-drain
output
Output error bit; generated on clock
cycle after the corresponding data
output.
Parity input
PAR_IN L3 L3 SSTL_18 Parity input. Arrives one clock cycle after
the corresponding data input.
Program inputs
CSGEN L2 L2 LVCMOS
input
Chip select gate enable. When HIGH,
the D1to D28[1]
only when at least one chip select input
is LOW during the rising edge of the
clock. When LOW, the D1to D28[1]
inputs will be latched and re-driven on
every rising edge of the clock.
Clock inputs L1 L1 differential
input
Positive master clock input. M1 M1 differential
input
Negative master clock input.
Miscellaneous inputs
RESET M2 M2 LVCMOS
input
Asynchronous reset input. Resets
registers and disables VREF data and
clock differential-input receivers.
Table 3. Pin description …continued
NXP Semiconductors SSTUM32868
1.8 V DDR2-800 conﬁgurable registered buffer with parity
[1] Data inputs = D1 to D5, D7, D9 to D12, D17 to D28 when C=0.
Data inputs = D1 to D12, D17 to D20, D22, D24 to D28 when C=1.
[2] Data outputs = Q1x to Q5x, Q7x, Q9x to Q12x, Q17x to Q28x when C=0.
Data outputs = Q1x to Q12x, Q17x to Q20x, Q22x, Q24x to Q28x when C = 1. Functional description
7.1 Function table
VREF A5, AB5 A5, AB5 0.9V
nominal
Input reference voltage.
VDD B3, B4, B5, B6, D3, D4,
D5, D6, F3, F4, F5, F6, H3,
H4, H5, H6, K4, K5, K6,
M4, M5, M6, P4, P5, P6,
T3, T4, T5, T6, V3, V4, V5,
V6, Y3, Y4, Y5, Y6, AB4,
AB6
B3, B4, B5, B6, D3, D4,
D5, D6, F3, F4, F5, F6, H3,
H4, H5, H6, K4, K5, K6,
M4, M5, M6, P4, P5, P6,
T3, T4, T5, T6, V3, V4, V5,
V6, Y3, Y4, Y5, Y6, AB4,
AB6
1.8V
nominal
Power supply voltage.
GND A4, A6, C3, C4, C5, C6,
E3, E4, E5, E6, G3, G4,
G5, G6, J3, J4, J5, J6, L4,
L5, L6, N3, N4, N5, N6, R3,
R4, R5, R6, U3, U4, U5,
U6, W3,W4, W5, W6, AA3,
AA4, AA5, AA6
A4, A6, C3, C4, C5, C6,
E3, E4, E5, E6, G3, G4,
G5, G6, J3, J4, J5, J6, L4,
L5, L6, N3, N4, N5, N6, R3,
R4, R5, R6, U3, U4, U5,
U6, W3,W4, W5, W6, AA3,
AA4, AA5, AA6
ground
input
Ground.
Table 3. Pin description …continued
Table 4. Function table (each ﬂip-ﬂop)
NXP Semiconductors SSTUM32868
1.8 V DDR2-800 conﬁgurable registered buffer with parity
[1] Q0 is the previous state of the associated output.
[2] DCS2 and DCS3 operate identically to DCS0 and DCS1, except they do not have corresponding re-driven (QCS) outputs.
[1] DCS2 and DCS3 operate identically to DCS0 and DCS1 with regard to the parity function.
[2] PAR_IN arrives one clock cycle after the data to which it applies.
[3] This transition assumes QERRis HIGHatthe crossingofCK going HIGH andCK going LOW.If QERRis LOW,it stays latched LOWfor
two clock cycles or until RESET is driven LOW.
[4] QERR0 is the previous state of output QERR.
[5]If DCS0, DCS1, DCS2, DCS3 and CSGENare driven HIGH,the deviceis placedin Low-Power Mode (LPM).Ifa parity error occurson
the clock cycle before the device enters the LPM and the QERR output is driven LOW, it stays latched LOW for the LPM duration plus
two clock cycles or until RESET is driven LOW.
7.2 Functional information
The SSTUM32868 is a 28-bit 1: 2 conﬁgurable registered buffer designed for 1.7 V to
1.9 V VDD operation.
All inputs are compatible with the JEDEC standard for SSTL_18, except the chip-select
gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are L VCMOS. All
outputs are edge-controlled circuits optimized for unterminated DIMM loads, and meet
SSTL_18 speciﬁcations, except the open-drain error (QERR) output.
Table 4. Function table (each ﬂip-ﬂop) …continued
Table 5. Parity and standby function table
NXP Semiconductors SSTUM32868
1.8 V DDR2-800 conﬁgurable registered buffer with parity
The device supports low-power standby operation. When RESET is LOW, the differential
input receivers are disabled, and undriven (ﬂoating) data, clock, and reference voltage
(VREF) inputs are allowed. In addition, when RESET is LOW, all registers are reset and
all outputs are forced LOW except QERR. The LVCMOS RESET and C inputs always
must be held at a valid logic HIGH or LOW level.
To ensure deﬁned outputs from the register before a stable clock has been supplied,
RESET must be held in the LOW state during power-up. the DDR2 RDIMM application, RESETis speciﬁedtobe completely asynchronous with
respectto CK and CK. Therefore,no timing relationship canbe ensured between the two.
When entering reset, the register will be cleared and the data outputs will be driven LOW
quickly, relative to the time to disable the differential input receivers. However, when
coming out of reset, the register will become active quickly, relative to the time to enable
the differential input receivers.As longas the data inputs are LOW, and the clockis stable
during the time from the LOW-to-HIGH transition of RESET until the input receivers are
fully enabled, the design of the SSTUM32868 must ensure that the outputs will remain
LOW, thus ensuring no glitches on the output.
The SSTUM32868 includes a parity checking function. Parity, which arrives one cycle
after the data input to which it applies, is checked on the PAR_IN input of the device. The
corresponding QERR output signal for the data inputs is generated two clock cycles after
the data, to which the QERR signal applies, is registered.
The SSTUM32868 accepts a parity bit from the memory controller on the parity bit AR_IN) input, compares it with the data received on the DIMM-independent D inputs
(D1to D5, D7, D9to D12, D17to D28 whenC=0;or D1to D12, D17to D20, D22, D24to
D28 when C= 1) and indicates whether a parity error has occurred on the open-drain
QERR pin (active LOW). The conventionis even parity, thatis, valid parityis deﬁnedasan
even numberof ones across the DIMM-independent data inputs combined with the parity
input bit.To calculate parity,all DIMM-independentD inputs mustbe tiedtoa known logic
state.
If an error occurs and the QERR output is driven LOW, it stays latched LOW for a
minimum of two clock cycles or until RESET is driven LOW. If two or more consecutive
parity errors occur, the QERR outputis driven LOW and latched LOWfora clock duration
equalto the parity error durationor until RESETis driven LOW.Ifa parity error occurson
the clock cycle before the device enters the Low-Power Mode (LPM) and the QERR
outputis driven LOW, thenit stays latched LOWfor the LPM duration plus two clock cycles
or until RESET is driven LOW. The DIMM-dependent signals (DCKE0, DCKE1, DODT0,
DODT1, DCS0, DCS1, DCS2 and DCS3) are not included in the parity check
computation.
TheC input controls the pinout conﬁguration from RegisterA conﬁguration (when LOW)to
RegisterB conﬁguration (when HIGH). TheC input should notbe switched during normal
operation.It shouldbe hard-wiredtoa valid LOWor HIGH levelto conﬁgure the registerin
the desired mode.
The device also supports low-power active operation by monitoring both system chip
select (DCS0, DCS1, DCS2 and DCS3) and CSGEN inputs and will gate the Qn outputs
from changing states when CSGEN, DCS0 and DCS1 inputs are HIGH. If CSGEN or the
DCSn inputs are LOW, the Qn outputs will function normally. Also, if all DCSn inputs are
HIGH, the device will gate the QERR output from changing states.If anyof the DCSn are
NXP Semiconductors SSTUM32868
1.8 V DDR2-800 conﬁgurable registered buffer with parity
LOW, the QERR output will function normally. The RESET input has priority over the
DCSn control, and when driven LOW will force the Qn outputs LOW and the QERR output
HIGH. If the chip-select control functionality is not desired, then the CSGEN input can be
hard-wired to ground (GND), in which case the set-up time requirement for DCSn would
be the same as for the other D data inputs. T o control the Low-power mode with DCSn
only, the CSGEN input should be pulled up to VDD through a pull-up resistor.
The two VREF pins (A5 and AB5) are connected together internally by approximately
150Ω. However,itis necessaryto connect only oneof the two VREF pinsto the external
Vref power supply. An unused VREF pin should be terminated with a Vref coupling
capacitor.
The SSTUM32868 is available in a TFGBA176 package.
NXP Semiconductors SSTUM32868
1.8 V DDR2-800 conﬁgurable registered buffer with parity
7.3 Register timing
NXP Semiconductors SSTUM32868
1.8 V DDR2-800 conﬁgurable registered buffer with parity

Partno	Mfg	Dc	Qty	Available	Descript
SSTUM32868ET	NXP	N/a	2710	avai	1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications