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SSTUH32865ET
1.8 V 28-bit high output drive 1:2 registered buffer with parity for DDR2 RDIMM applications
General descriptionThe SSTUH32865 is a 1.8 V 28-bit high output drive 1:2 register specifically designed for
use on two rank by four (2R× 4) and similar high-density Double Data Rate 2 (DDR2)
memory modules.Itis similarin functionto the JEDEC-standard 14-bit DDR2 register, but
integrates the functionality of the normally required two registers in a single package,
thereby freeing up board real-estate and facilitating routing to accommodate high-density
Dual In-line Memory Module (DIMM) designs.
The SSTUH32865 also integrates a parity function, which accepts a parity bit from the
memory controller, compares it with the data received on the D-inputs and indicates
whether a parity error has occurred on its open-drain PTYERR pin (active LOW).
The SSTUH32865 is packaged in a 160-ball, 12× 18 grid, 0.65 mm ball pitch, thin profile
fine-pitch ball grid array (TFBGA) package, which—while requiring a minimum
9mm×13 mm of board space—allows for adequate signal routing and escape using
conventional card technology.
The SSTUH32865 is identical to SSTU32865 in function and performance, with
higher-drive outputs optimized to drive heavy load nets (such as stacked DRAMs) while
maintaining speed and signal integrity.
Features 28-bit data register supporting DDR2 Higher output drive strength version of SSTU32865 optimized for high-capacitive load
nets Fully compliant to JEDEC standard JESD82-9 Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two
JEDEC-standard DDR2 registers (that is, 2× SSTU32864 or 2× SSTU32866) Parity checking function across 22 input data bits Parity out signal Controlled output impedance drivers enable optimal signal integrity and speed Exceeds JESD82-9 speed performance (1.8 ns max. single-bit switching propagation
delay, 2.0 ns max. mass-switching) Supports up to 450 MHz clock frequency of operation Optimized pinout for high-density DDR2 module design Chip-selects minimize power consumption by gating data outputs from changing state Supports Stub Series T erminated Logic SSTL_18 data inputs Differential clock (CK and CK) inputs
SSTUH32865
1.8 V 28-bit high output drive 1:2 registered buffer with parity
for DDR2 RDIMM applications
Philips Semiconductors SSTUH32865 Supports Low Voltage Complementary Metal Oxide Silicon (LVCMOS) switching levels
on the control and RESET inputs Single 1.8 V supply operation Available in 160-ball 9 mm×13 mm, 0.65 mm ball pitch TFBGA package
Applications High-density (for example, 2 rank by 4) DDR2 registered DIMMs DDR2 Registered DIMMs (RDIMM) desiring parity checking functionality Stacked or planar high-DRAM count registered DIMMs
Ordering information
Table 1: Ordering informationSSTUH32865ET/G Pb-free (SnAgCu solder ball
compound)
TFBGA160 plastic thin fine-pitch ball grid array package;
160 balls; body 9×13× 0.8 mm
SOT802-1
SSTUH32865ET SnPb solder ball compound TFBGA160 plastic thin fine-pitch ball grid array package;
160 balls; body 9×13× 0.8 mm
SOT802-1
Philips Semiconductors SSTUH32865 Functional diagram
Philips Semiconductors SSTUH32865 Pinning information
6.1 Pinning
Philips Semiconductors SSTUH32865
Philips Semiconductors SSTUH32865
6.2 Pin description
Table 2: Pin description
Ungated inputsDCKE0, DCKE1 U1, U2 SSTL_18 DRAM function pins not associated with Chip Select.
DODT0, DODT1 T2, T1
Chip Select gated inputsto D21 M1, B1, B2, C1, C2, D2, D1,
E1, E2, F2, M2, F1, G2, R1,
L2, H2, N2, N1, G1, P1, R2,
SSTL_18 DRAM inputs, re-driven only when Chip Select is LOW.
Chip Select inputsDCS0, DCS1 J2, K2 SSTL_18 DRAM Chip Select signals. These pins initiate DRAM
address/command decodes, andas suchat least one will
be LOW when a valid address/command is present. The
register can be programmed to re-drive all D-inputs only
(CSGATEEN= HIGH) when at least one Chip Select
input is LOW.
Re-driven outputsQ0Ato Q21A V11, F12, G12, V6, V9, H12,
L12, V8, V12, N12, M12,
P12, V7, V10, T12, R12,
E12, A12, A10, A9, D12, A8
SSTL_18 Outputs of the register, valid after the specified clock
count and immediately following a rising edge of the
clock.
Q0Bto Q21B U11, F11, G11, U6, U9,
H11, L11, U8, U12, N11,
M11, P11, U7, U10, T11,
R11, E11, A11, B10, B9,
D11, B8
QCS0A, QDS1A,
QCS0B, QCS1B
J12, K12, J11, K11
QCKE0A, QCKE1A,
QCKE0B, QCKE1B
A7, A6, B7, B6
QODT0A, QODT1A,
QODT0B, QODT1B
B12, C12, B11, C11
Parity inputPARIN A3 SSTL_18 Parity input for the D0to D21 inputs. Arrives one clock
cycle after the corresponding data input.
Parity errorPTYERR U4 open drain When LOW, this output indicates that a parity error was
identified associated with the address and/or command
inputs. PTYERR will be active for two clock cycles, and
delayedbyan additional clock cyclefor compatibility with
final parity out timing on the industry-standard DDR2
register with parity (in JEDEC definition).
Program inputsCSGATEEN H1 1.8V
LVCMOS
Chip Select Gate Enable. When HIGH, the D0to D21
inputs will be latched only when at least one Chip Select
input is LOW during the rising edge of the clock. When
LOW, the D0to D21 inputs will be latched and redriven
on every rising edge of the clock.
Philips Semiconductors SSTUH32865
Clock inputsCK, CK J1, K1 SSTL_18 Differential master clock input pair to the register. The
register operation is triggered by a rising edge on the
positive clock input (CK).
Miscellaneous inputsm.c.l. U3, V2, V3 Must be connected to a logic LOW
m.c.h. U5, V5 Must be connected to a logic HIGH.
RESET L1 1.8V
LVCMOS
Asynchronous reset input. When LOW, it causes a reset
of the internal latches, thereby forcing the outputs LOW.
RESET also resets the PTYERR signal.
VREF A1, V1 0.9V
nominal
Input reference voltageforthe SSTL_18 inputs. Two pins
(internally tied together) are used for increased reliability.
VDDL D4, E4, E6, F4, G4, H4, K4,
K5, N4, N5, P5, P6, R5, R6
power supply voltage
VDDR E7, F8, F9, G8, G9, J8, J9,
L8, L9, N8, N9, P7, P8
power supply voltage
GND D5, D8, D9, E5, E8, E9, F5,
G5, H5, H8, H9, J4, J5, K8,
K9, L4, L5, M4, M5, M8, M9,
P4, P9, R4, R7, R8, R9
ground
n.c. A2, A4, A5, B3, B4, B5, D6,
D7, V4
ball present but not connected to die
Table 2: Pin description …continued
Philips Semiconductors SSTUH32865 Functional description
7.1 Function table[1] Q0 is the previous state of the associated output.
[1] PARIN arrives one clock cycle afterthe datato whichit applies.AllDn inputs mustbe driventoa known statefor paritytobe calculated
correctly.
Table 3: Function table (each flip-flop) L X ↑↓ LL L L L L X ↑↓ HH L L H L L X L or H L or H X Q0 Q0 Q0 Q0 H X ↑↓ LL L H L H X ↑↓ HH L H H L H X L or H L or H X Q0 Q0 Q0 Q0 L X ↑↓ LL H L L L X ↑↓ HH H L H H L X L or H L or H X Q0 Q0 Q0 Q0 H L ↑↓ LL H H L H L ↑↓ HH H H H H H L L or H L or H X Q0 Q0 Q0 Q0 H H ↑↓ LQ0 HH L H H ↑↓ HQ0 HH H H H H L or H L or H X Q0 Q0 Q0 Q0 X or
floating
X or
floating
X or floating X or
floating
X or
floating
X or floating L L L L
Table 4: Parity and standby function table H ↑↓ even L H H ↑↓ odd L L H ↑↓ even H L H ↑↓ odd H H L ↑↓ even L H L ↑↓ odd L L L ↑↓ even H L L ↑↓ odd H H H ↑↓ XX PTYERR0 X X L or H L or H X X PTYERR0 X or floating X or floating X or floating X or floating X or floating X or floating H
Philips Semiconductors SSTUH32865[2] This condition assumes PTYERR is HIGH at the crossing of CK going HIGH and CK going LOW. If PTYERR is LOW, it stays latched
LOW for two clock cycles or until RESET is driven LOW.
CSGATEEN is ‘don’t care’ for PTYERR.
[3] PTYERR0 is the previous state of output PTYERR.
7.2 Functional informationThis 28-bit 1:2 registered buffer with parity is designed for 1.7 V to 1.9 V VDD operation.
All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The
control inputs are LVCMOS.All outputs are 1.8V CMOS drivers that have been optimized
to drive the DDR2 DIMM load.
The SSTUH32865 operates from a differential clock (CK and CK). Data are registered at
the crossing of CK going HIGH, and CK going LOW.
The device supports low-power standby operation. When the reset input (RESET)is LOW,
the differential input receivers are disabled, and undriven (floating) data, clock and
reference voltage (VREF) inputs are allowed.In addition, when RESETis LOWall registers
are reset, and all outputs except PTYERR are forced LOW. The LVCMOS RESET input
must always be held at a valid logic HIGH or LOW level.
To ensure defined outputs from the register before a stable clock has been supplied,
RESET must be held in the LOW state during power-up. the DDR2 RDIMM application, RESETis specifiedtobe completely asynchronous with
respect to CK and CK. Therefore, no timing relationship can be guaranteed between the
two. When entering reset, the register will be cleared and the data outputs will be driven
LOW quickly, relativeto the timeto disable the differential input receivers. However, when
coming out of reset, the register will become active quickly, relative to the time to enable
the differential input receivers.As longas the data inputs are LOW, and the clockis stable
during the time from the LOW-to-HIGH transition of RESET until the input receivers are
fully enabled, the designof the SSTUH32865 ensures that the outputs remain LOW, thus
ensuring no glitches on the output.
The device monitors both DCS0 and DCS1 inputs and will gate the Qn outputs from
changing states when both DCS0 and DCS1 are HIGH. If either DCS0 or DCS1 input is
LOW, the Qn outputs will function normally. The RESET input has priority over the DCS0
and DCS1 control and will force the Qn outputs LOW and the PTYERR output HIGH.If the
DCSn-control functionality is not desired, then the CSGATEEN input can be hardwired to
ground,in which case, the setup-time requirementfor DCSn wouldbe the sameasfor the
other Dn data inputs.
The SSTUH32865 includesa parity checking function. The SSTUH32865 acceptsa parity
bit from the memory controller at its input pin P ARIN, compares it with the data received
on the Dn inputs (with either DCS0 or DCS1 active) and indicates whether a parity error
has occurred on its open-drain PTYERR pin (active LOW).
Philips Semiconductors SSTUH32865
7.3 Functional differences to SSTU32864The SSTUH32865 for its basic register functionality, signal definition and performance is
based upon the industry-standard SSTU32864, but provides key operational features
which differ (at least in part) from the industry-standard register in the following aspects:
7.3.1 Chip Select (CS) gating of key inputs (DCS0, DCS1, CSGATEEN)a meansto reduce device power, the internal latches will onlybe updated when oneor
both of the CS inputs are active (LOW) and CSGATEEN HIGH at the rising edge of the
clock. The 22 ‘Chip-Select-gated’ input signals associated with this function include
addresses (ADDR0to ADDR15, BA0to BA2), and RAS, CAS, WE, with the remaining
signals (CS, CKE, ODT) continuously re-driven at the rising edge of every clock as they
are independent of CS. The CS gating function can be disabled by tying CSGA TEEN
LOW, enabling all internal latches to be updated on every rising edge of the clock.
7.3.2 Parity error checking and reportingThe SSTUH32865 incorporatesa parity function, whereby the signal receivedon input pin
PARINis receivedas parityto the register, one clock cycle later than the CS-gated inputs.
The received paritybitis then comparedto the parity calculated across these same inputs
by the register parity logic to verify that the information has not been corrupted. The 22
CS-gated input signals willbe latched and re-drivenon the first clock, and any error willbe
reported one clock cycle later via the PTYERR output pin (driven LOWfor two consecutive
clock cycles). PTYERR is an open-drain output, allowing multiple modules to share a
common signal pin for reporting the occurrence of a parity error during a valid command
cycle (coincident with the re-driven signals). This outputis driven LOWfor two consecutive
clock cycles to allow the memory controller sufficient time to sense and capture the error
even. A LOW state on PTYERR indicates that a parity error has occurred.
7.3.3 Reset (RESET)Similarto the RESET pinon the industry-standard SSTU32864, this pinis usedto clearall
internal latches and all outputs will be driven LOW quickly except the PTYERR output,
which will be floated (and will normally default HIGH by their external pull-up).
7.3.4 Power-up sequenceThe reset function for the SSTUH32865 is similar to that of the SSTU32864 except that
the PTYERR signal is also cleared and will be held clear (HIGH) for three consecutive
clock cycles.
Table 5: Chip Select gating modeGating CSGATEEN
HIGH
Registers only re-drive signals to the DRAMs when
Chip Select inputs are LOW.
Non-gating CSGATEEN
LOW
Registers always re-drive signals on every clock cycle,
independent of the state of the Chip Select inputs.
Philips Semiconductors SSTUH32865
Philips Semiconductors SSTUH32865
Philips Semiconductors SSTUH32865
Philips Semiconductors SSTUH32865
